Solution-Processed Non-Volatile Organic Transistor Memory based on

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Solution-Processed Non-Volatile Organic Transistor Memory based on Semiconductor Blends Yonghan Park, Kang-Jun Baeg, and Choongik Kim ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b20571 • Publication Date (Web): 01 Feb 2019 Downloaded from http://pubs.acs.org on February 2, 2019

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ACS Applied Materials & Interfaces

Solution-Processed Non-Volatile Organic Transistor Memory based on Semiconductor Blends Yonghan Park,a,§, Kang-Jun Baeg,b,§ and Choongik Kima*

a

Department of Chemical and Biomolecular Engineering, 35 Baekbeom-ro, Mapo-gu,

Sogang University, Seoul 04107, Republic of Korea b

Department of Graphic Arts Information Engineering, 45 Yongso-ro, Nam-gu, Pukyong

National University, Busan 48513, Republic of Korea

§ These authors contributed equally to this work.

* Corresponding authors E-mail addresses: [email protected] (C. Kim)

Keywords: non-volatile memory; organic field-effect transistor; electret; solution process; memory ratio

1

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ABSTRACT Solution-processed non-volatile organic transistor memory devices are fabricated employing semiconductor blends of p-channel 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-PEN)

and

n-channel

oly{[N,N’-bis(2-octyldodecyl)-naphthalene-1,4,5,8-

bis(dicarboximide)-2,6-diyl]-alt-5,5’-(2,2’-bithiophene)}

(P(NDI2OD-2T);

N2200)

on

polystyrene-brush as a polymer electret. Electret-based memory characteristics are significantly changed depending on the frontier molecular orbitals of the active semiconductors because the charge trapping efficiency is mainly determined by energy barrier to transfer electrons and holes from active channel to electret layer. Semiconductor mixture with optimized blending ratio results in efficient programming and erasing process. Thus, we obtained a remarkably high ratio of ON/OFF current (memory ratio) about 107 and a large amount of shifts in the threshold voltage (memory window) between programmed and erased states of 43 V, whilst a single component N2200 showed only writing-once-read-many (WORM)-type memory. Especially, the programmed data can be stably retained more than 10 years with a sufficient memory ratio of 103. Furthermore, our semiconductor blend system leads to preferable vertical phase separation, which affords good reliability under sequential memory operation condition as well as stability in ambient air. It is expected that our memory devices can be applied as versatile data storage in printed and flexible electronic applications.

2


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1. INTRODUCTION Organic semiconducting materials have attracted tremendous interests due to their many promising properties such as intrinsic mechanical flexibility, simple and lowtemperature solution-process, and versatile capability to molecular tailoring in order to obtain the optimized electrical and/or optoelectronic properties. Versatile optoelectronic properties of conjugated organic molecules have been utilized to enable various applications, such as organic light-emitting diodes,1-3 organic field-effect transistors (OFETs),4-7 and organic photovoltaics (OPVs).8-9 Notably, these devices are basically using the fundamental functions of organic semiconductors, that is, charge recombination, transport, and generation. On the other hand, multi-functional devices simultaneously use at least two kinds of physical behaviour; for instance, phototransistors for sensors and transistor memory for solid-state data storage. Among them, OFET-based non-volatile memory (ONVM) devices have combined the charge storing in additional gate dielectric layers with switching behaviour of transistors. Thus, it could enable easy integration with peripheral driver circuits and efficient charge transfer and trapping within fast programming/erasing time, as well as stable retention and reliability. Data storage capability of ONVMs can be broadly applied to various electronic components, such as near field communication (NFC) or radio-frequency identification (RFID) tags, wearable devices, and disposable sensors, at which either short product information or user file is required to be stored in each product.10-13 For the ONVMs, chargeable layers are incorporated in the gate dielectric. Depending on the type of charge traps and polarization methods in the chargeable layers, ONVMs are classified into three different types: i) ferroelectric ONVMs,14-19 ii) floating-gate ONVMs,2035

and iii) charge trap ONVMs.36-57 The ferroelectric ONVMs employ ferroelectric materials 3



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as gate dielectric in which permanent dipoles are induced to align through the application of external gate fields, thereby exhibit two stable states of polarization. While ferroelectric memory has many potential advantages, ferroelectric polymers often suffer from rough surface morphology due to their semi-crystalline nature, slower programming/erasing time, and relatively short retention time in comparison to its counterparts.14 In floating-gate type ONVMs, metallic or semiconducting nanoparticles or nanowires are embedded in the dielectric layer. Uniform dispersion and spatial distribution of these nanomaterials are important to achieve high-density NVMs, but the formation of a uniform tunneling layer between the semiconductor and floating-gates are sometimes challenges to overcome.35 On the other hand, charge trap ONVMs with chargeable insulators (electrets) can easily be processed via simple solution process and exhibit excellent non-volatile memory performance.13, 57 Thus, charge trap ONVMs would be a promising component for reliable data storage in flexible and printed electronic products. To enable the high-performance electret-based ONVMs with all solution processes, it is strongly required to fabricate the memory devices with hydrophobic polymer electrets with relatively small band gap which have been known to afford high charge storage capability for a large memory window.42,

53

However, those non-polar and hydrophobic electrets were

commonly dissolved in organic solvents that are used to deposit organic semiconductor films by solution process. On the other hand, polar and hydrophilic electrets, such as poly(4-vinyl phenol) and poly(vinyl alcohol) generally showed poor memory characteristics due to trapped water, ions, and/or permanent dipoles in the dielectric layer.58-59 These hydrophilic moieties could increase the bulk conductivity, thereby decreasing the relaxation time of stored charges in the electrets. When the organic semiconducting layer is employed from solution process 4


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onto the polymer electret, it is often difficult to find an orthogonal solvent. Hence, there have hardly been any reports on ONVMs using solution-processed semiconductors in the bottomgate/top-contact configuration,56 although the bottom-gated OFETs have enough advantages to be fabricated. Notably, this is because the dielectric is deposited before the semiconductor is laid, so semiconductor does not have to withstand the sensitive environment when compared to the top-gated OFETs, which is a configuration where a dielectric must be deposited on semiconductors generally using organic solvents which can adversely affect the semiconductor layer.60 In addition, the bottom-gated ONVM readily enables dielectric layer stacking with a robust dielectric layer, i.e., high-k and/or inorganic insulators, in order to effectively trap the transferred charges only in electret layer by blocking the leakage current flow. Furthermore, electret-based ONVMs usually showed better memory performance when using p-channel semiconductors. As shown in Table 1, a representative vacuumdeposited p-type semiconductor, pentacene, has generally been employed for electret-based ONVMs with various polymer electrets, which showed decent memory characteristics with memory ratio of 104 – 106, memory window of 17 – 99 V, and retention time over 104. On the other hand, when n-channel semiconductor was used, such as N, N-bis(2-phenylethyl)perylene-3,4:9,10-tetracarboxylicdiimide (BPE-PTCDI), the resulting memory devices exhibited relatively poor performance. Although a few n-channel ONVMs were reported using polyimide or star-shaped polymers as an electret,36,43,49,50 high-performance and ambient-stable n-channel memory devices are currently rare. Therefore, it is important to deeply understand the operation mechanism for the electret-based ONVMs as well as to demonstrate

high-performance

memory

devices

with

solution-processed

n-channel 5



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semiconductors to fulfill the commercial requirements of next-generation soft data storage media.

Table 1. Memory Device Characteristics of Bottom-Gated Electret-Based ONVMs Depending on the Type of Semiconductors and Electret Materials. Organic Semiconductor

Type

p-type

a

pentacene

Electret Material

Mobility [cm2 V-1 s-1]

Memory Window [V]

Memory Ratio

Retention Time [s]

PVN PαMS PS PVP PVPyr P(St-Fl)a star-PTPMAb polyimide P(St-Fl): PCBM

0.61 0.35 0.26 0.21 0.12 0.47 0.27 0.5

28 26 22 17 21 99 54 84

106 105 105 105 105 106 106 106

>105 >105 >105 >104 >104 >104 >105 >104

0.2

20

104

104

55

P13/PVPc

0.23

64

104

104

45

43 81 37 63 41 81

10 102 105 103 104 104

>104 >105 >104 >104 >104

28

103

>104

PS 6.3×10-3 d PVTT 7.1×10-5 star-PTPMA 0.02 polyimide 3.6×10-3 n-type BPE-PTCDI polyimide 8.2×10-3 polyimide 5.7×10-3 N(PTPMA)3: 0.0027 TIPS-PENe Polystyrene para-substituted with p-conjugated oligofluorenes

methacrylate]. PVP.

d

c

b

Ref.

56

53 51 54

52 51 36 50 49 43

Star-shaped poly[(4-diphenylamino) benzyl

Heterojunction of N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (PTCDI-C13) and

Poly(5-hexyl-5′′-vinyl-2,2′:5,2′′- terthiophene) (PVTT).

e

Blending of three-armed star-shaped poly[4-

(diphenylamino)benzyl methacrylate] (N(PTPMA)3) and 6,13-bis(triisopropylsilylethynyl)pentacene (TIPSPEN).

To this end, we report herein high-performance solution-processed ONVMs based on PS-brush as a polymer electret and n-channel polymer semiconductor blends with a p-channel conjugated small molecule for achieving the optimized memory characteristics. The PS-brush dielectric layer is covalently attached to the SiO2/Si(n++) substrates, thus enabled multi-layer stacking of subsequent layers (organic semiconductors) via solution process. Especially, the 6


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semiconductor blends interestingly showed superior reprogrammable memory behaviour, which is significantly different with those of single component n-channel semiconductor; write-once-read-many (WORM) type memory characteristics. It is mostly attributed to engineered barrier heights between the frontier molecular orbitals of organic semiconductors and a PS electret in order to precisely control the charge transfer and trapping process. Consequently, the addition of p-channel molecules with small electron affinity in n-channel polymer matrix resulted in ONVMs with excellent programming and erasing capability with a large memory window of 43 V, memory ratio of 107 as long as 104 s, and very long retention time approaching 10 years by extrapolating the ON/OFF current plots. Furthermore, our blend system has also an additional prospect that p-channel component exposure to top surface by vertical phase separation, which played as a passivation layer for relatively airsensitive n-channel semiconductor to afford stable and reliable memory devices under ambient conditions.

2. EXPERIMENTAL SECTION Materials

and

Methods.

Poly{[N,N′-bis(2-octyldodecyl)-naphthalene-1,4,5,8-

bis(dicarboximide)-2,6-diyl]-alt-5,5′-(2,2′-bithiophene)} (P(NDI2OD-2T); N2200, Mw = 289,730 g mol-1, Ossila), 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-PEN, Ossila), polystyrene (PS)-brush (Mw = 28,000 g mol-1, Polymer Source), chlorobenzene (Sigma-Aldrich) were purchased from commercial source and used as received. Electrochemical Characterization. The electrochemical characteristics of two semiconductor materials were measured by cyclic voltammetry (CV) using electrochemical analyser/workstation (CHI 900D, CH Instruments, Inc.). 1.0 M tetrabutylammonium 7



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tetrafluoroborate in dichloromethane and acetonitrile were used for TIPS-PEN and N2200, respectively, as electrolyte solutions. TIPS-PEN was measured in the electrolyte solution at a concentration of 2 mg/mL and N2200 was measured as a thin-film on the working electrode (glassy

carbon).

The

Ag/Ag+

reference

electrode

was

calibrated

using

a

ferrocene/ferrocenium (Fc/Fc+) redox couple (-4.80 eV) as an external standard. And, platinum wire electrode was used as a counter electrode. The HOMO and LUMO levels (EHOMO/LUMO) were extracted using the following equations: EHOMO (eV) = -e(Eoxonset – EFc/Fc+onset) – 4.80 eV

(1)

ELUMO (eV) = -e(Eredonset – EFc/Fc+onset) – 4.80 eV

(2)

where Eoxonset is the oxidation potential, Eredonset is the reduction potential, and EFc/Fc+onset is the halfway potential of Fc/Fc+ between the two onset points of observed peaks. Device Fabrication. For the fabrication of bottom-gate/top-contact (BG/TC) OFETs, highly n-doped Si wafer with a 300 nm thick thermally grown SiO2 gate dielectric was used as substrates. The substrates were cleaned via bath sonication in 2propanol for 15 min, followed by oxygen plasma cleaning for 5 min (Harrick plasma, PDC-32G, 18W). The commonly used recipe for PS-brush treatment was employed to attach polymeric electret layer on SiO2/Si(n++) substrates.61 The semiconductor layer was deposited by spin-coating (500 rpm, 50 s) of a chlorobenzene solution of N2200 (6 mg mL-1) or N2200/TIPS-PEN blends in various weight ratio (12:1, 9:1, 6:1, 1:1, 1:3, 1:6, total concentration of 6 mg mL-1). The spin-coated samples were kept in a vacuum oven at 100 °C for 10 h to remove the residual solvent. The thicknesses of the PS-brush (10 nm) and semiconductor films (100 – 160 nm) were measured using atomic force microscopy (AFM, NX10, Park system) and surface profilometer 8


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(DEKTAK-XT, Brucker), respectively. The Au source/drain electrodes (40 nm) were thermally evaporated (deposition rate = 0.2 Å s-1) using metal shadow mask with a channel length of 50 µm and width of 2000 µm, respectively. Device Characterization. The electrical characteristics of ONVMs were measured using Keithley 4200-SCS under vacuum or in ambient. The saturation mobility (µsat) was extracted from gradual channel approximation, as the following equation: µsat = (2IDSL)/[WCi (VG - Vth)2]

(3)

where IDS is the source-drain current, L is the channel length, W is the channel width, Ci is the areal capacitance of the PS-brush treated gate dielectric (11.1 nF cm-2), VG is the gate voltage, and Vth is the threshold voltage. The surface morphology of the semiconductor films was characterized by atomic force microscopy (AFM, NX10, Park system).

3. RESULTS AND DISCUSSION To realize solution-processed ONVMs based on polymer electrets in the BG/TC configuration, finding appropriate orthogonal solvents for organic semiconductor is very important. Instead, we chose the PS-brush as a charge trapping layer, since covalentlyattached PS layer onto the SiO2/Si(n++) substrate enables successive solution processing of organic semiconductors (Figure 1). Also, the PS-brush-treated substrate exhibited a very smooth surface (root-mean-square roughness = 0.22 nm), so that the upper semiconductor layer could well be processed (Figure S1). A representative n-channel organic semiconductor, N2200, was spin-coated onto PS-brush layer and Au source/drain electrodes were deposited. The resulting memory devices were characterized in terms of a few figures of merits, including memory window, memory ratio, programming/erasing (P/E) voltage, retention time, 9



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and P/E cycle endurance. The memory window represents the difference in threshold voltage (Vth) between the programmed and the erased state. And the memory ratio is the drain current ratio between the programmed and the erased state when the gate voltage (VG) is zero. For programming the n-channel transistor memory, negative VG bias was applied to induce hole transfer and trapping in PS electret layer. When high VG of -120 V was applied for 1 s, we could confirm the hole trapping process from the negative shift in the transfer plots, as shown in Figure 2a. As a result of the programming process, a large Vth shift of 56 V was observed, which reveals the excellent charge trapping property of PS-brush layer. It is consistent with previous reports that non-polar and hydrophobic polymers such as PS had long charge relaxation time to stably store the charge.58 In addition, the ONVM with PS-brush showed the electron mobility of 0.03 cm2 V-1 s-1 in the saturation region (VDS = 20 V); relatively low mobility in comparison to OFETs without electret layer was attributed to the trapping of mobile electrons accumulated at the semiconductor-electret interface.

10


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Figure 1. A schematic illustration of non-volatile organic memory, charge trapping capability of PS-brush, and chemical structures of the materials employed in this study.

On the other hand, for erasing the memory device, positive VG of +100 V was applied to the programmed ONVMs. Note that erasing voltage of +100 V was applied to sufficiently erase the programmed memory device (vide infra). However, this erasing process did not occur well. As can be seen in Figure 2a, a positive shift of the transfer curve was around 15 V. When we further increased the erasing voltage up to +120 V, the transfer plots were just moved in the positive direction by 36 V (Figure S2), but it was still insufficient recovery for complete erasing of the data. Notably, for the efficient erasing process of the ONVM based on electret, the existence of minority charge carriers and its moderate energetic barrier to overcome the charge transfer/trapping is important. Although the N2200 molecule 11



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has both donor-acceptor moieties to transport electron and holes, respectively, the bottomgated OTFTs typically exhibited electron dominant charge transport characteristics due to air exposure and/or charge injection barrier from TC Au electrode. Moreover, it is also attributed to relatively large barrier height for electron transfer/trapping from the N2200 to PS-brush electret since the N2200 has high electron affinity with low-lying lowest unoccupied molecular orbital (LUMO) of ~ -3.9 eV.

Figure 2. (a) Program and erase switching characteristics of transfer curves of ONVMs and (b) Retention characteristics of the memory device using pristine N2200 as an active layer. Drain voltage was fixed at VDS = 20 V and programming and erasing voltages were -120 V (for 1 s) and +100 V (for 1 s), respectively. All measurements were carried out in a vacuum.

12


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Figure 2b shows retention characteristics of the N2200 ONVMs with PS-brush electret. After programming and erasing by application of -120 V and +100 V for 1 s, respectively, the progressive decrease in memory ratio was measured. It is clearly verified that the ON-state current was very stably sustained with a large memory ratio of 107 more than 104 s. As extrapolating the ON/OFF current plots, the memory ratio of 105 was estimated to have remained even after 10 years (Figure 2b). Note that although the extrapolation method has usually been employed to estimate the retention characteristics of ONVM after a long period of time, organic materials would gradually be degraded under longterm external stimuli, which may bring a sudden change of current rather than a slow decline. Therefore, the N2200 ONVMs based on PS-brush electret showed excellent charge storage capability but without enough erasing performance, so that this memory can only be used as a write-once-read-many (WORM) type memory. In order to enable complete erasing of the programmed ONVMs, those holes trapped in the PS-brush electret during programming process should be de-trapped or compensated with counter charge carriers, in which electrons injected from the N2200 active channel recombine with the trapped holes. As mentioned above, due to the low LUMO level of the N2200 and a large bandgap of PS-brush, electron injection to the electret is significantly difficult, making it impossible for programmed holes to compensate with electrons. Therefore, it is strongly recommended to use electrets with smaller band-gap and/or semiconductors with engineered highest occupied molecular orbital (HOMO) and LUMO levels. To this end, we chose TIPS-PEN, a solution-processable p-channel semiconductor with small electron affinity. Because the TIPS-PEN is a functionalized small molecule with good solubility in common organic solvents, it can simply be blended with polymeric N2200. A semiconductor 13



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blend solution (total concentration of 6 mg mL-1) of N2200 and TIPS-PEN was employed via spin-coating as an active layer of ONVMs. To see if the erasing process was possible, the same gate bias of -120 V and +100 V was applied for programming and erasing, respectively. As shown in Figure 3, the resulting memory characteristics clearly demonstrated that efficient erasing process occurred in PS-brush electret memory. Note that -120 V and +100 V of programming and erasing voltages were employed for the operation of memory device since that voltage (-120 V) created a programming state with the highest on-current value at VG = 0 V and sufficient erasing process was achieved at the voltage (+100 V) lower than programming voltage (Figure S3). The ONVMs using N2200:TIPS-PEN semiconductor blends showed a full recovery of transfer plots by application of VG (erase) = +100 V, in contrast to those of single component N2200-based memory device (Figure 2a).

14


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Figure 3. P/E switching characteristics of transfer curves of ONVMs with various blending ratio of N2200 and TIPS-PEN; N2200:TIPS-PEN ratio (a) 12:1, (b) 9:1, (c) 6:1, (d) 1:1, (e) 1:3, and (f) 1:6. Drain voltage was fixed at VDS = 20 V and programming and erasing voltages were -120 V (for 1 s) and +100 V (for 1 s), respectively. All measurements were carried out in a vacuum. The ONVMs with optimized ratio (6:1) of semiconductor blends showed reasonable electrical characteristics with electron mobility (µe), Vth, and memory ratio of 0.12 cm2 V-1 s-1, 0.11 V, and 107, respectively, at the drain voltage of 20 V (Figure S4). The measured electron mobility was higher than those of other n-channel ONVMs reported in the literatures (Table 1), as well even better than those of single component N2200 memory device. Various blending ratios of N2200 and TIPS-PEN were employed in order to achieve the optimized 15



Page 16 of 35

memory characteristics (Table 2 and Figure 3). As the TIPS-PEN concentration is increased, the memory windows tend to increase. The reason is that p-channel TIPS-PEN component in semiconductor blend could provide more holes to be stored in a PS-brush electret than those of single N2200; thus larger Vth shifts were observed in the negative direction as the ratio of TIPS-PEN increased when negative programming bias was applied. Moreover, the memory window of ONVMs employing TIPS-PEN as the active layer was much larger under the same programming and erasing voltage conditions in this study (Figure S5). On the other hand, the memory ratio showed the highest value of 107 for 6:1 ratio of N2200 versus TIPSPEN due to low OFF current of the device after the erasing process. Consequently, we found the optimum blend ratio of 6:1 by considering the values of the memory window and the memory ratio, which had a remarkably large memory ratio of 107 and adequate memory window of 43 V. Although a 1:6 ratio has a larger memory window as high as 66 V, a 6:1 ratio is more advantageous in terms of distinct memory ratio because it has a much larger memory ratio of 107 than those of ONVMs with the other semiconductor blend ratios (Figure 4). Note that a 1:6 ratio exhibited relatively small memory ratio (103) due to high off current of the corresponding memory device (Figure 3f). This could be due to enhanced formation of p-type conductive channel, and the resulting ambipolar behavior. Especially, this memory ratio of 107 maintained stably over 104 s, proving excellent retention characteristics of our memory devices (Figure 5a).

16


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Figure 4. Memory ratio and memory window with various blending ratios of N2200 versus TIPS-PEN. Table 2. Memory Device Characteristics Based on Semiconductor Blends of N2200 and TIPS-PEN: Electron Mobility, Memory Window, and Memory Ratio at Various Blending Ratio. Ratio (N2200:TIPS-PEN) [cm2 V-1 s-1]

Mobility Memory Window [V] Memory Ratio

12 : 1

9:1

6:1

1:1

1:3

1:6

0.12 31 103

0.14 46 103

0.12 55 107

0.07 60 104

0.10 64 103

0.07 66 103

The memory devices based on the optimized semiconductor blends were further characterized via sequential programming, reading, and erasing cycling endurance by measuring each drain current according to the number of P/E cycles. As shown in Figure 5b, the PS-brush electret memory based on optimized N2200:TIPS-PEN blend exhibited reliable memory performance with stable P/E cycling endurance over 100 cycles. Moreover, the large memory window and memory ratio would be promising in order to increase the storage capacity per unit memory cell. Since the optimized ONVMs exhibited large memory ratio, various digital information with intermediate ON-state current can be written and stored. To this end, we measured the multi-level memory characteristics by dividing the memory states to 4 levels (2 bits per 1 cell), and it showed no significant decay of ON currents even after 104 s (Figure 5c). 17



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Figure 5. Memory characteristics of the ONVM with the N2200:TIPS-PEN (6:1) blends as an active layer. (a) Retention characteristics of ON/OFF drain current as a function time, (b) P/E memory cycling endurance characteristics, and (c) multi-level memory characteristics of the ONVM. Drain voltage was fixed at VDS = 20 V. All measurements were carried out in a vacuum. 18


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Based on the memory device characteristics, we propose a possible operation mechanism, as shown in Figure 6. The LUMO level of n-channel N2200 and HOMO/LUMO levels of p-channel TIPS-PEN were measured by cyclic voltammetry as -3.83 eV and -5.08/3.29 eV, respectively (Figure S6). The measured LUMO level of N2200 was similar to the values reported in the literatures.62-69 By application of a negative gate bias for programming the ONVMs, minority charge carriers (holes) in the N2200 are injected and trapped in the PSbrush electret. The shift of Vth in the negative direction is induced as a function of the number of trapped charge carriers (Figures 6a and 6c). For the erasing process of ONVMs, reverse gate bias has to be applied for holes to be de-trapped and/or compensated with injected counter charge carriers (electrons). When a positive gate bias is applied with the N2200 active layer, some holes in the PS-brush electret are de-trapped but the complete erasing process is not feasible due to high energy barrier between the LUMO of N2200 and PS-brush for electrons to recombine with the holes (Figure 6b). On the other hand, the incorporation of p-channel TIPS-PEN with higher LUMO level affords the injection of electrons from TIPSPEN to PS-brush electret, enabling the full compensation of the trapped holes in the electret and complete erasing process (Figure 6d). If higher positive gate bias is applied, an excess number of electrons would be transferred and stored in the electret layer. Therefore, overall transfer plots were moved in the positive direction and larger memory window was observed with more distinguishable memory ratio.

19



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Figure 6. Schematic illustrations of the programming and erasing processes of ONVMs based on PS-brush electrets. (a) programming and (b) erasing process of ONVM employing single-component N2200 as an active layer, (c) programming and (d) erasing process of ONVM with N2200:TIPS-PEN blends as an active layer.

The OFETs based on N2200 as an active layer have been known to suffer from performance degradation in ambient air due to relatively high LUMO level (-3.83 eV) of the corresponding compound against oxidization of electrons by ambient species.21,

23, 48, 70

Therefore, most of N2200-based devices showed superior electrical performance either under vacuum condition or in top-gate/bottom-contact configuration, where upper-laid gate 20


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dielectric acts as a passivation layer. When we measured the electrical properties of ONVMs based on single-component N2200 in ambient air, they exhibited poor retention characteristics with no capability as non-volatile memory (Figure S7). Interestingly, ONVMs based on the semiconductor blends of N2200 and TIPS-PEN showed decent memory device characteristics with memory ratio of 106 and memory window of 51 V, even in ambient air (Figure S8). Notably, the charge retention time was remarkably improved with memory ratio of 106 after 104 s. For commercial applications to solid-state data storage, the minimum retention time should be at least 10 years. In this regard, our ONVMs fulfill the requirement, that is, the memory ratio stably sustained even after 10 years which was estimated by extrapolating the ON/OFF current plots, as can be seen in Figure S8. To investigate the origin of low OFF current and decent ambient stability of ONVMs employing semiconductor blends of N2200 and TIPS-PEN, surface morphologies of the blend thin-films were characterized by atomic force microscopy (AFM). Since we could confirm a phase separation through the AFM image,71-73 active layer morphologies were analyzed between the single-component N2200 and N2200:TIPS-PEN blends as an active layer of ONVMs. As shown in Figure 7, pristine N2200 film shows a fibril-textured morphology (Figure 7a). On the other hand, it is difficult to find those fibril textures of N2200 polymers in semiconductor blend films; but as the ratio of TIPS-PEN increased, TIPSPEN crystals with higher height were observed, as can be seen in Figures 7b-g. Importantly, except for the 6:1 ratio, a number of small-sized TIPS-PEN crystallites are observed, which are likely to form a relatively conductive channel. As can be seen in Figures 3f and 7g, a high concentration of TIPS-PEN in N2200:TIPS-PEN blend (1:6) films induced small memory ratio, due to the formation of a conductive pathway through the TIPS-PEN crystals. The 21



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highest memory ratio was obtained at 6:1 blend ratio, possibly due to the isolated TIPS-PEN crystals in the blended semiconductor film.

Figure 7. AFM images (area size 15 µm x 15 µm) of (a) pristine N2200 thin-film and (b-g) N2200:TIPS-PEN blended thin-films with different concentration ratio, and (h) pristine TIPS-PEN thin-film. RMS (root-mean-square) roughness values were 2.3, 32.7, 26.4, 35.0, 84.9, 73.5, 48.0, and 82.5 nm from (a) to (h), respectively. AFM images exhibited vertical phase separation of two active layer components after spin-coating the blended semiconductor solution. To confirm the topological feature, we used an orthogonal solvent of N2200, propylene glycol methyl ether acetate (PGMEA), to selectively remove the small molecular p-type component (TIPS-PEN). The substrate was immersed in PGMEA solvent, thus TIPS-PEN crystals formed onto the N2200 film were washed out by PGMEA. After the washing, TIPS-PEN crystals dissolved in PGMEA and only the underlying N2200 film morphology was observed (Figure S9). Interestingly, when we measured the memory characteristics after dissolving the TIPS-PEN layer by PGMEA, erasing process did not work well (Figure S10). This memory behaviour reveals that the 22


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blended semiconductor film was vertically separated. Vertical phase separation could be attributed to the exposure of relatively polar and small molecules to top surface during spincoating and the dewetting of TIPS-PEN by high-temperature annealing. Note that relatively flat TIPS-PEN film was observed after annealing at low temperature (30 °C) (Figure S11). Therefore, the decent ambient stability of ONVMs based on semiconductor blends employed in this study might be ascribed to the vertically separated semiconductors in the thin film. Due to this favorable phase separation of the blended semiconductor solution, the TIPS-PEN crystals formed a passivation layer on top of the N2200 film at the optimized blending ratio, which lead to complete erasing process, P/E memory cycling endurance, large memory window, and remarkably stable retention characteristics for ONVM based on blended semiconductor with PS-brush electret, even in ambient air.

4. CONCLUSION In summary, we have successfully developed a high-performance solution-processed ONVM devices based on a PS-brush electret. Since the PS-brush electret is designed to be covalently bonded to the substrate, a semiconductor layer can be deposited via solution process to fabricate the bottom-gated ONVMs. Those memory characteristics are strongly dependent on the conformation of the semiconductor layer. When a representative n-type semiconductor N2200 is employed as an active layer, its memory device exhibits a WORMtype memory behaviour without a full erasing process. On the other hand, ONVMs were fabricated by employing an N2200:TIPS-PEN blend with a distinctively different HOMO and LUMO levels. Consequently, relatively high LUMO level of p-channel TIPS-PEN enables injecting electrons efficiently into the PS-brush electret so that complete erasing process was 23



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possible with remarkably improved memory performances, such as stable memory cycling endurance, large memory window, memory ratio, and a long charge retention time approaching 10 years. In addition, due to the vertical phase separation of the blended semiconductor layer, TIPS-PEN crystals were formed on the upper layer of N2200 polymer matrix, resulting in decent ambient stability. Our research paves the way to analyze the exact operation mechanism for the electret-based ONVMs and provides a strategy for the fabrication of n-type ONVMs via simple and cost-effective printing process for flexible solidstate data storage based on organic semiconductors.

Acknowledgments This work was supported by a National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIT) (Nos. NRF-2017R1A2B4001955).

ASSOCIATED CONTENT Supporting Information. Surface morphology of polystyrene-brush-treated substrate and semiconductor films, electrical characteristics of memory devices, electrochemical characteristics of semiconductors, Figures S1–S11.

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Solution-Processed Non-Volatile Organic Transistor Memory based on

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