Solution-Processed Self-Assembled Nanodielectrics on Template

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Solution-Processed Self-Assembled Nanodielectrics on Template-Stripped Metal Substrates Julian Juin E McMorrow, Amanda Walker, Vinod K. Sangwan, Deep Jariwala, Emily E. Hoffman, Ken Everaerts, Antonio Facchetti, Mark C Hersam, and Tobin J. Marks ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.5b07744 • Publication Date (Web): 19 Oct 2015 Downloaded from http://pubs.acs.org on November 18, 2015

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ACS Applied Materials & Interfaces

Solution-Processed Self-Assembled Nanodielectrics on Template-Stripped Metal Substrates Julian J. McMorrow,† Amanda R. Walker,‡ Vinod K. Sangwan,† Deep Jariwala,† Emily Hoffman,† Ken Everaerts,‡ Antonio Facchetti,*,‡,# Mark C. Hersam,*,†,‡,§ and Tobin J. Marks*,†,‡ †

Department of Materials Science and Engineering, ‡Department of Chemistry, §Department of

Medicine, Northwestern University, Evanston, Illinois 60208 #

Polyera Corporation, 8045 Lamon Avenue, Skokie, Illinois 60077, USA

KEYWORDS nanodielectric, self-assembly, capacitor, template strip, unconventional electronics

ABSTRACT The coupling of hybrid organic-inorganic gate dielectrics with emergent unconventional semiconductors has yielded transistor devices exhibiting record-setting transport properties. However, extensive electronic transport measurements on these high-capacitance systems are often convoluted with the electronic response of the semiconducting silicon substrate. In this report, we demonstrate the growth of solution-processed zirconia self-assembled nanodielectrics (Zr-SAND) on template-stripped aluminum substrates. The resulting Zr-SAND on Al structures leverage the ultrasmooth (r.m.s. roughness < 4 Å), chemically uniform nature of template-

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stripped metal substrates to demonstrate the same exceptional electronic uniformity (capacitance ~ 700 nF cm-2, leakage current < 1 µA cm-2 at -2 MV cm-1) and multilayer growth of Zr-SAND on Si, while exhibiting superior temperature and voltage capacitance responses. These results are important to conduct detailed transport measurements in emergent transistor technologies featuring SAND as well as for future applications in integrated circuits or flexible electronics.


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Scaling trends in modern complementary metal-oxide-semiconductor (CMOS) technologies have necessitated the adoption of high-κ gate dielectric materials to supplant silicon oxide in field-effect transistors (FETs).1 Similarly, the eventual replacement of silicon as a transistor channel material has generated intense interest in the electronic transport properties of unconventional semiconductors such as carbon nanotubes,2,3 graphene,4 organics,5,6 amorphous metal oxides,7,8 layered transition metal dichalcogenides,9 and black phosphorus.10 While electronic transport in these semiconductors is described by several mechanisms, in general important FET device metrics such as charge carrier mobility,11-13 threshold voltage,14-17 and interface trap density18,19 can be considerably improved by the incorporation of organic materials in the gate insulator to form hybrid organic-inorganic gate dielectrics.20-22 An important class of these hybrid gate dielectric films is the self-assembled nanodielectric (SAND), which leverages the sequential self-assembly of high-κ organic layers on traditional inorganic oxide materials to form multilayer superlattice structures.23,24 The inorganic layer of solution-processed SAND has evolved from siloxane-derived SiOx (Si-SAND)25 to include high-κ metal oxides such as ZrOx and HfOx (Zr-SAND26 and Hf-SAND,27 respectively), while vapor phase assembled SAND (VSAND)28 has recently incorporated atomic-layer deposited (ALD) AlOx (VA-SAND).29 Furthermore, the rational design of different SAND variants has improved the electronic transport properties (e.g., charge carrier mobility and hysteresis, threshold voltage, etc.) of FETs based on the aforementioned unconventional semiconductors.30-33 These demonstrations of enhanced electronic transport in emergent electronic materials afforded by SAND motivate further studies into the details of charge transport in these SAND/semiconductor systems. Although the constituent materials and methodologies for SAND fabrication have advanced since the original SiOx-based nanodielectrics, all such second generation SAND variants have so


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far been grown on the native oxides of polished silicon wafers serving as the FET gate contact. While these wafers are ideal substrates for growing and characterizing new gate dielectric materials due to their extraordinarily low roughness (r.m.s. < 0.2 nm) and chemical uniformity, they ultimately limit the technological impact of these novel gate dielectrics for a number of reasons. First, the inclusion of a low-κ SiO2 layer in the SAND structure is antithetical to the goal of developing truly high-κ dielectrics, motivating its removal or replacement with a high-κ oxide material. Second, investigating the fundamental mechanisms at play when pairing emergent semiconductor channel materials with SAND gate dielectrics begins with electronic transport measurements. Charge carrier depletion in the semiconducting Si gate electrode results in a gate capacitance dependent both on gate bias and temperature. These effects are negligible in low-capacitance dielectrics (for 300nm SiO2, Ci = 11.5 nF cm-2) but are prominent in dielectric films in which the capacitance of the insulating layer is greater than that of the Si depletion layer (C ~ 300 nF cm-2; see Supporting Information). Thus, charge transport phenomena occurring at gate biases coincident with the depletion of the Si substrate (e.g., the carrier population of the conduction or valence bands of most semiconductors, or the Dirac point in graphene field-effect devices)4 are convoluted and difficult to analyze with SAND on Si. Third, the temperaturedependent electronic transport of a semiconductor cannot be disentangled from the temperaturedependent capacitance of the underlying insulator and Si substrate. Finally, the underlying Si substrate introduces the additional complexity of carrier freeze-out at cryogenic temperatures.34 For these reasons, Si substrates are suboptimal for accurate temperature-dependent FET transport studies featuring SAND. In contrast, a metallic substrate would allow unambiguous assignment of the gate dielectric capacitance as well as isolate the temperature-dependent behavior of the gate dielectric from that of the substrate.


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Here, we present a methodology for depositing high-quality solution-processed Zr-SAND thin-films on metal substrates. Large area ultra-flat (r.m.s. roughness < 0.4 nm) metal surfaces are achieved by template stripping (TS), producing metal films that approach the smoothness of polished Si wafers.35 Without careful control of the growth substrate surface36 as well as the metal film growth parameters,37,38 the top surface of an evaporated metal film is generally very rough and has large asperities39 (Figure S2), making evaporated metal a problematic substrate for depositing ultrathin dielectric layers. In this work, aluminum was chosen as the metallic substrate material due to its self-limiting ultrathin high-κ native oxide, which forms readily under ambient conditions. The AlOx surface of the Al also presents a chemically ideal surface for the subsequent growth of Zr-SAND. The resulting Zr-SAND on Al structures are characterized by atomic force microscopy (AFM) and are found to retain the ultra-smooth surface quality of the TS Al (Zr-SAND r.m.s. roughness = 0.55 - 0.65 nm26). Furthermore, cross-sectional transmission electron microscopy (TEM) measurements reveal the preservation of the Zr-SAND multilayer structure following growth on TS Al. Capacitance-voltage (C-V; maximum Ci ~ 700 nF cm-2) and leakage current-voltage (I-V; < 1 µA cm-2 at -2 MV cm-1 applied field) measurements indicate that the excellent dielectric properties of the Zr-SAND films are preserved on TS Al. The C-V and C-T behaviors of Zr-SAND on Al are found to be superior to Zr-SAND on Si, as the metal-insulator-metal (MIM) structure minimizes the voltage and temperature-dependent behavior of the dielectric/substrate system. When compared to Zr-SAND on Si substrates, ZrSAND on Al exhibit superior electronic properties while maintaining the uniformity, smoothness and multilayer superlattice structure that are hallmarks of Zr-SAND on Si. Figure 1 depicts the process flow for achieving template-stripped aluminum. Native oxide Si wafers (r.m.s. roughness = 0.17 nm by tapping mode AFM, Asylum Cypher S) serve as the


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ultra-smooth template material. The typically strong adhesion of Al to SiO2 is prevented by the use of a hexamethyldisilazane (HMDS)-derived trimethylsilyl release layer, self-assembled on the SiO2 surface before the thermal evaporation of Al (100 nm). Next, a UV and thermally cured epoxy layer (NOA – Norland Optical Adhesive 83H) is placed in between the Al surface and a glass slide. When the NOA fills the volume between the glass and the Al surfaces, the NOA is cured. The glass/NOA/Al structure is mechanically delaminated, yielding a smooth Al surface (r.m.s. = 0.39 nm), templated by the Si wafer surface. Si template substrates have been shown to be reusable,40 offering a cost-effective method for producing Al surfaces with few-Ångstromscale roughness. Compared to the Si wafer surface, the TS Al surface features a small population of defects related to Al evaporation, contributing to the observed, slightly increased roughness. It will be shown below that these defects affect neither Zr-SAND dielectric properties nor film quality, suggesting that the Zr-SAND growth is unaffected by their presence.

Figure 1. Schematic of the process flow for achieving template-stripping (TS) aluminum. (1) A native oxide silicon template wafer is (2) coated with HMDS (yellow) and evaporated aluminum. (3) Epoxy bonds a glass substrate to the aluminum surface (4). (5) The glass/epoxy/aluminum structure is mechanically delaminated from the silicon template, affording (6) an ultra-smooth aluminum bottom surface. AFM micrographs in top left and bottom right depict silicon native


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oxide surface and template stripped aluminum native oxide surface, respectively. (5 µm x 5 µm, height scale 5 nm). Figure 2 illustrates the Zr-SAND deposition scheme through three successive layers (a-d). The TS Al substrate surface is first treated with an O2 plasma to remove potential HMDS residue from the template-stripping process. AFM measurements of the TS Al surface before and after plasma treatment reveal no increase in surface roughness. The Zr-SAND deposition process begins with spin coating a sol-gel processed ZrOx film on the plasma treated AlOx surface, establishing the bottom-most ZrOx priming layer. This step is followed by the solution phase self-assembly

of

the

phosphonic

acid-based

π-electron

molecule

4-[[4-[Bis(2-

hydroxyethyl)amino]phenyl]diazenyl]-1-[4-(diethoxyphosphoryl)benzyl]pyri-dinium

bromide

(PAE), the synthesis of which is described previously.26 The 1-layer Zr-SAND structure is completed by spin coating another ZrOx layer (capping layer). Fig 2a and b illustrate a schematic of the 1-layer Zr-SAND structure and the PAE molecular structure. Repeated iterations of the self-assembled PAE and spin coated ZrOx capping layers form Zr-SAND having the desired number of layers. The surface morphologies for 1-3 layers of Zr-SAND, imaged by AFM, are shown in Figures 2 f–h. The r.m.s. roughness values of the Zr-SAND layer top surfaces, 0.54 nm, 0.65 nm, and 0.60 nm for layers 1-3, respectively, are somewhat larger than that of the AlOx substrate (0.35 nm) by a factor comparable to previous reports of Zr-SAND growth on Si/SiO2: 0.17 nm for the Si native oxide vs. 0.36 nm for 3-layer Zr-SAND.26 Low dielectric surface roughness is essential for back-gated transistor devices, as rough dielectric/semiconductor interfaces are known to decrease mobility via increased carrier scattering.41


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Figure 2. Schematic depicting Zr-SAND growth process. (a) – (d) layer-by-layer assembly of the Zr-SAND multilayer structure. (e) Brightfield TEM cross-section of 3-layer Zr-SAND structure in (d); the multilayer modulation of the Zr-SAND can be seen between the aluminum (light) and gold (dark) regions. (f) AFM micrograph of the aluminum oxide surface. (g – i) AFM micrograph of 1 – 3 layer Zr-SAND surfaces, respectively. AFM scans are 5 µm x 5 µm with height scale 5 nm. (j) Normalized intensity profile averaged from (e) quantifying the total ZrSAND thickness and multilayer spacing. To further examine the microstructure of Zr-SAND on TS Al, cross-sectional transmission electron microscopy (TEM) was utilized on a 3-layer Zr-SAND sample. These bright field TEM images (Figure 2e) reveal regions of low and high Z-contrast, corresponding to layers of Au and Al, respectively. This orientation is corroborated by energy dispersive x-ray spectroscopy (EDS) in Figure S3. Between these regions are highly parallel, alternating regions of high and low contrast. The first layer nearest the Al corresponds to AlOx (4.2 nm) while the adjacent dark contrast layer corresponds to the ZrOx priming layer (5.4 nm). The next alternating regions of bright and dark contrast correspond to the alternating ZrOx/PAE multilayers. The total thickness of the 3-layer Zr-SAND structure is found to be 20.1 nm with a multilayer spacing of 3.5 nm (Figure 2j). Because the implementation of Al substrates does not compromise the


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morphological quality of the multilayers, Zr-SAND dielectrics on Al can be further characterized for electronic applications. To examine the dielectric properties of Zr-SAND on Al, MIM capacitor devices were fabricated by evaporating gold contact pads (200 µm x 200 µm) on Zr-SAND on Al. Control metal-insulator-semiconductor (MIS) capacitors of Zr-SAND on degenerately doped n++ Si substrates were also fabricated to highlight the advantages of metallic substrates for Zr-SAND characterization. The top, grounded contact in both the MIM and MIS capacitors is composed of gold. The room-temperature C-V and characteristics of Zr-SAND on Al and Si are reported in Figure 3. Figure 3a includes the C-V behavior of 1-3 layers of Zr-SAND on Al (MIM) and Si (MIS). For each layer, the difference between the MIM and MIS devices are clear, as the capacitances of the MIS devices vary strongly with bottom bias, while the capacitance of the MIM devices do not. The voltage dependence of the capacitance of the MIS structures is the result of the semiconducting substrate; the C-V curves exhibit clear regions of accumulation and depletion for the Si substrate (percent change in depletion = 62%, 56%, 54% for layers 1-3, respectively) while the C-V curves of the MIM capacitors exhibit comparatively constant voltage dependence (within 4% of the maximum value). In accumulation, the capacitance of a MIS capacitor approaches that of the dielectric film, so it is common to assign the maximum value in the C-V plot to Ci, the area normalized capacitance of the dielectric film. For this reason, assigning an unambiguous value for Ci is problematic in the case when the Si substrate is not in full accumulation for a given voltage. Thus, the voltage-independent C-V behavior of Zr-SAND on Al is clearly superior to that of Zr-SAND on Si for dielectric characterization.


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(a) on Al

on Si

1L Zr-SAND 2L Zr-SAND 3L Zr-SAND

(b)

(c) on Si on Al

on Si on Al

Figure 3. (a) Representative room temperature capacitance-voltage curves for 1-3 layer ZrSAND on Al (solid) and Si (dashed) substrates, contrasting the bottom-voltage-independent capacitance of Zr-SAND on Al to the strongly dependent bottom-voltage behavior of Zr-SAND on Si. (b) Capacitance as a function of layer number for Zr-SAND on Al (purple) and Si (brown). 1/n functional fits are established by inverting the linear fit in (c). (c) Inverse capacitance as a function of layer number. The linear fit reveals well-behaved layer-by-layer growth. Markers and error bars in (b) and (c) represent the average and standard deviation, respectively, over 10 devices on a single substrate. Figure 3b plots Ci (at Vb = +4V) versus the number of Zr-SAND layers, n, for Zr-SAND on Al and Si. Each data point represents the average over 10 devices on a single substrate with the


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standard deviation given by the error bars. For Zr-SAND on Al, the Ci values are 707 ± 11 nF cm-2 (n = 1), 566 ± 4 nF cm-2 (n = 2), and 462 ± 4 nF cm-2 (n = 3), while for Zr-SAND on Si, the Ci values are 748 ± 24 nF cm-2 (n = 1), 552 ± 5 nF cm-2 (n = 2), and 421 ± 5 nF cm-2 (n = 3). The exceptionally small standard deviation values highlight the large area (>1 cm2) dielectric performance uniformity afforded by the combination of TS Al substrates and the Zr-SAND deposition process. Modeling each constituent layer of the Zr-SAND structure as a parallel plate capacitor allows the analysis of the Zr-SAND multilayer structure as a collection of parallel plate capacitors in series, the capacitance of which is given by 1 Ci

=

1 Cnative

+

1 Cprime

+ n · C

1

PAE

+

1 Ccap

(1)

where Cnative, Cprime, CPAE, and Ccap represent the capacitances of the native oxide layer (AlOx or SiO2), the ZrOx priming layer, an individual PAE layer plus an individual ZrOx capping layer, respectively. This analysis predicts 1/Ci to be linear in n, as is plotted in Figure 3c. The data are fitted well by a linear function for Zr-SAND on both Al and Si, evidence of uniform layer-bylayer Zr-SAND growth on both substrates. The differences in slope and intercept for the linear fit lines appear to indicate differences in the growth of Zr-SAND on Al vs. Si. Eq. 2 indicates that the intercept (n = 0) is related to the capacitance of the native oxide and ZrOx priming layer, while the slope is the inverse of the per-layer capacitance of the Zr-SAND structure. For ZrSAND on Al, the capacitance of the AlOx + ZrOx priming layer is found to be 967 nF cm-2, while the capacitance of the SiO2 + ZrOx priming layer is 1240 nF cm-2. Making the reasonable assumption that the ZrOx priming layer is identical when deposited on AlOx or SiO2, it can be concluded that the AlOx layer has lower capacitance than the SiO2 layer. Note that while bulk Al2O3 has a higher κ (9) than SiO2 (3.9), the lower apparent capacitance of the AlOx layer here versus the SiO2 layer can be attributed to the greater thickness of the AlOx, (4.2 nm) vs. SiOx (1.8


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nm), as shown by cross-sectional TEM. The per-layer capacitance of the Zr-SAND multilayers is then found to be 2675 nF cm-2 per layer for Al substrates and 1935 nF cm-2 per layer for Si substrates. The higher apparent per-layer capacitance for Zr-SAND on Al substrates versus the Si substrates is understandable since the measured Ci (taken to be the maximum of the C-V curve) is an underestimate of the actual dielectric capacitance in the case of the semiconducting substrate which does not reach full accumulation in the measured voltage range. Since this is a result of the voltage-dependent capacitance of MIS structures, it serves to illustrate the advantages of metallic substrates for experiments using Zr-SAND. Additionally, the frequencydependent capacitance behaviors of Zr-SAND structures on Al substrates are found to be superior to those of Zr-SAND on Si (Figure S4). Finally, I-V leakage measurements indicate no increased leakage current for Zr-SAND on Al versus those on Si substrates (Figure S5). Temperature-dependent C-V measurements on MIS structures are an additional strong motivator for enabling Zr-SAND growth on Al. Thus, Figure 4a plots the C-V behavior of 1layer Zr-SAND MIM (Al) and MIS (Si) structures in the 290 K - 6.4 K temperature range. The voltage-dependent capacitance response of the MIS device, coupled with a shift in the onset voltage for accumulation, results in dramatic differences in the temperature dependence of the apparent Zr-SAND capacitance values. These temperature responses are quantified in Figure 4b, which plots the measured capacitance of 1-layer Zr-SAND MIM and MIS films as a function of temperature at Vb = +1.5 V and Vb = +3 V. In all cases, the measured capacitance decreases monotonically with decreasing temperature. The percent change of this decrease ((C290KC6.4K)/C290K) is computed to be 15% and 13% for Zr-SAND on Al at +3 V and +1.5 V, respectively, and 26% and 47% for Zr-SAND on Si at +3V and +1.5V, respectively. The nonzero temperature dependence of the capacitance of the Zr-SAND on Al structure has been observed in


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other studies of MIM capacitors.42-44 For Zr-SAND on Al, this may arise from the temperaturedependent ionic motion of the metal cations in the ZrOx and AlOx layers and the Br¯ counter-ions in the PAE layers. While beyond the scope of this work, detailed temperature-dependent capacitance studies to elucidate the polarization mechanisms in Zr-SAND should now be enabled by the present Zr-SAND growth capability on metallic substrates. Because temperaturedependent transport measurements are vital to elucidating transport mechanisms in semiconducting materials, transistor devices in which the apparent capacitance of the gate dielectric varies strongly with temperature convolute the extraction of important transport parameters (e.g., mobility, activation energy, etc.). Thus, minimizing the variation of the gate capacitance with temperature is critical to such studies. The availability of materials such as ZrSAND on Al presents opportunities for temperature dependent charge transport studies not afforded by Zr-SAND on Si.


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Figure 4. (a) Capacitance – voltage curves for 1-layer Zr-SAND on Al (solid) and Si (dashed) for a range of decreasing temperatures. Blue and green curves correspond to T = 200 K and T = 80 K, respectively. (b) Capacitance as a function of temperature recorded at a bottom voltage (Vb) of +3V (solid) and +1.5V (open) for 1-layer Zr-SAND on Al (purple) and Si (brown). Markers and error bars represent the average value and standard deviation, respectively, over 5 devices on a single substrate. The capacitance of Zr-SAND on Si exhibits a larger percent change (26%) with temperature compared to Zr-SAND on Al (15%), especially for Vb = +1.5V (47% versus 13%). In conclusion, we have demonstrated the first successful incorporation of template-stripped ultra-smooth metal substrates (Al) into the Zr-SAND growth scheme. Structurally, the resulting


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Zr-SAND on Al structures exhibit the excellent surface roughness and multilayer hybridsuperlattice structures characteristic of Zr-SAND on Si substrates. Electronically, Zr-SAND on Al structures exhibit exceptionally uniform C-V and I-V properties whose magnitudes meet or exceed those of equivalent Zr-SAND on Si structures. The incorporation of Al substrates eliminates the contribution of semiconducting Si to the observable capacitance of the dielectric film, resulting in Zr-SAND on Al capacitors with minimal C-V curve temperature and voltage dependence. Thus, the use of TS Al substrates in Zr-SAND and related gate dielectrics has immediate applications in electronic transport studies of unconventional semiconductors. Supporting Information. Detailed experimental procedure, a discussion of depletion in high capacitance MIS structures, AFM characterization of the aluminum top surface, EDS analysis of the Zr-SAND structure, representative frequency-dependent capacitance data, and representative leakage-current I-V measurements can be found in the supporting information. This material is available free of charge via the Internet at http://pubs.acs.org. Corresponding Author Tobin J. Marks: *[email protected] Mark C. Hersam: *[email protected] Antonio Facchetti: *[email protected] Author Contributions The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript. Notes


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The authors declare no competing financial interests. Acknowledgements This work was supported by the MRSEC program of the National Science Foundation (DMR1121262), at the Materials Research Center of Northwestern University, National Aeronautics and Space Administration NSTRF Grant NNX12AM44H, and ONR MURI grant N00014-11-10690. A.R.W. is supported by the Department of Defense (DoD) through the National Defense Science and Engineering Graduate Fellowship (NDSEG) Program. D.J. acknowledges support in part by a SPIE Optics and Photonics Graduate Scholarship. This work made use of the EPIC facility (NUANCE Center-Northwestern University), which has received support from the MRSEC program (NSF DMR-1121262) at the Materials Research Center, and the Nanoscale Science and Engineering Center (EEC-0118025/003), both programs of the National Science Foundation; the State of Illinois; and Northwestern University.

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20

r.m.s. = 0.17 nm

Page 21 of 25

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21


1

2

3

Glass Epoxy

Si

Al

Al

Si + HMDS

Si + HMDS

r.m.s. = 0.39 nm

4

5 Glass

Glass

6

Al

Al Si + HMDS


Si + HMDS

Al Glass

(a) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

(b)

(c)ACS Applied Materials & Interfaces (d)

(e)

Au

3-Layer Zr-SAND

=

Page 22 of 25

2-Layer Zr-SAND 1-Layer Zr-SAND AlOx

Al + AlOx

(f)

r.m.s. = 0.35 nm

Al + AlOx

(g)

r.m.s. = 0.54 nm

Al + AlOx

(h)

ACS Paragon Plus Environment r.m.s. = 0.65 nm

Al + AlOx

(i)

r.m.s. = 0.60 nm

10 nm

(j)

Al

Page 23 of 25 ACS Applied Materials & Interfaces

(a) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

on Al

on Si

1L Zr-SAND 2L Zr-SAND 3L Zr-SAND

(b)

(c) on Si on Al

on Si on Al



Page 24 of 25

(a) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

290 K

6.4 K

on Al

on Si

290 K

6.4 K

(b)

on Si, Vb = 3V on Al, Vb = 3V

on Si, Vb = 1.5V on Al, Vb = 1.5V


Page 25 of 25

1 2 3 4 5 6 7 8 9

Glass Al Si


Al Glass


Al

10 nm

Solution-Processed Self-Assembled Nanodielectrics on Template

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