Solution-Processed Transistors Using Colloidal Nanocrystals with

Letter pubs.acs.org/NanoLett

Solution-Processed Transistors Using Colloidal Nanocrystals with Composition-Matched Molecular “Solders”: Approaching Single Crystal Mobility Jaeyoung Jang,† Dmitriy S. Dolzhnikov,† Wenyong Liu,† Sooji Nam,§ Moonsub Shim,§ and Dmitri V. Talapin*,†,∥ †

Department of Chemistry and James Franck Institute, University of Chicago, Chicago, Illinois 60637, United States Department of Materials Science and Engineering, University of Illinois at Urbana−Champaign, Urbana, Illinois 61801, United States ∥ Center for Nanoscale Materials, Argonne National Lab, Argonne, Illinois 60439, United States Downloaded by TEXAS A&M INTL UNIV on September 3, 2015 | http://pubs.acs.org Publication Date (Web): September 2, 2015 | doi: 10.1021/acs.nanolett.5b01258

§

S Supporting Information *

ABSTRACT: Crystalline silicon-based complementary metal-oxide−semiconductor transistors have become a dominant platform for today’s electronics. For such devices, expensive and complicated vacuum processes are used in the preparation of active layers. This increases cost and restricts the scope of applications. Here, we demonstrate high-performance solution-processed CdSe nanocrystal (NC) field-effect transistors (FETs) that exhibit very high carrier mobilities (over 400 cm2/(V s)). This is comparable to the carrier mobilities of crystalline silicon-based transistors. Furthermore, our NC FETs exhibit high operational stability and MHz switching speeds. These NC FETs are prepared by spin coating colloidal solutions of CdSe NCs capped with molecular solders [Cd2Se3]2− onto various oxide gate dielectrics followed by thermal annealing. We show that the nature of gate dielectrics plays an important role in soldered CdSe NC FETs. The capacitance of dielectrics and the NC electronic structure near gate dielectric affect the distribution of localized traps and trap filling, determining carrier mobility and operational stability of the NC FETs. We expand the application of the NC soldering process to core−shell NCs consisting of a III−V InAs core and a CdSe shell with composition-matched [Cd2Se3]2− molecular solders. Soldering CdSe shells forms nanoheterostructured material that combines high electron mobility and near-IR photoresponse. KEYWORDS: nanocrystals, nanoheterostructures, molecular solder, inorganic ligands, field-effect transistor, electron mobility, switching speed

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emerged as new class of solution-processable semiconductors for FET and solar cell devices.10−15 FET mobilities of the best solution-processed organic and inorganic materials have already reached 10−40 cm2/(V s).6−8,11,13−17 These values are well above that of amorphous silicon-based transistors (∼1 cm2/(V s)).18,19 Therefore, the remaining challenge in the field is to chase or overcome the carrier mobility of polycrystalline and single crystalline silicon (100−1000 cm2/(V s)) that typically requires high-cost and complex vacuum processes, laser-assisted annealing, or very high processing temperatures (>500 °C).18−22 Meeting the challenge will open up new avenues for designing highperformance semiconductors with low-cost solution-based fabrication processes.

hin-film transistors made of solution-processable semiconductors have gained considerable interest as the lowcost alternative to traditional silicon-based complementary metal-oxide−semiconductor (CMOS) devices.1−8 For this purpose, various classes of materials have been developed including organic materials2,4,5 and soluble precursors for inorganic semiconductors.1,6−9 CMOS circuits require both pand n-type semiconductors. Organic materials are particularly convenient for p-type components, whereas the best solutionprocessed n-type semiconductors utilize inorganic materials. Among n-type devices, sol-gel-processed metal-oxide thin-film field-effect transistors (FETs) have made a lot of progress in recent years. Thin films composed of In2O3, ZnSnO3, InZnO, and InZnGaO (IGZO) exhibited carrier mobilities of 10−40 cm2/(V s) when annealed at temperatures ranging from 200 to 250 °C.6,7 Sol-gel oxide films processed at room temperature with photochemical activation have also been reported to have carrier mobilities of ∼10 cm2/(V s).9 In addition, colloidal nanocrystals (NCs) with inorganic surface ligands have recently © XXXX American Chemical Society

Received: April 1, 2015 Revised: July 31, 2015

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DOI: 10.1021/acs.nanolett.5b01258 Nano Lett. XXXX, XXX, XXX−XXX

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Downloaded by TEXAS A&M INTL UNIV on September 3, 2015 | http://pubs.acs.org Publication Date (Web): September 2, 2015 | doi: 10.1021/acs.nanolett.5b01258

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ZrOx) to form thin films of NC arrays. The effects of annealing temperature on FET performance and grain growth have been studied to find the relationship between carrier mobility and NC grain size. We demonstrate a record-high electron mobility up to ∼450 cm2/(V s) in solution-processed CdSe thin films and show that high-mobility FETs are remarkably stable with respect to a number of consecutive operation cycles and different gate−voltage sweep rates. Furthermore, these high performance and stable solution-processed FETs exhibit fast switching with a −3 dB frequency of 2.3 MHz despite their simple device architecture and a 50 μm long FET channel. Finally, we also demonstrate the potential for designing complex nanoheterostructured layers with high electron mobility by soldering core−shell NCs consisting of an InAs core and a CdSe shell capped with Na2Cd2Se3 MCC ligands. Soldered CdSe NC FETs with Various Oxide Dielectrics. The synthesis of CdSe NCs and Na2Cd2Se3 MCCs and the exchange of the original organic NC surface ligands with Na2Cd2Se3 was performed as detailed in previously published procedure (see Supporting Information for details).32 It should be noted that excessive MCC ligands that were not bound to the NC surface do not need to be removed because they act as “molecular solder” for CdSe grains. Figure 1a compares the

Among solution-processable semiconductors, colloidal NCs have unique advantages as building blocks for thin-film electronic and optoelectronic devices given their size-dependent optical and electrical properties as well as the ease of control over size, shape, and composition by high-throughput colloidal synthesis.23,24 The as-synthesized NCs are capped with long and insulating hydrocarbon chains. The arrays of NCs capped with such ligands exhibit poor electrical conduction because of transport bottlenecks at the interfaces. The use of compact organic ligands and post-thermal or chemical treatments of NC solids allowed charge transport through NCs with carrier mobilities on the order of ∼10−4−1 cm2/(V s).23−26 With the goal of improving electronic communication between NCs, a variety of inorganic small molecules have been developed as ligands for colloidal NCs such as metal chalcogenide complexes (MCCs),10 chalcogenides,27 SCN−,28 halides, and halometallates.29 These inorganic ligands act as the electronic linker between NCs and have increased the carrier mobility of NC solids up to ∼30 cm2/(V s).14,15 This enhancement in charge transport originated from the significantly reduced interparticle distance and lowered energetic barrier between adjacent NCs.10,28 Colloidal NCs can also be convenient precursors to fabricate high-mobility thin films through NC sintering. For example, our group has attempted to sinter CdSe NCs capped with In2Se42− MCC ligands and obtained an improved electron mobility over 30 cm2/(V s) compared to that of the nonsintered NC arrays (∼15 cm2/(V s)).14 This level of improvement is decent but not remarkable compared to the electron mobility in CdSe single crystals (∼650 cm2/(V s)).30,31 We think that the enhancement of carrier mobility has been limited by the heterogeneity between the NC and the MCC ligand, which may prevent efficient NC grain growth during sintering and charge transport at the grain boundaries. Very recently, our group reported on the concept of “semiconductor soldering” of technologically important binary and ternary chalcogenide semiconductors such as CdSe, CdTe, PbTe, and Bi2‑xSbxTe3.32 We developed Cd-, Pb-, and bismuth based MCCs, and introduced them as composition-matched molecular “solders” for joining nano-, meso-, and macroscopic chalcogenide semiconductors both mechanically and electronically.32 In particular, the CdSe NCs soldered with Na2Cd2Se3 MCC ligands at 250 °C exhibited a surprisingly high carrier mobility up to ∼200 cm2/(V s).32 These results suggest that semiconductor soldering using colloidal NCs and compositionmatched MCC ligands can be a powerful solution-based route to the fabrication of semiconductor thin films with electron mobility comparable to that in polycrystalline and single crystalline silicon. Therefore, it is timely to study the material and process for understanding the origin of high device performance and to investigate the potential for real-world applications of these devices. Moreover, it is also important to enrich the advantages of the soldering process by exploring possible means to make nanoheterostructures while preserving quantum confinement of NCs, especially for optical and optoelectronic applications. In the present work, we have performed systematic parametric studies of soldered CdSe NC FETs prepared from colloidal CdSe NCs capped with Na2Cd2Se3 MCC ligands. We have also conducted a proof-of-concept study for using the soldering process for nanoheterostructures. Colloidal solutions of CdSe NCs capped with Na2Cd2Se3 MCC ligands were spincoated on various oxide gate dielectrics (SiO2, Al2O3, and

Figure 1. CdSe NC FETs prepared from colloidal CdSe quantum dots capped with [Cd2Se32‑] ligands. (a) Absorption spectra of CdSe NCs capped with ODPA in toluene and capped with Na2Cd2Se3 in hydrazine. (b) Cross-sectional SEM image of a thin film composed of CdSe NCs capped with Na2Cd2Se3 annealed at 250 °C. (c) Schematic illustrations of the experimental procedure and the structure of CdSe NC FET.

absorption spectra of n-octadecylphosphonic acid (ODPA)capped and [Cd2Se3]2−-capped CdSe NCs. The colloidal solution of [Cd2Se3]2−-capped CdSe NCs preserved the original quantum dot excitonic features and showed a small red shift (4 nm) of the first excitonic peak, likely due to the expansion of wave functions into the compositionally matched ligand shell. To make thin films of [Cd2Se3]2−-capped CdSe NCs, solutions of the NCs were spin-coated on top of three different oxide gate dielectric layers prepared on heavily doped Si wafers: (1) commercial thermally grown 100 nm-thick SiO2, (2) ∼ 37 nm-thick Al2O3 grown with atomic layer deposition (ALD), and (3) ∼ 10 nm-thick ZrOx prepared by spin coating ZrOx sol-gel precursors, followed by thermal annealing at 400 °C.33 The NC films were dried at 100 °C for 1 h to remove residual B


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the highest μ (∼210 cm2/(V s) in the linear regime, ∼ 180 cm2/(V s) in the saturation regime). To understand why the FETs showed different performance with different gate dielectrics, we need to take into account the charge per unit area on the semiconductor side of the insulator (Qs). The Qs, determined as the areal capacitance (Ci) multiplied by the maximum gate voltage during operation, is directly related to the filling of trap states in the FET channel.35 With a sufficiently large value of Qs, all localized states can be filled and subsequently injected carriers can move without trapping.35 This consideration provides insight into the superior performance of the ZrOx-based FETs. As shown in Table 1, Qs is about 1.5 times larger for ZrOx-based FETs than for SiO2- and Al2O3based FETs. Having a larger Qs is expected to lead to charge transport with a lower concentration of empty trap sites, resulting in superior carrier mobility. This explanation is supported by the smallest hysteresis in transfer characteristics (Figure 2a−c) and the most well-saturated drain current in output characteristics (Figure 2d−f) of the ZrOx-based FETs.36 In addition, the three different gate dielectrics may cause different concentrations of trap sites at the dielectric−channel interface because of different densities of trapping sites (e.g., hydroxyl groups).33 This interfacial trap density (Ntrap) can be estimated from the subthreshold slope (S) of the FET transfer characteristics: Ntrap ≈ [qS log(e)/kBT − 1]Ci/q, where q is the electronic charge, kB is Boltzmann’s constant, and T is the temperature.37 The CdSe NC FETs with ZrOx gate dielectrics show significantly smaller S than devices with SiO2 dielectrics (Figure 3), resulting in estimated Ntrap values of 9.8 × 1012


solvent. This was followed by thermal annealing at 250 °C to induce soldering of CdSe NCs by Na2Cd2Se3, leading to efficient CdSe grain growth. Figure 1b shows the typical crosssectional scanning electron microscopy (SEM) image of a soldered CdSe NC film on a SiO2 dielectric. To complete topcontact bottom-gate FET geometry, Al source/drain (S/D) electrodes were deposited onto the NC film through a shadow mask by thermal evaporation (Figure 1c). The heavily doped Si wafer served as the gate terminal. All FET fabrication and measurement processes were carried out in nitrogen atmosphere. Figure 2 shows representative transfer (drain current vs gate voltage, ID vs VG) and output (ID vs drain voltage VD)

Figure 2. Device characteristics of soldered CdSe NC FETs with various oxide gate dielectrics. (a, b, c) Representative transfer (ID vs VG) and (d, e, f) output (ID vs VD) characteristics of CdSe NC FETs using (a, d) SiO2 (channel width W = 1500 μm and channel length L = 60 μm), (b, e) Al2O3 (W = 1500 μm and L = 60 μm), and (c, f) ZrOx gate dielectrics (W = 1500 μm and L = 30 μm). In all cases, CdSe NCs in the FET channels were soldered with Na2Cd2Se3 ligands at 250 °C. Figure 3. (a, b) Transfer characteristics of CdSe NC FETs using (a) SiO2 and (b) ZrOx gate dielectrics with on/off ratios and average values of subthreshold slop (S).

characteristics of CdSe NC FETs using SiO2, Al2O3, and ZrOx gate dielectrics (hereafter, CdSe NC FETs using SiO2, Al2O3, and ZrOx gate dielectrics will be referred to as SiO2-, Al2O3-, and ZrOx-based FETs, respectively, according to the identity of the gate dielectric). The properties of the gate dielectrics and NC FETs using the dielectrics are summarized in Table 1. All FETs exhibited remarkably high performance with carrier mobilities (μ) of >90 cm2/(V s).34 These results emphasize the potential of soldered CdSe NCs as the active material of FETs using various gate dielectric materials. Among the three kinds of FETs, the ZrOx-based FETs showed superior performance with

cm−2 and 2.1 × 1013 cm−2 for the FETs using ZrOx and SiO2 dielectrics, respectively. The Ntrap of ZrOx devices is about two times lower than that of SiO2 devices, which supports that, in addition to higher Qs charge, the use of ZrOx gate dielectrics reduces the density of localized trap states at the dielectricchannel interface. Effects of Annealing Temperature on Grain Growth and FET Characteristics of CdSe NC Thin Films. We also studied the effects of annealing temperature on the grain growth of CdSe NCs when soldered with [Cd2Se3]2− molecular solders. First, we performed powder X-ray diffraction (XRD) measurements. Solutions of CdSe NCs with [Cd2Se3]2− ligands were spin-coated onto SiO2 and ZrOx gate dielectrics and then annealed at different temperatures for 30 min. The XRD patterns and the Scherrer size of CdSe grains are shown in Supporting Information Figure S1 and Figure 4a, respectively.

Table 1. Summary of Electrical Properties of Gate Dielectrics and Soldered CdSe NC FETs Annealed at 250°C dielectric

Ci (nF/ cm2)

maximum gate voltage (V)

Qs (μC/ cm2)

μ (cm2/(V s))

SiO2 Al2O3 ZrOx

31.2 192 710

30 5 2

0.938 0.960 1.420

91 102 210 C


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350 °C. At the same time, gate dielectric did not significantly affect sintering and grain growth of CdSe NCs. These results suggest the possibility of improving carrier mobility of soldered CdSe thin films by increasing CdSe NC grain size using elevated annealing temperatures. To check this possibility, we fabricated FETs of [Cd2Se3]2−capped CdSe NCs annealed at 300 and 350 °C using SiO2, Al2O3, and ZrOx gate dielectrics. Supporting Information Figure S3 shows the transfer characteristics of the NC FETs and Figure 4b plots the mobilities of the NC FETs depending on the annealing temperature and gate dielectric.34 All FETs using different gate dielectrics showed an increase in mobility at elevated annealing temperatures, which agreed well with the results of XRD and SEM analyses. The mobility increased by ∼41% for SiO2-based FETs, ∼ 32% for Al2O3-based FETs, and ∼115% for ZrOx-based FETs as the annealing temperature was elevated from 250 to 350 °C. Interestingly, the enhancement of mobility with elevated annealing temperature is much larger for ZrOx-based FETs compared to other devices. Considering the fact that the grain size of the NCs is almost identical at each temperature regardless of the dielectrics (Figure 4a and Supporting Information Figure S2), the predominantly improved performance of ZrOx-based FETs may be due to factors other than the grain size. These surprisingly high carrier mobilities of ZrOx-based FETs could not be artifacts caused by gate leakage currents. As shown in Supporting Information Figure S4, gate leakage currents in the FETs during the gate voltage sweep are about 2−4 orders of magnitude smaller than the ID, suggesting no severe contribution of gate leakage currents to the ID. As shown in Supporting Information Figure S5, our FETs show high mobilities across a wide range of gate voltages, with a linear ID vs VG relation in the VG range for

Figure 4. Temperature-dependent grain size and FET characteristics of [Cd2Se3]2−-capped CdSe NCs. (a) Dependence of the Scherrer grain size on annealing temperature of [Cd2Se3]2−-capped CdSe NCs spin-coated on SiO2 and ZrOx gate dielectrics. (b) Plot of FET mobilities of [Cd2Se3]2−-capped CdSe NCs spin-coated on SiO2 Al2O3, and ZrOx gate dielectrics and annealed at different temperatures. Several, typically five or six, different batches of devices were measured for each experimental condition. For the devices with SiO2 and Al2O3 gate dielectrics, the deviations of mobilities are about ±7− 12 cm2/(V s) depending on the annealing temperature.

As shown in Figure 4a, [Cd2Se3]2−-capped CdSe NCs did not show noticeable grain growth until 200 °C. We found that the NCs started growing rapidly between 200 °C−250 °C and the grain growth was nearly saturated above 350 °C. In addition, the NC films on SiO2 and ZrOx gate dielectrics showed almost the same trend with annealing temperatures and very similar Scherrer grain sizes at each temperature. To examine the morphology of the NCs, we performed SEM measurements of the NCs annealed at 250 °C, 300 °C, and 350 °C (Supporting Information Figure S2). Consistent with XRD results, both the NCs on SiO2 and ZrOx dielectrics showed apparent grain growth as we increased the annealing temperature from 250 to

Figure 5. Operational stability of CdSe FETs and electronic structure of CdSe NCs. (a, b) Transfer characteristics of [Cd2Se3]2−-capped CdSe NC FETs using ZrOx dielectrics for a consecutive cycling of VG sweeps and (e, f) μ and on/off ratio values versus cycling number. The NCs were annealed at (a, e) 250 °C (W = 1500 μm and L = 30 μm) and (b, f) 300 °C (W = 1500 μm and L = 45 μm). (c) Transfer characteristics of [Cd2Se3]2−-capped CdSe FETs using ZrOx dielectrics with a different sweeping rate (W = 1500 μm and L = 30 μm) and (g) μ and on/off ratio values versus sweeping rate. The NCs were annealed at (c, g) 350 °C. (d) Schematic diagrams of electronic structures of CdSe NCs (left) on ZrOx dielectrics and (right) on SiO2 dielectrics, describing operation of FETs. D


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Figure 6. Switching speed measurements of soldered CdSe NC FETs. (a) (bottom) Schematic device structure of the FET used in switching speed measurements and (top) an optical microscopy image showing the top view of the device (W = 280 μm and L = 50 μm). (b) Transfer and (c) output characteristics of the FET shown in (a). (d) Drain current responses to a square wave signal applied to the gate voltage with 1 kHz (left panel) and 200 kHz (right panel) frequencies. (e) Plot of the maximum value of the normalized drain current over the frequency. The solid red line is a guide to the eye and the dotted blue line shows the 70% value of the normalized drain current. The f 3dB was determined at the intersecting point of the two lines.

mobility extraction. This observation confirms that estimated μ values reflect an equilibrium charge carrier concentration and current carrying capability of the device.38,39 Therefore, we conclude that ZrOx gate dielectrics provides a more favorable surface for charge transport at the interface between NCs and the dielectric with reduced density of localized traps, as supported by the analysis of FET subthreshold slopes and interfacial trap densities (Figure 3).15 Combined with the largest value of Qs, the ZrOx gate dielectrics enable FETs with superior characteristics. Relation between Trap Distributions in Soldered CdSe Films and Operational Stability of NC FETs. To evaluate the prospects of soldered CdSe NCs for real-world device applications, we performed a consecutive cycling of gate voltage sweeps for the NC FETs. Each cycle consists of a “forward” gate voltage sweep (VG: from negative to positive) and a subsequent “backward” gate voltage sweep (VG: from positive to negative). For this experiment, we operated ZrOxbased FETs under similar values of Qs as those for SiO2- and Al2O3-based FETs to compare device stability. Therefore, we reduced the maximum gate voltage of ZrOx-based FETs to 1.5 V resulting in a Qs of ∼1.0 μC/cm2 similar to those of SiO2and Al2O3-based FETs. Figure 5a shows the transfer characteristics of ZrOx-based FETs annealed at 250 °C for a consecutive cycling of VG sweeps, and Figure 5e summarizes mobilities and on/off ratios corresponding to the cycling experiment. ZrOx-based FETs showed outstanding electrical stability against a consecutive cycling of gate voltage sweeps without significant drops in both the carrier mobility and on/off ratio (Figure 5e). On the other hand, the SiO2-based FETs showed consistent decreases of both the carrier mobility and on/off ratio during the same experiment (Supporting Information Figure S6). In general, the stability against a consecutive cycling of gate voltage sweeps is closely related to the number of trap

sites and the time scale that the charge carrier spends being trapped on the traps (i.e., trap lifetime).33,40−44 If charge carriers are trapped during an FET operation and those carriers cannot be released before the start of the next cycle, the trapped carriers cannot participate in charge transport, leading to lowered ID and μ. These results provide additional support to our conclusion that the superior performance of ZrOx-based FETs originated from the combination of the lowest density of localized traps and the largest values of Qs, as schematically explained in Figure 5d. The ZrOx-based FETs with NCs annealed at 300 °C also showed an excellent level of stability against the cycling of gate voltage sweeps as shown in Figure 5b and f. We can see evident hysteresis behavior at the low gate voltage region (VG: −0.2 V∼1 V) in the transfer characteristics, with higher channel current during off-to-on switching than the current during onto-off switch. This type of hysteresis behavior can be generally explained by the presence of states in the forbidden gap of a semiconductor as discussed in ref 14. The hysteresis completely disappeared as the positive gate bias increased. The results obtained so far suggest that localized tail states in ZrOx-based FETs are not deep traps but shallow traps42 and that these shallow traps are almost filled up during an FET operation because of the large Qs value. We also performed FET measurements with different sweeping rates of gate voltage in order to get more insight into the localized trap states. Generally, slower sweeping of gate voltage leads to a longer time for charge carriers to stay in the channel, resulting in more charge trapping.24,33,40−42,45,46 As shown in Figure 5c and g, although the carrier mobility slightly decreased as the sweeping rate reduced from 1.20 V/s to 0.54 V/s, the mobility still maintained ∼90% of its initial value. This result also indicates that the number of traps in ZrOx-based E


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Figure 7. Soldering of InAs/CdSe core−shell NCs. (a) Absorption spectrum of organic capped InAs/CdSe core−shell NCs in tetrachloroethylene. (b,c) TEM images of [Cd2Se3]2−-capped InAs/CdSe core−shell NCs (b) before and (c) after annealing at 300 °C for 30 min. (d) Powder XRD patterns of [Cd2Se3]2−-capped InAs/CdSe core−shell NC thin films after drying at 100 °C and annealing at 300 °C. The blue and red vertical lines on the bottom are the corresponding positions and intensities of X-ray reflections for bulk wurtzite-phase CdSe and InAs, respectively. (e) Transfer characteristics of [Cd2Se3]2−-capped InAs/CdSe core−shell NC FETs (W = 1500 μm and L = 60 μm). The gate dielectric is 300 nm-thick SiO2 and NCs were annealed at 300 °C for 30 min. (f) Effect of annealing temperature on electron mobility of [Cd2Se3]2−-capped InAs/CdSe core−shell NC FETs. (g) Photoresponse of FETs made of [Cd2Se3]2−-capped InAs/CdSe core−shell NCs and CdSe NCs annealed at 300 °C, measured upon illumination with 980 nm light at a VG of 0 V and a VD of 9 V.

over the patterned gate electrode (e.g., the fabrication of ZrOx gate dielectrics involves a thermal annealing process at 400 °C, which severely destroys patterned Ti gate electrodes). As shown in Figure 6b and c, the FETs with patterned gate exhibited good transfer and output characteristics with carrier mobilities of ∼84 cm2/(V s). This value is slightly lower than that of normal Al2O3-based FETs using unpatterned, doped Si gate electrodes (∼100 cm2/(V s)). This might result from the reduction of charge carrier injection from the source electrode due to a decrease in the overlap area between the S/D and gate electrodes. To estimate the switching speed of our NC FETs, we measured the ID response over time and applied a square shape VG signal at different frequencies. Figure 6d shows a typical ID response at two different VG signal frequencies, 1 kHz and 200 kHz. Supporting Information Figure S7 shows all the responses at frequencies ranging from 100 Hz to 1 MHz. As shown in Figure 6d and Supporting Information Figure S7, clear on/off responses of the ID have been observed. Sharp current spikes started emerging at the frequency of 100 kHz when the VG signal was being inverted. These current spikes came from parasitic capacitances present between the S/D and gate electrodes.51 It is difficult to eliminate the parasitic capacitance without introducing a fine patterning process and a specialized device architecture for ultra-high-speed measurements.50,52,53 However, our simple devices can be used to evaluate the switching speed and extract the transit time of the charge

FETs is small and the traps are almost inactive during an FET operation. Switching Speed of Soldered CdSe NC FETs. In practical applications, transistors are the key component as switching devices in integrated circuits. The switching speed is therefore important and depends on many device parameters, including carrier mobility.14,47 In addition, measurement of the switching speed allows independent verification of the mobility values extracted from quasistatic FET characteristics. The high carrier mobility of our soldered CdSe NCs offers an opportunity to construct fast switching FETs via a solutionbased route. Therefore, we estimated the switching speed of our NC FETs by measuring the channel current response to square-wave modulation of the gate voltage. In the AC measurements of FETs, parasitic capacitance between the source/drain (S/D) electrodes and the gate electrode plays a crucial role.2,48−50 When an AC VG voltage was applied, the charges induced by parasitic capacitance contribute to an AC channel current.49,50 The amplitude of induced AC current increases as the FET switching frequency is increased and becomes significant at high frequency.49,50 To reduce the effects of parasitic capacitance, we introduced a different device architecture using a patterned titanium gate electrode and an ALD-deposited Al2O3 gate dielectric, as shown in Figure 6a. The ALD-deposited Al2O3 thin films were the best choice among dielectric candidates because they could be deposited at a relatively low temperature (80 °C) with good step coverage F


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connected ∼10 nm-sized crystalline grains. To gain more insight, we performed powder XRD measurements on thin films of InAs/CdSe core−shell NCs capped with [Cd2Se3]2− after annealing at different temperatures for 30 min (Figure 7d and Supporting Information Figure S10). It is obvious that the core−shell NCs were much less sintered than the CdSe NCs capped with [Cd2Se3]2− molecular solders (Supporting Information Figure S1). Both X-ray diffraction and highresolution TEM suggest soldering of CdSe shells. For example, the peaks of wurtzite CdSe phase (2Θ ∼ 24° and ∼27°) gradually got sharper as the annealing temperature increased (Supporting Information Figure S10). Because of similarity in the lattice constants, the diffraction peaks from the InAs core are superposed onto the peaks from the CdSe shell and broadening of the XRD peaks cannot be used to extract information about the sintering of InAs cores. However, our previous studies and control experiments showed that InAs NCs are much more stable against sintering compared to CdSe NCs. Thus, InAs NCs capped with various MCC ligands showed no sign of sintering up to at least 350 °C.12,59 The additional evidence for the absence of sintering of InAs cores was obtained from scanning TEM (STEM) elemental mapping that revealed preservation of InAs cores after sintering CdSe shells (Supporting Information Figure S11). To check the electrical properties of the soldered InAs/CdSe core−shell NCs, we fabricated FET with annealing temperatures of 250 °C, 300 °C, and 350 °C. Figure 7e and f respectively show the transfer characteristics of the soldered InAs/CdSe core−shell NC FETs and the plot of carrier mobilities over annealing temperature. The FETs annealed at 250 °C exhibited good performance with a mobility of ∼4 cm2/ (V s) (Supporting Information Figure S12). As the annealing temperature increased to 300 °C, the performance of the FETs remarkably improved with enhanced mobilities up to ∼26 cm2/ (V s) (see Figure 7f). The mobility did not further increase with annealing at 350 °C. It could be due to suppressed grain growth for CdSe shells caused by pinning of grain boundaries by InAs cores and due to additional electron scattering at the InAs−CdSe interfaces. InAs is a narrow gap semiconductor that can efficiently absorb near-IR radiation. In contrast, CdSe should not absorb light at a wavelength above its fundamental edge at 713 nm at 300 K. We therefore compared photoconductivity of CdSe NCs and InAs/CdSe core−shells, both soldered with [Cd2Se3]2− solder, under illumination with 980 nm (1.27 eV) photons. As shown in Figure 7g, soldered CdSe NCs do not show any photoconductivity at this wavelength. At the same time, the materials made by soldering InAs/CdSe core−shells demonstrated a clear photoresponse at 980 nm, showing that InAs absorb near-IR photons and supply mobile carriers to electronically connected and “soldered” CdSe shells (Figure 7g and Supporting Information Figure S13). We believe that the soldering of nanoheterostructures offers unique potential for designing complex semiconductor solids via appropriate band structure engineering between the quantum-confined core and the shell, aiming at optoelectronic device applications with improved charge transport properties. In summary, we report a record high electron mobility above 400 cm2/(V s) and megahertz switching speeds for solutionprocessed transistors prepared from colloidal CdSe quantum dots capped with Na2Cd2Se3 ligands using the NC soldering process. Various oxide thin films were introduced as gate dielectrics for the CdSe NC FETs and thermal annealing of the

carriers in the FET channel. The transit time between source and drain electrodes (τ) can be expressed as τ = L/(μE) = L2/ (μVD), where E is the electric field. τ can be measured in the frequency domain and related to the −3 dB frequency (the frequency where signal power drops by half) as f 3dB = (2πτ)−1. For our case, these relations, using experimental values of L, μ, and VD, predict τ = 62.5 ns and f 3dB = 2.55 MHz. As shown in Figure 6e, the measured f 3dB of our devices is about 2.3 MHz. The deviation of the measured f 3dB from the ideal value is small and may result from several factors like charge carrier trapping and detrapping.54 In addition, the hysteresis in transfer characteristic also causes additional energy dissipation during transistor switching, which is especially significant for analog circuits.14 The measured f 3dB = 2.3 MHz is orders of magnitude higher than previously reported values for NC FETs14 and comparable to or higher than the f 3dB of the best organic FETs with submicron channels optimized for fast switching.49,50 These switching speeds further support the high carrier mobilities of the soldered NC FETs and demonstrate prospects of these FETs for real-world applications such as RFID tags. We believe that much faster speeds can be achieved when combined with optimized device designs such as dielectric engineering for eliminating hysteresis14 and fine patterning and alignments of S/D and gate electrodes for reducing the channel length as well as parasitic capacitances.52,53 Soldering of InAs/CdSe Core−Shell NCs with Na2Cd2Se3 Molecular Solders. As we have shown in our previous report32 and discussed in this work, the soldering of NCs with composition-matched molecular solders is advantageous for designing chalcogenide semiconductor solids and improving device performance. At the same time, elimination of grain boundaries between individual NCs relaxes the quantum confinement of charge carriers. Taking the benefits of NC soldering while maintaining the quantum-confined nature of NCs or designing materials with embedded nanoheterostructures can open up completely new avenues for solutionprocessed optoelectronic devices.55−58 Here, we report a proofof-concept study for soldering nanoheterostructures using InAs/CdSe core−shell NCs and Na2Cd2Se3 molecular solders. Soldering the CdSe shell with the composition-matched molecular solders improves electrical properties without sintering the InAs cores. InAs core was chosen because (i) it is a typical example of III−V semiconductor;12,59 (ii) the lattice parameter of InAs matches that of the cubic CdSe phase within 1%, favoring epitaxial interfaces; and (iii) we can tailor the optical properties of obtained composite materials in the nearIR region. InAs/CdSe core−shell NCs consisting of a 5.6 nm InAs core and a three-layer CdSe shell were synthesized following the reported recipe with minor modifications.60 The first excitonic peak of InAs NCs shifted from 1265 to 1584 nm as the thickness of CdSe shell increased from 0 to 3 unit cells. This is due to the expansion of the electron wave function into the CdSe shell (see Supporting Information Figure S8 and Figure 7a). The organic ligands of the core−shell NCs were exchanged with Na2Cd2Se3 with the same procedure described in the Supporting Information) for CdSe NCs. As shown in the transmission electron microscopy (TEM) image in Figure 7b, the InAs/CdSe core−shell NCs have an average size of ∼10 nm. After annealing at 250 or 300 °C for 30 min, those NCs formed a continuous thin film and the film was investigated with a TEM (Figure 7c and Supporting Information Figure S9). The TEM images show that the annealed film consisted of well G


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Nano Letters

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NCs formed on the dielectrics at different temperatures was performed to investigate the origin of the outstanding carrier mobility. We think that ZrOx gate dielectrics provide a favorable surface for charge transport of [Cd2Se3]2−-capped CdSe NCs with reduced numbers of localized traps. Our FETs showed carrier mobilities of ∼200−450 cm2/(V s) depending on NC annealing temperatures and remarkable electrical stability against a number of consecutive operation cycles and different gate-voltage sweep rates. The NC FETs using a patterned Ti gate electrode and Al2O3 dielectric exhibited very fast switching speeds with a high f 3dB of ∼2.3 MHz. Finally, we demonstrated high performance [Cd2Se3]2−-capped InAs/CdSe core−shell NC FETs soldered while maintaining InAs quantum dot cores inside the NC films. Collectively, we believe that our work can be a milestone for developing high-performance electronic and optoelectronic devices using a low-cost solution process while retaining electronic properties comparable to those of crystalline semiconductors.

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ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.5b01258. Experimental details, characterization techniques (including figures). (PDF)

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AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. Present Address

(J. J.) Department of Energy Engineering, Hanyang University, Seoul 133-791, Republic of Korea Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS We want to thank P. Phillips and R. Klie at the University of Illinois at Chicago for STEM and EDX elemental mapping measurements. This work was supported by DOD ONR Award Number N00014-13-1-0490, by NSF Award Number DMR1310398 and by II−VI Foundation. We also acknowledge the use of facilities supported by the University of Chicago NSF MRSEC Program under Award Number DMR 14-20709.

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REFERENCES

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Solution-Processed Transistors Using Colloidal Nanocrystals with

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