Statistical Study on the Schottky Barrier Reduction of Tunneling

Dec 23, 2015 - Ta2O5, which has a low conduction band offset(23-25) to MoS2, has been used as the MIS contact insulator (Supporting Information, Figur...
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Letter pubs.acs.org/NanoLett

Statistical Study on the Schottky Barrier Reduction of Tunneling Contacts to CVD Synthesized MoS2 Seunghyun Lee,*,† Alvin Tang,† Shaul Aloni,‡ and H.-S. Philip Wong† †

Department of Electrical Engineering and Stanford SystemX Alliance, Stanford University, Stanford, California 94305, United States The Molecular Foundry, Lawrence Berkeley National Laboratory, Berkeley, California 94720, United States

‡

S Supporting Information *

ABSTRACT: Creating high-quality, low-resistance contacts is essential for the development of electronic applications using two-dimensional (2D) layered materials. Many previously reported methods for lowering the contact resistance rely on volatile chemistry that either oxidize or degrade in ambient air. Nearly all reported efforts have been conducted on only a few devices with mechanically exfoliated flakes which is not amenable to large scale manufacturing. In this work, Schottky barrier heights of metal-MoS2 contacts to devices fabricated from CVD synthesized MoS2 films were reduced by inserting a thin tunneling Ta2O5 layer between MoS2 and metal contacts. Schottky barrier height reductions directly correlate with exponential reductions in contact resistance. Over two hundred devices were tested and contact resistances extracted for large scale statistical analysis. As compared to metal-MoS2 Schottky contacts without an insulator layer, the specific contact resistivity has been lowered by up to 3 orders of magnitude and current values increased by 2 orders of magnitude over large area (>4 cm2) films. KEYWORDS: MoS2, tunneling insulator, low-resistance contact, CVD synthesis

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drive.4 In fact, the high resistance of metal-2D semiconductor contacts have largely been attributed to sizable Schottky barriers4,5 and Fermi level pinning4,7,8 upon band alignment. While earlier reports have reported that gold contacts to MoS2 are ohmic,9,10 the linear I−V relation is limited to the low voltage regime. Many subsequent reports confirm the existence of sizable Schottky barriers at the contacts.4,5 Experimental evidence of Fermi level pinning also has been presented for various metal-2D semiconductor contacts and the pinning is believed to be caused by gap state formation.4,7,8 Various methods have previously been used to reduce the contact resistance of transistors with TMD channels. Chemical adsorption doping techniques such as the use of NO2 gas ambient11 or potassium ions12 to dope contact regions of WSe2-based devices have been shown to reduce contact resistance. Low work function metals have been used as contact metals to form improved contacts with thin MoS2 flakes, resulting in higher carrier injection.4 However, air stability is a major issue with these techniques because adsorbed chemical species may desorb from the surface and the chemical species may react with oxygen and water molecules upon prolonged exposure to ambient air.13,14 Similarly, low work function metals are susceptible to oxidation.15

wo-dimensional (2D) layered materials ranging from zero bandgap graphene to wide bandgap insulators such as boron nitride offer new opportunities in the field of nanoelectronics with its rich variation of physical properties. Although graphene has been the most widely studied 2D material, its lack of a bandgap and the resulting leakage current of graphene transistors severely limits its use. 2D layered materials such as transition metal dichalcogenides (TMDs) provide a solution to this dilemma as most TMDs have a finite bandgap while retaining the ideal qualities of ultrathin 2D materials. Layered TMDs represent the ideal channel material for device scalability as their few-atom thick layers devoid of surface dangling bonds will be robust against short-channel effects down to very short gate lengths for ultrathin short channel devices.1,2 Although TMDs exhibit excellent intrinsic properties for device scaling, creating high-quality, low-resistance contacts is an open challenge in the development of 2D layered materials for electronics applications. While metal contacts to semimetals such as graphene have proven to be less problematic,3 metal contacts to semiconducting TMDs have proven to be more challenging due to Schottky barrier formation.4,5 Conventional substitutional doping method for decreasing the contact resistance of bulk semiconductors is not suitable for lowdimensional materials as doping impurities introduce large strain to the lattice as well as additional defect sites that lower carrier mobility.6 Previous studies show that even small Schottky barriers have significant impact on the device current © XXXX American Chemical Society

Received: September 15, 2015 Revised: December 15, 2015

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DOI: 10.1021/acs.nanolett.5b03727 Nano Lett. XXXX, XXX, XXX−XXX

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Nano Letters A robust, air-stable technique to reduce the contact resistance is to use metal−insulator−semiconductor (MIS) contacts, which are formed by inserting a thin insulator layer between metal and semiconductor. Such a contact structure has previously been shown to reduce the effective Schottky barrier height of metal contacts to Si,16 Ge,17 and III−V material.18,19 The barrier height reduction in these contact structures has been attributed to the attenuation of metal induced gap states (MIGS) 20,21 in the insulator and/or electronic dipole formation22 at the insulator-semiconductor interface. In this work, a systematic study of the application of MIS contacts has been conducted on a large batch of MoS2 devices fabricated using CVD grown large area cm2 scale four-layer MoS2. True Schottky barrier heights were extracted at flat band gate bias conditions for various MIS contact insulator thicknesses. Over 200 two terminal transfer length measurement (TLM) structures were fabricated and measured to present the statistical variation of specific contact resistivity. Ta2O5, which has a low conduction band offset23−25 to MoS2, has been used as the MIS contact insulator (Supporting Information, Figure S1). Large area (>4 cm2), uniform fourlayer MoS2 has been synthesized by CVD method, transferred, and patterned. (Supporting Information, Figure S2 and S3). Although large-scale syntheses of both single-layer and multilayer MoS2 are possible, multilayer (four-layer) MoS2 was used in this work because multilayer MoS2 was found to have lower contact resistance and higher on-current. This is in agreement with several reports claiming that multilayer TMDs have lower contact resistance26 and higher mobility4,27 due to suppression of both quantum confinement effect and interfacial Coulomb impurities scattering. The MIS technique has also been previously applied to metal−TMD contacts by using MgO and TiO2 as the thin insulators.28,29 Although these works also showed reduction in effective Schottky barrier height, no quantitative study on the reduction of specific contact resistivity has been done. Moreover, all of these previous studies used mechanically exfoliated samples with flake sizes on the order of μm2. With such small flake areas, a proper statistical study on the correlation of insulator thickness to specific contact resistivity and effective Schottky barrier height was not feasible due to the limited number of devices. Additionally, no report exists on the application of MIS contacts on larger area cm2 scale TMDs grown by synthesis techniques such as chemical vapor deposition (CVD) that are amenable to large scale manufacturing. Lastly, and most importantly, some of the early works29,30 did not taken into account the influence of the gate field in their calculation of Schottky barrier height. An important goal of this work was to address the limitations of previous works, and in doing so, provide deeper insights for the application of MIS contacts. An optical image of the multilayer MoS2 synthesized on 285 nm thick SiO2 substrate is shown in Figure 1a. The film shows uniform contrast over large area in the microscope image (Figure 1b). Raman spectra taken at 10 random spots on the MoS2 film indicate that the peak frequency difference between the MoS2 characteristic A1g peak (407 cm−1) and the E12g peak (383 cm−1) was 24 cm−1, indicative of 4−5 layer MoS2 according to literature.31 However, it is known that Raman signature becomes less sensitive to layer thickness as the number of MoS2 layers increase,31 and another verification method is necessary to determine the thickness of CVD grown MoS2. The MoS2 film is characterized by atomically smooth

Figure 1. (a) An optical image of the multilayer MoS2 layer synthesized on a SiO2 substrate. (b) A microscopic image of the continuous MoS2 layer with uniform contrast and its Raman spectrum (scale bar: 100 μm). The Raman peak frequency difference between the MoS2 characteristic A1g peak (407 cm−1) and the E12g peak (383 cm−1) was found to be 24 cm−1, indicative of 4−5 layer MoS2. (c) A high-resolution TEM image of the side edge profile of the MoS2 film. The film is polycrystalline as shown from the selected area electron diffraction pattern (inset). (d) Atomic force microscopy (AFM) image of MoS2 layer on SiO2 substrate. (e) MoS2 layer transferred to HfO2 substrate and patterned with lithography.

edges and high crystallinity. From the high-resolution images at the edges (Figure 1c), we can define the thickness of the film to be four layers, a value that is in close agreement with the Raman measurement. A selective area diffraction pattern taken from ∼1 μm in diameter area (Figure 1c inset) shows high-quality crystalline MoS2 with two domains rotated by about 15°, suggesting that typical domain size is about 1 μm. The thickness of the film is further confirmed by atomic force microscopy (AFM) measurement at the edge of the film (Figure 1d). These films can be transferred to an arbitrary substrate and patterned by dry etching as shown in Figure 1e. The side view schematic of the fabricated structure is shown in Figure 2a. MoS2 films were transferred onto a 40 nm thick HfO2 substrate, and various thicknesses of Ta2O5, ranging from 0 to 5 nm, were deposited using atomic layer deposition (ALD) technique (details provided in the Supporting Information). Metal contacts (Ti/Au: 3 nm/30 nm) were then deposited and patterned to form the TLM structures (Figure 2b). The separation between contacts of the TLM structure were varied, and the resistance across the contacts were extracted from the I−V curve and plotted as a function of the contact separation. A representative plot of TLM total resistance vs contact separation is shown in Figure 2c. From such a plot, the specific contact resistivity can be extracted. Devices made from pristine, exfoliated MoS2 flakes are reported to have specific contact resistivities ρc ranging from ∼3 × 10−4 Ω·cm2 to 3 × 10−2 Ω· B

DOI: 10.1021/acs.nanolett.5b03727 Nano Lett. XXXX, XXX, XXX−XXX

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Figure 2. (a) Side view schematic of the fabricated transfer length measurement (TLM) structure. MoS2 films were transferred onto a 40 nm thick HfO2 substrate. Various thicknesses of Ta2O5, ranging from 0 to 5 nm, were deposited using ALD process. (b) Optical microscope image of the TLM structures. The device width was fixed; the separation between contacts was varied, and the resistance across the contacts was measured. (c) Typical plot of the resistance vs contact separation distance. Specific contact resistivity was extracted from the x- and y-axis intercepts. (d) Schematic band diagram of a pinned MoS2 Fermi level. The metal and MoS2 are in direct contact, allowing the tail of the metal electron wave function to decay into the semiconductor bandgap. (e) Schematic band diagram with Ta2O5 inserted between metal and MoS2. The metal wave function is attenuated in the gap states. (f) Schematic band diagram with Ta2O5 inserted between metal and MoS2. Dipole formation at the interface may also lower the effective Schottky barrier. (g) Measured specific contact resistivity ρc as a function of Ta2O5 dielectric thickness.

Figure 3. (a) Energy band diagrams corresponding to the applied gate biases in three distinct regions: below flat band, at the flat band, and above flat band. The contribution from the tunneling current becomes negligible only when VGS is at or below VFB. (b, d) The Arrhenius plot for various gate biases when the thickness of Ta2O5 is 0 nm (b) and 1.5 nm (d), respectively. The slopes of these lines represent the effective Schottky barrier height, for the corresponding gate bias. (c, e) The effective Schottky barrier height as a function of gate bias when the thickness of Ta2O5 is 0 nm (c) and 1.5 nm (e), respectively.

cm2 at zero gate bias using gold as the metal contact.26 From our work, we found the ρc of our CVD grown MoS2 without any modification to be between 3.2 × 10−3 Ω·cm2 and 5.9 × 10−2 Ω·cm2 with Ti/Au contact as shown in Figure 2f. Such relatively high contact resistivity is due to the large barrier height and Fermi level pinning at the metal-MoS2 contact

interface as investigated in many reports.4,5,7,8 To confirm the existence of Fermi level pinning, we measured the Schottky barrier heights for another metal (Pt) contacted to MoS2 and compared it with Ti contacts to extract the pinning factor (Supporting Information S4). From the temperature-dependent measurement, the pinning factor, S, was extracted to be S = C

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Figure 4. Effective Schottky barrier height as a function of gate bias when the thickness of Ta2O5 is 0.5 nm (a), 2.5 nm (b), and 5 nm (c), respectively. (d) The Schottky barrier height at flat band condition as a function of Ta2O5 thickness. (e) The diode current flow across the devices in logarithmic scale for various Ta2O5 thicknesses.

0.107 which was slightly smaller than the S = 0.113 value extracted from the trend line shown in another article.4 According to the MIGS theory,20,21 the metal electron wave function decays into the semiconductor bandgap at the metal− semiconductor junction and charges the interface states of the semiconductor (Figure 2d). This pulls the intrinsic Fermi level (EF,int) at the interface toward the charge neutrality level (ECNL) of the gap states. A thin insulator inserted between metal and semiconductor attenuates the metal electron wave function prior to penetrating the semiconductor (Figure 2e). This results in fewer charges available to move EF,int toward ECNL, as shown in Figure 2e. Another explanation for how the MIS contact structure reduces the effective Schottky barrier height is through dipole formation at the insulator−semiconductor interface. As shown in Figure 2f, interfacial dipoles of opposite polarity can effectively neutralize charges that cause the intrinsic Fermi level (EF,int) to move toward the charge neutrality level (ECNL), reducing the effective Schottky barrier height. From the collective plots of total resistance vs contact separation (e.g., Figure 2c), the specific contact resistivity (ρc) for contacts with varying Ta2O5 thicknesses was extracted, and the data are shown in Figure 2g. The insertion of a 1.5 nm thick Ta2O5 layer resulted in 2−3 orders of magnitude reduction in ρc. However, as the insulator thickness is more than 1.5 nm, ρc increased again. Such an effect is shown in Figure 2g. To understand this trend, the contact resistance of the metal/ insulator/MoS2 MIS contact can be modeled as two resistances in series: the resistance due to the Schottky barrier (RSB) and the resistance due to tunneling through the insulator (RT). Without any insulator, the large Schottky barrier causes RSB to dominate contact resistance. By inserting a thin insulator to reduce the effective Schottky barrier height RSB is greatly lowered while a small RT component is added, effectively reducing the overall contact resistance. Once the insulator is increased beyond an optimal thickness, RT begins to dominate

as current becomes tunneling limited, resulting in higher overall contact resistance. This is the first time such trade-offs between RT and RSB have been observed for metal/insulator/2D material MIS contacts, and the existence of an optimal insulator thickness for MIS contacts is confirmed. To investigate the physical origin of lowering of RSB, temperature-dependent carrier transport measurements were conducted, and the effective Schottky barrier heights ΦSB were extracted for different insulator thicknesses. We note that the effective Schottky barrier heights ΦSB of this work are not equivalent to the Schottky barrier heights of conventional metal/semiconductor junctions. Because the insulator is not accounted for in the expression for current−voltage characteristics (1) employed to determine the barrier height, the effective Schottky barrier heights extracted here are a representation of overall electrical behavior. As illustrated in Figure 3a, the band diagrams depict the contributions of thermionic emission current and thermally assisted tunneling current under various gate bias conditions. When the gate bias is above the flat band voltage, VFB, both components contribute to the current flow during temperature-dependent measurements.4 The contribution from the tunneling current becomes negligible only when the gate voltage is at or below VFB. To extract the accurate ΦSB based on diode eq 1 and thermionic emission theory, ΦSB must be extracted at the flat band voltage condition (VGS = VFB).4 ⎤ ⎛ e Φ ⎞⎡ ⎛ eV ⎞ Id = AT 2 exp⎜ − SB ⎟⎢exp⎜ − ds ⎟ − 1⎥ ⎥⎦ ⎝ kBT ⎠⎢⎣ ⎝ kBT ⎠

(1)

In this equation 1, Id is the current through the device, A is the Richardson’s constant, T is the absolute temperature, kB is the Boltzmann constant, q is the electronic charge, and Vds is the drain to source bias. The values of ln(Id/T2) at a drain bias of Vds = 1 V for various gate biases are plotted in an Arrhenius plot (Figure 3b). The slopes of these lines directly provide the D

DOI: 10.1021/acs.nanolett.5b03727 Nano Lett. XXXX, XXX, XXX−XXX

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ACKNOWLEDGMENTS This work is supported in part by the member companies of Stanford Initiative for Nanoscale Materials and Processes (INMP) affiliate program, and Function Accelerated nanoMaterial Engineering (FAME) Center, one of six centers of Semiconductor Technology Advanced Research Network (STARnet), a Semiconductor Research Corporation (SRC) program sponsored by Microelectronics Advanced Research Corporation (MARCO) and Defense Advanced Research Projects Agency (DARPA). Work at the Molecular Foundry was supported by the Office of Science, Office of Basic Energy Sciences, of the U.S. Department of Energy under Contract No. DE-AC02-05CH11231.

effective Schottky barrier height (units in eV), for the corresponding gate bias, VGS. This extraction is repeated for all measured gate voltages, and the slopes (i.e., effective ΦSB) as a function of the gate voltage is plotted in Figure 3c. For VGS less than or equal to VFB, the effective ΦSB extracted from Figure 3b linearly responds to VGS as shown in Figure 3c. However, as VGS increases above VFB, the tunneling current component becomes relevant, and the plot deviates from its linear relation. Hence the accurate ΦSB extracted at flat band voltage conditions for devices without any Ta2O5 layer was found to be 95 meV (Figure 3c). Compared to this 95 meV barrier height, the ΦSB of devices with the lowest contact resistance was extracted to be 29 meV for a 1.5 nm thick Ta2O5 insulator layer as shown in Figure 3d,e. Such analysis was repeated for other fabricated devices with various thicknesses of Ta2O5 (Figure 4a−c). ΦSB as a function of Ta2O5 insulator thickness is plotted in Figure 4d. Such change in ΦSB had a dramatic effect on the current flow across the devices because of the significant reduction in the specific contact resistivity. In Figure 4e, the current level increased by 2 orders of magnitude after the optimized thickness (1.5 nm) of Ta2O5 was inserted between the metal-MoS2 contact. A linear plot of the transfer curve for devices both with and without the Ta2O5 layer is also shown in Supporting Figure S5. To gain more insight into the effect of the Ta2O5 layer, we extracted the threshold voltages for transistors both with and without a 1.5 nm Ta2O5 layer (Supporting Figure S6). From the gate response of the MoS2 bottom gate transistor, we found a slight decrease in the threshold voltage, VTh, before and after Ta2O5 layer insertion. However, the drive current increased dramatically by several orders of magnitude after Ta2O5 layer insertion. In this work, we demonstrate how a low temperature (200 °C) ALD process can be used to reduce contact resistance of devices fabricated from CVD synthesized large area 2D materials. With ever-growing interest in layered two-dimensional (2D) materials, controlling material interfaces has been a critical challenge in utilizing 2D materials for their unique properties. This has been especially important for recently emerging TMDs because, unlike graphene, these materials have finite bandgaps. The tunneling insulator thickness of this MIS contact technique is highly controllable using conventional ALD tools and does not rely on low-work function metal or volatile chemistry techniques that are unstable in ambient air. This large area contact resistance study on CVD grown films will enable more facile integration of 2D material technology with today’s semiconductor technology.

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ASSOCIATED CONTENT

* Supporting Information S

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.5b03727. Band alignment of MoS2 and Ta2O5; synthesis of large area MoS2; device fabrication process (PDF)

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AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. Author Contributions

S.L. and A.T. contributed equally. Notes

The authors declare no competing financial interest. E

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DOI: 10.1021/acs.nanolett.5b03727 Nano Lett. XXXX, XXX, XXX−XXX