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Functional Inorganic Materials and Devices

Sub-5 nm Monolayer Arsenene and Antimonene Transistors Xiaotian Sun, Zhigang Song, Shiqi Liu, Yangyang Wang, Youyong Li, Weizhou Wang, and Jing Lu ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b03840 • Publication Date (Web): 07 Jun 2018 Downloaded from http://pubs.acs.org on June 7, 2018

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ACS Applied Materials & Interfaces

Sub-5 nm Monolayer Arsenene and Antimonene Transistors Xiaotian Sun1†, Zhigang Song2†, Shiqi Liu2, Yangyang Wang4*, Youyong Li5, Weizhou Wang1* and Jing Lu2,3* 1

College of Chemistry and Chemical Engineering, and Henan Key Laboratory of FunctionOriented Porous Materials, Luoyang Normal University, Luoyang 471934, P. R. China

2

State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871, P. R. China 3 4

Collaborative Innovation Center of Quantum Matter, Beijing 100871, P. R. China

Nanophotonics and Optoelectronics Research Center, Qian Xuesen Laboratory of Space Technology, China Academy of Space Technology, Beijing 100094, P. R. China

5

Functional Nano & Soft Materials Laboratory (FUNSOM) and Collaborative Innovation Center of Suzhou Nano Science and Technology Jiangsu Key Laboratory for Carbon-Based Functional Materials & Devices, Soochow University, Suzhou, Jiangsu 215123, P. R. China.

Email: [email protected], [email protected], [email protected] †

These authors contributed equally to this work.

Abstract Novel two-dimensional (2D) semiconductors arsenene and antimonene are promising channel materials for next-generation field effect transistors (FETs) because of the high carrier mobility and stability under ambient condition. Stimulated by the recent experimental development of sub-5 nm 2D MoS2 FETs, we investigate the device performance of monolayer (ML) arsenene and antimonene in the sub-5 nm region by using accurate ab initio quantum transport simulation. We reveal that the optimized sub-5 nm double-gate (DG) ML arsenene and antimonene metal–oxide–semiconductor FETs (MOSFETs) can fulfill the low power requirements of the International Technology Roadmap for Semiconductors in 2028 until the gate length is scaled down to 4 nm. When the gate length is scaled down to 1 nm, the performances of the DG ML arsenene and antimonene MOSFETs are superior to that of the DG ML MoS2 MOSFETs in terms of the On-current. Therefore, 2D arsenene and antimonene are probably more suitable for ultra–scaled FETs than 2D MoS2 in the post–silicon era.

Keywords: monolayer arsenene and antimonene; sub-5 nm transistor; performance limit; 1

ACS Paragon Plus Environment

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quantum transport simulations; density functional theory

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1．． Introduction Recently, two new semiconducting 2D materials, arsenene and antimonene (As and Sb analogues of graphene, respectively) have been fabricated by various experimental methods,1 such as shear exfoliation,2 mechanical exfoliation,3 liquid-phase exfoliation,4-6 molecular beam epitaxy (MBE),7, 8 and van der Waals epitaxy9 and on several substrates such as InAs substrates,10 Sb2Te3(111), Bi2Te3(111),11 PdTe2,7 and germanium.12 Recently, flat antimonene has also been synthesized successfully on the Ag(111) substrate.8 Because of atomically thin thickness, which enhances gate electrostatics and geometric scaling behavior, and free-dangling-bond smooth surface, which promotes the efficient carrier transport, 2D semiconductors are very promising channel materials in next-generation field effect transistors (FETs).13 Unlike phosphorene, which is easily degraded in air14-17, both arsenene18 and antimonene have high stability, especially antimonene is highly stable under ambient condition over periods of months3, 5

and even in water.3 Remarkably, monolayer (ML) antimonene is predicted to have a high

mobility to 510 cm2/V·s from the ab initio quantum transport simulation, which exceeds that of ML MoS2.19, 20 With the development of the experimental technology, 1 nm–gate–length bilayer MoS2 FET,21 5 nm–gate–length CNT FET,22 and 4~9 nm–channel–length ML MoS2 FET23,

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have been

fabricated. The 1 nm-gate-length bilayer MoS2 transistor using a single-walled carbon nanotube as the gate electrode has exhibited excellent switching characteristics with subthreshold swing (SS) of ~65 mV/dec and a maximum on/off current ratio of 106,21 showing a potential of 2D materials to extend the Moore’s law down to 10 nm. However, the experimental sub-10 nm 2D MoS2 FETs suffer from a low On-currents (less than 250 µA/µm),23-25 a result in agreement with the ab initio quantum transport simulations and associated with their low carrier mobility.26 Because of the low On-current, the switching speed in 2D MoS2 FETs is too slow to meet the requirement of the international technology roadmap for semiconductors (ITRS) for both high performance (HP) and low power (LP) devices in 2024. By contrast, the 5–nm–gate–length CNT FETs show a high

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On-current up to the order of magnitude of 103 µA/µm,22 but the integration of CNT in large scale circuits is difficult.27, 28 In terms of the similar fabrication technique, achieving sub–5 nm arsenene and antimonene FETs is prospective in the near future. Previous theoretical calculations have revealed that ML arsenene and antimonene metal-oxide-semiconductor field effect transistors (MOSFETs) with gate length above 5 nm have excellent device performance, with On-currents superior to the case of ML MoS2 and meeting the ITRS HP goal of 2024.19, 29 However, it is open whether such an excellent performance can be maintained when the gate length is scaled down below 5 nm.30, 31 Apparently, a simulation of the sub–5 nm ML arsenene and antimonene FETs based on rigorous approach is highly desirable to check their performance limit. For the first time, we provide the investigation of sub-5 nm ML arsenene and antimonene ML MOSFETs by using ab initio quantum transport simulations. When the gate lengths are scaled down to 4 nm, the On-state current, delay time and power dissipation indicator (PDP) of the DG ML arsenene and antimonene MOSFETs with proper underlap (UL) structure still could fulfill the International Technology Roadmap for Semiconductors ITRS 2013 goals for the LP devices in 202832. The DG ML arsenene and antimonene MOSFETs can achieve 519 and 452 µA/µm On-state current, respectively, and both of them are greater than the simulated value of DG ML MoS2 at Lg = 1 nm, implying a faster switching speed compared with the latter. Hence, ML arsenene and antimonene are promising channel candidates for nanoscale electronic devices.

2. Model and Method We use the density functional theory (DFT) coupled with the nonequilibrium Green’s function (NEGF) formalism to calculate the transport properties, as implemented in the Atomistix ToolKit 2016 package.33, 34 The drain current Id is calculated through the following Landauer–Bűttiker formula 35 (1) at a given bias voltage Vb and gate voltage Vg: d(Vb ,Vg )=

2e +∞ TE,Vb ,Vg fS E h -∞

− µS − fD E − µD dE

(1)

Where T(E, Vb, Vg) is the transmission coefficient, fS and fD are the Fermi−Dirac distribution 4


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function for the source and drain, respectively, while µS and µD are the electrochemical potential of the source and drain, respectively. Double zeta polarized basis set (DZP) is adopted. We use 75 Ha for the real–space mesh cutoff and k–point meshes36 are sampled with separation of about 0.01 Å–1 in the Brillouin zone. The temperature is set to 300 K. Generalized gradient approximation (GGA) in the form of the Perdew−Burke−Ernzerhof (PBE) functional is employed to describe the exchange and correlation interaction.37 DFT-GGA is a single electron approximation, which turns out to be effective enough to describe the electron behavior in a FET configuration because the electron-electron interaction of the 2D semiconductor channel is greatly screened by doped carriers from the metal electrodes.38-43 To verify the reliability of the ab initio quantum transport simulation at DFT-GGA level, the transfer characteristic for the 1-nm-gate-long MoS2 FET was calculated and generally consistent with the experimental result.21,

44

Especially, the calculated SS of 66 mV/dec is nearly equal to the

experimental one of 65 mV/dec.21, 44

3. Result and Discussion 3.1 Device optimization The optimized lattice parameters of ML arsenene and antimonene are a1 = 3.508 Å and a2 = 4.098 Å, separately. In our device model, double gated two-probe model of the ML arsenene and antimonene MOSFET is constructed with intrinsic ML arsenene/antimonene as channel and degenerately n-doped ML arsenene/antimonene as electrode, as shown in Figure. 1(a). The optimal doping concentration of the source and drain are 1.0×1013 cm−2 from the test. The segments between the gate and source (or drain) are the UL construction, which has been considered with length at the range of 0 to 3 nm. The supply voltage (Vdd) of each device is 0.64 V (= Vb) and equivalent oxide thickness (EOT) is 0.41 nm, which are taken from the ITRS 2028 requirements for HP and LP devices. The typical transfer characteristics of the n–type sub–5 nm DG ML arsenene and antimonene MOSFETs at a bias of Vb = 0.64 V with different gate lengths Lg and ULs are shown in Figure 1(b-e) and Figure 2(a-d), respectively. The Off-state current Ioff is set to 0.1 µA/µm and 5×10-5 µA/µm according to

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the ITRS HP and LP standard, respectively. Ileak are in the range of 2.2×10-8 ~ 2.1×10-4/7.5×10-7 ~ 2.4×10-4 µA/µm for the sub-5 nm DG ML arsenene/antimonene MOSFETs. All the Ileak are low enough to meet the ITRS HP Off-state goal of 0.1 µA/µm while some of the Ileak are higher than the ITRS LP Off-state goal of 5×10-5 µA/µm. Then Ion (HP) and Ion (LP) are obtained at Vg (on/HP) = Vg (off/HP) + Vdd and Vg (on/LP) = Vg (off/LP) + Vdd, respectively. The key figures of merit of the sub-5 nm DG ML arsenene and antimonene MOSFETs with UL= 0 - 3 nm are benchmarked against those of the ITRS 2028 requirements for HP and LP transistors in Table 1 and 2, respectively. 3.2 On current For the logic transistors, Ion is one of the crucial parameters to evaluate their switching speed. A high Ion is beneficial for application in such as high-performance servers with high switching speed. We demonstrate the On-state currents of the arsenene and antimonene MOSFETs in Figure. 3(a, b) and (c, d), respectively. Ion of the arsenene and antimonene HP MOSFET monotonously decreases rapidly with the decreased Lg without underlap. Ion of the HP transistors (IonHP) of the sub-5 nm DG ML arsenene/antimonene MOSFETs (96 ~ 770/85 ~ 775 µA/µm) with ULs = 1~3 nm are always larger than those (71~ 716/61 ~ 648 µA/µm) without UL at the same Lg except for Lg = 4 nm. The reduced size generally has a negative effect on the device performance. For example, the On-current of the DG ML arsenene/antimonene HP device reduces from 648/716 µA/µm to 71/61 µA/µm at Lg = 4 nm to at Lg= 1 nm without underlap. The improvement of Ion by UL is generally more effective for shorter Lg (less than 3 nm). The previous research only predicted the UL = 2 nm can improve the On-current of the DG ML arsenene/antimonene at Lg = 5 nm19. Whether the influence of UL is positive or negative also depends on the Lg. For example, Ion of the DG ML antimonene decreases from 736 to 658 µA/µm when the UL changes from 2 to 3 nm at 2-nm-gate-length. Among all the different constructive HP transistors, the largest Ion of the DG ML arsenene/antimonene MOSFETs is 770/775 µA/µm with the structure of Lg = 2/3 nm and UL = 2 nm, which is just lower than the value of 9 × 102 µA/µm for the ITRS 2028 requirements for HP transistors by 14.4/13.9 %.

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Previous experiments have shown that 2D MoS2 is an excellent channel material, and the 2D MoS2 FETs with Lg = 1 nm have been fabricated21 and own a rather small threshold swings. Compared with the calculated Ion (15 ~ 102 µA/µm)

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of the 1-nm-gate-length MoS2 HP

transistors with ULs = 0 ~ 4 nm (also shown in Figure. 3), Ion of the 1-nm-gate-length arsenene/antimonene MOSFETs (61 ~ 519 µA/µm) are generally larger with ULs = 0 ~ 3 nm. The optimal Ion value of 519 µA/µm for the DG ML arsenene/antimonene MOSFETs with Lg = 1 nm and UL = 3 nm is four times larger than that of 102 µA/µm for the optimal ML MoS2 counterpart at the same calculation level. The larger On-state currents of our DG ML arsenene/antimonene MOSFETs than the DG ML MoS2 MOSFETs are attributed to their electronic property difference (See Discussion section). Both of the DG ML arsenene and antimonene MOSFETs are also better than those of DG ML MoS2 MOSFETs within the gate length of 5 nm. For example, the n-type DG ML MoS2 MOSFET owns an On-current of 334 µA/µm at 3-nm-gate-length and 2-nm-underlap among all the sub-5 nm devices while the DG ML arsenene/antimonene MOSFET owns an On-current 756/775 µA/µm at the same scale. Compared with the HP applications, the LP applications focus more on the static energy saving and require ultra-low Off-state current. Hence, Ion of the LP applications depends on the subthreshold characteristic of the MOSFET. As shown in Figure. 3(b) and (d), unlike the HP applications, Ion of the LP devices decreases progressively with the shortening gate length and drops to only 11 µA/µm when Lg scaled down to 2 nm. The optimal UL is 3 nm at 2 nm ≤ Lg ≤ 4 nm for both of the DG ML arsenene and antimonene MOSFETs in the LP application. Remarkably, with UL = 3 nm, the On–currents of the DG ML arsenene and antimonene MOSFETs are 677 and 475 µA/µm at Lg = 4 nm, respectively, both of which can meet the ITRS LP goal (295 µA/µm). With a shorter UL of 2 nm, the On–current of the 4-nm-gate-length DG ML arsenene MOSFETs (385 µA/µm) can full fill the ITRS goal while the antimonene MOSFETs only can fill 83% at the same scale. 3.3 Gate control Subthreshold swing (SS) primarily describes the subthreshold characteristics to indicate the the

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gate control ability at the subthreshold region. The definition of the gate control ability at the subthreshold region is SS =

g . ∂lgId

Given the same UL, the value of SS for our DG ML

arsenene/antimonene MOSFETs increases obviously with the decreasing Lg, as shown in Figure. 4(a) and (b). Actually, compared with SS (55 ~ 113 mV/dec)19 of the DG ML arsenene/antimonene MOSFETs with longer Lg = 5~10 nm, the SS values ( 76 ~ 282 mV/dec) for the sub-5 nm arsenene/antimonene devices are much larger. Given the same Lg, SS is decreased with the increasing UL. For example, the SS values of the arsenene MOSFETs with Lg = 1 nm are 220/209/169/139 mV/dec for UL = 0/1/2/3 nm, respectively. Compared with the optimal simulated SS of 66 mV/dec in 1nm-gate-length DG ML MoS2 MOSFETs,44 the SS of arsenene and antimonene device are much larger. This indicates the poor gate-controllability of sub-5 nm arsenene/antimonene devices than the MoS2 in the subthreshold region. Transconductance gm (=

Id )

Vg

is a good indicator to characterize the gate control ability at the

superthreshold region, as shown in Figure. 4 (c) and (d). Without UL, shortening Lg of DG ML arsenene/antimonene MOSFETs will lead to the decrease of transconductance from 1991/1979 µS/µm to 969/971 µS/µm. In both arsenene and antimonene devices, there is no obvious effect on gm value with 3-nm UL at any gate length. The use of 2 and 1 nm ULs at Lg = 1 and 2 nm, respectively, can effectively improve the superthreshold gate control of arsenene/antimonene device with gm increasing to 1947/1830 µS/µm and 2156/2234 µS/µm, respectively. However, the using of ULs at Lg = 4 nm can degrade gm by 46.8/35.8% compared with the devices without UL in arsenene and antimonene MOSFETs. Different from the gate-controllability in the subthreshold, the gate control of the DG ML arsenene and antimonene MOSFETs is much better than that of DG ML MoS2 devices in the superthreshold region and leads to a larger On-current. For example, the optimal transconductance (at UL = 2 nm) of the 1 nm–gate–length DG ML MoS2 MOSFETs is 340 µS/µm which is only in 1/6 and 1/3 of those of the DG ML arsenene and antimonene devices with the same configuration, respectively (see Figure. 4 (c) and (d)). Thus, the On-state current of 1 nm–gate–length DG ML arsenene/antimonene MOSFETs (UL = 2 nm) for HP applications can reach to 224/229 µA/µm which are much larger than the same case MoS2 device 8


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of 102 µA/µm. In order to understand the mechanism of gate modulation, we have computed the local density of state (LDOS) for the 1-nm-gate length DG ML arsenene MOSFETs with UL = 3 nm in Figure. 5 (a-c). The effective barrier height ΦB is 0.35 eV at Vg = −0.9 V (Off state). As Vg increases, ΦB is greatly reduced to 0.12 eV at Vg= −0.6 V (intermediate) and zero at Vg = -0.26 V (On state). Therefore, the current is logarithmically increased to saturation as Vg increases. From the spectral current, the total current is composed by Itunnel and Itherm out of the bias window, as shown in Figure. 5(a) - (c). Therefore, we calculate the correspondingly transmission eigenvalues and eigenstates at E = −0.35 eV and the Γ point under Vg = -0.26, 0.6, and -0.9 V, respectively. The transmission eigenvalues decrease significantly from 0.66 at On-state and 6.97 × 10−3 at intermediate state Vg = -0.6 V to 5.27 × 10−5 at Off-state. The change of the transmission eigenstates is shown in Figure. 5(d), where the incoming electron wave function passes through the entire channel and reaches the drain region at On-state, partially passes through at intermediate state, and is forbidden at Off-state. 3.4 Intrinsic delay time and power consumption The intrinsic delay time (τ) usually indicates the switching speed. The lower delay time (τ) indicates the faster switching speed. It is calculated by the formula: =

CgVdd , Ion

where Vdd is the

supply voltage, Ion is the On–state current, and Cg is the gate capacitance, which is defined as Cg =

Qch ,

Vg

where Qch is the total charge in the region of gate. The total gate capacitance of the

arsenene/antimonene is in the range of 0.013 ~ 0.062/0.013 ~ 0.530 fF/µm, which are much lower than the ITRS goals for both HP (0.60 fF/µm) and LP (0.69 fF/µm) requirements and indicate a good gate control. The delay time of the device with a well-defined Ion (Ioff of this device can reach ITRS standard for HP or LP in 2028) can be calculated. The calculated τ of the sub-5 nm DG ML arsenene/antimonene MOSFETs with and without UL are given in Figure. 6/7 (a) and (b). With so small Cg, all of the intrinsic delay time (0.020 ~ 0.135/0.022 ~ 0.195 ps) for HP application of arsenene/antimonene MOSFETs are much lower than the ITRS HP standards (0.423 ps). For the shorter Lg (≤ 2 nm), the UL can effectively decrease the delay time to one 9



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order of magnitude smaller than of ITRS HP standards. Most of the delay times are four times to twenty times lower than the ITRS HP standards, so the sub-5 nm DG ML arsenene/antimonene MOSFETs own excellent ability as the fast switching devices. For the LP applications, the delay time of arsenene transistors can meet the ITRS standards at the Lg ≥ 3 nm and proper UL. With the construction of Lg = 2 nm and UL = 2 nm, the delay time of arsenene device is 101.060 ps and it can be sharply decreased to 1.500 ps with UL = 3 nm. Similar to DG ML arsenene MOSFETs, the delay time of antimonene device can be decreased from 1.618 ps with UL = 2 nm to 0.105 ps with UL = 3 nm at the Lg = 3 nm. At the gate length of 4 nm with UL ≥ 1 nm, all the delay time of both ML arsenene and antimonene MOSFETs can meet the standards for LP in ITRS 2028. The delay time that can meet or almost fill the ITRS LP goals are shown in Figure. 6/7 (b). Another major concern for FETs applications is the power consumption, and it is can be indicated by the PDP per width which is defined as PDP =

(Qon - Qoff)·Vdd ,

where Qon and Qoff are the

total charges in the region of the gate at the states of On- and Off-, respectively, and W is the channel width. From Figure. 6 (c-d) and 7 (c-d), the PDPs decrease monotonically with the decreasing Lg for both HP and LP applications. The PDPs of our sub-5 nm DG ML arsenene and antimonene MOSFETs are one to two order of magnitude smaller than the ITRS HP/ LP 2028 requirement of 0.24/0.28 fJ/µm. Encouragingly, with the optimal Ion that can fulfill the ITRS LP standards in 2028, the transistors with the configuration of 4-nm-gate-length and proper UL (2 - 3 nm for arsenene device and 3 nm for the antimonene device) have at least one order of magnitude less cost of switching energy and twenty times faster switching speed compared with the ITRS HP 2028 target. 3.5 Discussion For the antimonene system, the spin orbital coupling (SOC) is strong. We have checked SOC’s influence on the band structure of ML antimonene and transport properties of the ML antimonene FET. The SOC brings about a 0.27 eV decrease in the band gap of ML antimonene, as shown in Figure S1 (a) but has no obvious effect on the dispersion of the conduction band, a result consists with the previous calculation29. We check the effect of the SOC on the transfer curve of the n-type 10


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DG ML antimonene MOSFET with Lg = 1 nm and UL = 0 nm, as shown in Figure S1 (b). From Figure S1 (b), the transfer curves of the n-type DG ML antimonene MOSFET with and without SOC are quite similar to each other. Therefore, the device performance of the n-type DG ML antimonene MOSFETs is nearly intact with inclusion of the SOC due to the nearly intact conduction band of ML antimonene. In the real situation, arsenene and antimonene are fabricated on the substrate such as InAs, Sb2Te3(111) and so on. These substrates are rough surface. They will bring trap or charge impurity into the interface and will limit the carrier mobility of arsenene and antimonene. The lower carrier mobility will degrade the performance of the device. However, some substrates such as the atomically flat hexagonal h-BN monolayer is expected not to affect the device performance of the arsenene/antimonene FET since h-BN monolayer owns smooth surface and no charge impurity is formed at the interface. Actually, when placed on h-BN substrate, the mobility of graphene is comparable to that of free-standing graphene45. As a result, the mobility and device performance of the arsenene/antimonene FET is expected to be nearly intact when stacked on the hexagonal h-BN substrates. Therefore, the device performance of the free-standing ML arsenene and antimonene FETs what we deal with can approximately represent that of the ML arsenene and antimonene FETs on hexagonal h-BN substrate and is the upper limit of the device performance. Previous research has shown that the ML phosphorene shows a good performance in the sub-5 nm ML MOSFETs44, so here we compare the performance of ML arsenene/antimonene with ML phosphorene in the sub-5 nm DG ML MOSFETs. The DG ML phosphorene MOSFETs are divided into two kinds that the one is along the x-direction and another is along the y-direction. At the gate length within 2 nm and underlap within 3 nm, Ion of all the DG ML arsenene and antimonene MOSFETs are higher than those of the x-direction DG ML phosphorene MOSFETs for both HP and LP applications. However, Ion of y-direction DG ML phosphorene MOSFETs for HP and LP devices are all higher than those of all the arsenene and antimonene MOSFETs (all the comparisons are made in the same scale conditions). The SS values of the DG ML arsenene and

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antimonene MOSFETs are all lower than those of the x-direction DG ML phosphorene MOSFETs and higher than those of the y-direction DG ML phosphorene MOSFETs. In terms of the delay time, all these DG ML MOSFETs are almost equal to each other for the HP application which indicate they own similar switch speed. But for the LP applications, the switch speeds of the DG ML arsenene and antimonene MOSFETs are faster than those of the x-direction DG ML phosphorene MOSFETs and slower than those of the y-direction DG ML phosphorene MOSFETs. Another major concern for FETs applications is the power consumption. Because the power consumptions of the DG ML arsenene and antimonene MOSFETs are all smaller than those of all the x-direction and y-direction DG ML phosphorene MOSFETs, the DG ML arsenene and antimonene MOSFETs have an advantage in the cost of switching energy. From the previous research, the band gap of ML arsenene/antimonene are 1.76/1.65 eV,19 which are lower than the one of 1.8 eV of ML MoS2 46 at the PBE level. ML MoS2 owns a heavier electron effective mass of 0.579 m0 (m0 is the free electron mass) than arsenene and antimonene ML (0.28 m0 for both of them19). With a lighter electron effective mass and smaller band gap, the On-currents of 1-nm-gate length DG ML arsenene and antimonene MOSFETs are thus higher than that of the DG ML MoS2 counterpart at the same scale. But the band gaps and effective masses of arsenene/antimonene remain too high to provide a very high carrier speed. As a result, they can`t satisfy the ITRS goal for the HP application in 2028. On the other hand, the large band gaps suppress the tunneling, which favors the less power consumption. Hence, the 4-nm gate length DG ML arsenene and antimonene MOSFETs can fulfill 2028 requirements of ITRS for LP devices. The subthreshold slope of these sub-5 nm MOSFETs are higher than 60 mV/dec, which is the limit of thermal carrier injection mechanism. Adding a ferroelectric layer to the gate stack of ML arsenene/antimonene MOSFETs can form a negative capacitance FET, which may offer a promising solution to break the 60 mV/dec limit on SS47. Combined with two split gates with opposite voltage will inject holes and electrons into the channel, a arsenene/antimonene p–n junction is realized, and it may be used for the solar-energy conversion and light emission as the

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WSe2 lateral p–n junction48. This homogeneous p-n junction also can constitute a arsenene /antimonene in-plane tunneling FET and has a potential to break the 60 mV/dec limit on SS. Moreover, vertical stack of arsenene/antimonene with other 2D materials such as monolayer transition metal dichalcogenides can constitute a vertical hetero-junction tunneling FET, which even has a better device performance than homogeneous in-plane TFET49, 50.

4．．Conclusion To summarize, we simulate the performance limitation of the DG ML arsenene/antimonene MOSFETs at sub-5 nm scale by using ab initio quantum transport calculations. With optimal doping concentration and underlap configuration, we predict that the On-state current of the DG ML arsenene/antimonene MOSFETs at gate length of 1 nm is five times larger than that of the ML MoS2 counterpart. More encouragingly, until the gate length is scaled down to 4 nm with proper UL configurations, our DG ML arsenene/antimonene MOSFETs can even fulfill the 2028 standards of the ITRS for LP devices in terms of the On-current, the delay times and power dissipations indicator. Besides, the delay times and power dissipations indicator surpass the 2028 requirements of ITRS for HP devices significantly even at an ultimate gate length of 1 nm. We propose that ML arsenene and antimonene are competitive channel materials for the sub-5 nm transistors in the near future.

Acknowledgement This work was supported by Foundation of He'nan Educational Committee (Grant No. 17A430026),

the

National

Natural

Science

Foundation

of

China

(Nos.

11704406

/21773104/11674005/11664026), Ministry of Science and Technology (Nos. 2016YFB0700600 (National Materials Genome Project) and 2016YFA0301300) of China and Doctoral startup fund (Grant No. 300101/4600169). This is also a project supported by the He'nan Key Laboratory for Function-Oriented Porous Materials. Supporting Information

13



The Supporting Information is available free of charge on the ACS Publications website: Comparison of the band structure of ML antimonene and the transfer curve of the DG ML antimonene n-type MOSFET (Lg = 1 nm and UL = 0 nm) without and with SOC.

References 1.

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17



Page 18 of 27

Table 1. Benchmark of the ballistic device performances of the sub-5nm DG ML arsenene and antimonene MOSFETs against the ITRS requirements for HP transistors of the next decades (2013 version). The Off–state current is set to 0.1 µA/µm in terms of the ITRS HP standards. Vdd: supply voltage; SS: subthreshold swing; Cg: intrinsic gate capacitance; τ: delay time; PDP: power dissipation. Lg (nm) ITRS HP

5.1

UL (nm) 0

Vdd (V) 0.64

0 1

1 2

0.64

2

0.64

3

1 2 3

4

1

1 2

0.005

9.60×10

0.014

0.094

0.005

2.94×10

3

0.013

0.029

0.005

5.19×10

3

0.013

0.015

0.011

3.05×10

3

0.030

0.064

0.011

6.37×10

3

0.037

0.037

0.012

7.70×10

3

0.026

0.022

0.011

710

7.10×10

3

0.026

0.023

0.009

600

3

673

99

756 757 716

110

631

90

742

0.039

0.042

0.017

6.73×10

3

0.034

0.033

0.018

7.56×10

3

0.027

0.023

0.014

7.57×10

3

0.023

0.020

0.011

7.16×10

3

0.062

0.055

0.027

6.31×10

3

0.053

0.054

0.024

7.42×10

3

0.043

0.037

0.018

3

0.032

0.028

0.019

6.0×10

7.27×10

0

282

61

6.12×102

0.019

0.195

0.005

85

8.46×10

2

0.016

0.121

0.005

2.29×10

3

0.015

0.043

0.005

4.52×10

3

0.013

0.019

0.006

2.26×10

3

0.031

0.089

0.010

4.92×10

3

0.029

0.038

0.011

7.36×10

3

0.027

0.024

0.011

6.58×10

3

0.023

0.023

0.010

6.24×10

3

0.036

0.037

0.016

7.14×10

3

0.033

0.030

0.017

7.75×10

3

0.030

0.025

0.015

7.28×10

3

0.025

0.022

0.012

6.48×10

3

0.053

0.052

0.028

6.22×10

3

0.052

0.053

0.025

7.41×10

3

0.043

0.037

0.019

7.64×10

3

0.030

0.026

0.015

1 2

0.64

1 2

1 2

0.64

3

229 452 226

153

492

109

736

122

658

147 0.64

624

124

714

108

775

91

0

2

180

180

3

1

213

141

0

4

0.135

727

3

3

0.015

2

78

0

Antimonene

7.11×10

3

3

2

124

139 0.64

0.24

770

87

0

0.423

637

169 0.64

0.600

2

305

100

0

9.00×10

519

123

PDP (fJ/µm)

294

147

τ (ps)

96

169

Cg (fF/µm)

71

209

Ion/Ioff 3

900

209

3

Arsenene

–

139

0 1

Ion (µA/µm)

220

3

2

SS (mV/dec)

728

118 0.64

648

103

622

90

741

76

764

18


Page 19 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Table 2. Benchmark of the ballistic device performances of the sub-5nm DG ML arsenene and antimonene MOSFETs against the ITRS requirements for LP transistors of the next decades (2013 version). The Off–state current is set to 5.0×10-5 µA/µm in terms of the ITRS LP standards. The sign “–” represents no valid data.

ITRS LP

Lg

UL

Vdd

SS

Ion

(nm )

(nm)

(V)

(mV/dec)

(µA/µm)

5.9

0

0.64

2

Arsenene

3

4

1

2

Antimonene

3

4

6

Cg

τ

PDP

(fF/µm)

(ps)

(fJ/µm)

0.600

1.493

0.28

–

295

5.90×10

220

–

–

0.015

–

–

209

–

–

0.014

–

–

169

–

–

0.013

–

–

3

139

–

–

0.013

–

–

0

209

–

–

0.030

–

–

147

–

–

0.037

–

–

123

–

–

0.026

–

–

0.026

1.500

0.006

0.039

–

–

0 1

Ion/Ioff

1 2

1 2

0.64

0.64

3

100

11

2.2×10

0

169

–

–

124

–

–

1 2

0.64

99

33

5

0.034

–

–

6.55×10

5

0.027

0.523

0.008

6

0.023

0.089

0.008

3

87

165

3.30×10

0

139

–

–

1 2

0.64

110

59

90

385

0.062

–

–

1.18×10

6

0.053

0.576

0.010

7.71×10

6

0.043

0.071

0.012

7

0.032

0.030

0.014

3

78

677

1.35×10

0

282

–

–

0.019

–

–

213

–

–

0.016

–

–

180

–

–

0.015

–

–

3

141

–

–

0.013

–

–

0

180

–

–

0.031

–

–

153

–

–

0.029

–

–

109

–

–

0.027

–

–

0.023

1.361

0.006

1 2

1 2

0.64

0.64

5

3

122

11

2.2×10

0

147

–

–

0.036

–

0.024

124

–

–

0.033

–

0.014

108

12

2.4×105

0.030

1.618

0.008

6

0.025

0.105

0.008

1 2

0.64

3

91

152

3.5×10

0

118

–

–

1 2 3

0.64

0.053

–

–

5

0.052

0.875

0.010

103

38

7.6×10

90

254

5.1×106

0.043

0.109

0.012

475

6

0.030

0.041

0.011

76

9.5×10

19



(a)

As

(b)

I (µΑ/µm)

103 10

UL =

0 nm

1 nm

(c)

Lg=1 nm

IHP off

10

10-3

3 nm

Lg = 2 nm IHP off

-1

10-4 I

-6

(d)

2 nm

102

0

10

I (µΑ/µm)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 20 of 27

-2.8 -2.1 Lg = 3 nm

-1.4

-0.7

LP off

0.0

102 -1

-7

10 0.7(e) -2.0 -1.5 103 Lg= 4 nm

IHP off

10

-1.0

-0.5

0.0

0.5

IHP off

100 10

-3 LP

-4

10

I 10-7 -2.0

ILP off

-1.5

-1.0 -0.5 Vg (V)

0.0

LP off

0.5

Ioff

10-6 10-9

-1.5

-1.0

-0.5 Vg (V)

0.0

0.5

Figure 1. (a) Schematic view of the sub-5 nm DG ML arsenene/antimonene MOSFET. (b-e) I-Vg characteristics of the sub 5-nm DG ML arsenene-MOSFETs at the bias of Vb = 0.64 V with UL at the range of 0-3 nm and gate length at the range of 1-4 nm.

20


Page 21 of 27

Sb UL = 0 nm

1 nm

I (µΑ/µm)

(a) L = 1 nm g

10

2 nm

3 nm

(b) L = 2 nm g

102

102

IHP off

-1

10-4

IHP off

10-1 10-4

LP off

ILP off

I 10-7

(c)

I (µΑ/µm)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


-2.4

-1.8

-1.2

-0.6

10-7

0.0

103 Lg = 3 nm

102

100

IHP off

-1.8

-1.2

-0.6

0.0

IHP off

10

10-4 ILP off -1.5

-1.0 -0.5 Vg (V)

0.0

0.6

Lg = 4 nm

-1

10-3 10-6 -2.0

-2.4

(d)

10-7 0.5 -2.0

ILP off -1.5

-1.0 -0.5 Vg (V)

0.0

0.5

Figure 2. (a-d) I-Vg characteristics of the sub 5-nm DG ML antimonene-MOSFETs at the bias of Vb = 0.64 V with UL at the range of 0-3 nm and gate length at the range of 1-4 nm, separately.

21



As UL = 0 nm 1 nm 2 nm 3 nm

(a)

Ion (µΑ/µm)

800

Sb UL = 0 nm 1 nm

(b)

I

HP on

750

450 400

300

200

As

MoS2

(c)

MoS2

2 nm 3 nm

UL = 0 nm

2 nm 4 nm

As

600

600

0

Ion (µΑ/µm)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 22 of 27

1

2

3

150

(d)

600

MoS2

0

4

HP 800 Ion

ILP on

1

450

Sb

300

ILP on

2

3

4

3

4

400 150 200

Sb

MoS2

0 1

2

Lg (nm)

3

4

MoS2

0 1

2

Lg (nm)

Figure 3. (a–d) On–current as a function of the gate length in the DG ML arsenene and antimonene MOSFETs for the HP (a, c) and LP (b, d) applications. Black dashed lines represent the ITRS HP and LP requirements in 2028. The data of the simulated DG ML MoS2 MOSFET at Lg = 1 nm with different ULs are shown for comparison.44

22


Page 23 of 27

SS (meV/dev)


(a)

Sb UL = 0 nm 1 nm 2 nm 3 nm

240

160

160

80

(c)

2

3

4

(d)

2x103

2x103

1x103

1x103

As

0

1

2

Sb

80

60 mV/dec

1

3

MoS2 UL = 0 nm 2 nm 4 nm

(b)

As

240

gm (µS/µm)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


4

60 mV/dec

1

2

3

4

Sb

0

1

2

3

4

Lg (nm)

Lg (nm)

Figure 4. (a-b) Subthreshold swing (SS) and (c-d) transconductance (gm) as a function of the gate length in DG ML arsenene and antimonene MOSFETs with different ULs, respectively. The data from the simulated DG ML MoS2 MOSFETs at Lg = 1 nm with different ULs are shown for comparison. 44

23



Figure 5. Position resolved local density of states (LDOS) and the spectral current in the channel region for the DG ML arsenene MOSFETs with Lg = 1 nm and UL = 3 nm at (a) Vg = -0.26 V, (b) Vg = -0.6 V, (c) Vg = -0.8 V, respectively. Bias window of 0.64 V is indicated by the two horizontal black dash lines. The µs and µd are the electrochemical potential of the source and drain, respectively. ΦB is the effective barrier height. The spectral currents of x–axis are in logarithm scale and the ratio of Itunnel to Itherm is not the proportional to the shade area. (d) Transmission eigenstates at E = 0.35 eV and the Γ point under On-state (Vg = -0.26 V), intermediate (Vg = -0.6V), and Off-state (Vg = -0.90 V) states. The isovalue is 0.15 a.u.

24


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Page 25 of 27


(a) 0.5

τ (ps)

0.4

MoS2 UL = 0 nm 2 nm 4 nm

(b) 2.4

ITRS for HP

2.1 1.5

0.2

ITRS for LP

1.0 0.1 0.5 0.0 0.0

(c) 0.30 0.25

1

2

3

4

(d)0.30

ITRS for HP

0.28 0.26

PDP (fJ/µm)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


1

2

3

4

3

4

ITRS for LP

0.02 0.01

0.01 0.00

1

2

3

0.00

4

1

Lg (nm)

2

Lg (nm)

Figure 6. (a-b) Intrinsic delay time (τ) and (c-d) power dissipation (PDP) as a function of the gate length in DG ML arsenene MOSFETs with UL = 0, 1, 2 and 3 nm, respectively. Black dashed lines are the ITRS HP and LP requirements for τ and PDP in 2028, respectively. The delay time and PDP of the DG ML arsenene MOSFETs that can meet the ITRS requirements are shown. For details, please check Tables 1 and 2.

25



(a)

Sb UL = 0 nm 1 nm 2 nm 3 nm

0.5 ITRS for HP

0.4

MoS2

(b)

UL = 0 nm 2 nm 4 nm

1.5 ITRS for LP

0.2

τ (ps)

1.0 0.1

0.0

(c)

PDP (fJ/µm)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 26 of 27

0.24 0.22

0.5 0.0 1

2

3

4

(d) 0.30 0.28

ITRS for HP

1

2

3

4

ITRS for LP

0.02 0.01 0.01 0.00

1

2

3

0.00

4

1

2

3

4

Lg (nm)

Lg (nm)

Figure 7. (a-b) Figure 4 (a-b) Intrinsic delay time (τ)and (c-d) power dissipation (PDP) as a function of the gate length in DG ML antimonene MOSFETs with UL = 0, 1, 2 and 3 nm, respectively. Black dashed lines are the ITRS HP and LP requirements for τ and PDP in 2028, respectively. Only the delay time and PDP of the DG ML antimonene MOSFETs that can meet the ITRS requirements are shown. For details, please check Tables 1 and 2.

26


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TOC:

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Sub-5 nm Monolayer Arsenene and Antimonene ... - ACS Publications

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