Surface Engineering of Polycrystalline Silicon for Long-Term

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Surface Engineering of Polycrystalline Silicon for Longterm Mechanical Stress Endurance Enhancement in Flexible Low Temperature Poly-Si Thin-Film Transistors Bo-Wei Chen, Ting-Chang Chang, Yu-Ju Hung, Shin-Ping Huang, Hua-Mao Chen, Po-Yung Liao, Yu-Ho Lin, Hui-Chun Huang, Hsiao-Cheng Chiang, Chung-I Yang, Yu-Zhe Zheng, Ann-Kuo Chu, Hung-Wei Li, Chih-Hung Tsai, Hsueh-Hsing Lu, Terry Tai-Jui Wang, and Tsu-Chiang Chang ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.6b14525 • Publication Date (Web): 08 Feb 2017 Downloaded from http://pubs.acs.org on February 12, 2017

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ACS Applied Materials & Interfaces

Surface Engineering of Polycrystalline Silicon for Long-term Mechanical Stress Endurance Enhancement in Flexible Low Temperature Poly-Si Thin-Film Transistors Bo-Wei Chen†, Ting-Chang Chang*,‡,§, Yu-Ju Hung†, Shin-Ping Huang†, Hua-Mao Chen¶ , Po-Yung Liao§, Yu-Ho Lin ∥ , Hui-Chun Huang††, Hsiao-Cheng Chiang††, Chung-I Yang‡‡, Yu-Zhe Zheng†, Ann-Kuo Chu†, Hung-Wei Li§§ , Chih-Hung Tsai§§ , Hsueh-Hsing Lu§§, Terry Tai-Jui Wang¶ ¶ , Tsu-Chiang Chang¶ ¶

†

Department of Photonics, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan R. O. C. ‡ Advanced Optoelectronics Technology Center, National Cheng Kung University, Tainan 701, Taiwan R. O. C. § Department of Physics, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan R. O. C. ¶ Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan R. O. C. ∥ Department of Chemistry, National Sun Yat-Sen University, Kaohsiung, 804,

Taiwan R. O. C. †† Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan R. O. C. ‡‡ Department of Electrophysics, National Chiao Tung University, Hsinchu 300, Taiwan R. O. C. §§ New Display Process Research Division, AU Optronics Co., Ltd., 300 Taiwan ¶¶

Industrial Technology Research Institute, 195, Sec. 4, Chung Hsing Rd., Hsinchu, 31040, Taiwan

ACS Paragon Plus Environment


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ABSTRACT Surface morphology in polycrystalline silicon (poly-Si) film is an issue regardless of whether conventional excimer laser annealing (ELA) or the newer metal-induced lateral crystallization (MILC) process is used. This paper investigates the stress distribution while undergoing long-term mechanical stress and the influence of stress on electrical characteristics.

Our simulated results show that the non-uniform stress in the gate

insulator is more pronounced near the polysilicon/gate insulator edge and at the two sides of the polysilicon protrusion. This stress results in defects in the gate insulator and leads to a non-uniform degradation phenomenon, which affects both the performance and reliability in thin-film transistors (TFTs). The degree of degradation is similar regardless of bending axis (channel-length axis, channel-width axis) or bending type (compression, tension), which means that the degradation is dominated by the protrusion effects. Furthermore, by utilizing long-term electrical bias stresses after undergoing long-tern bending stress, it is apparent that the carrier injection is severe in the sub-channel region, which confirms that the influence of protrusions is crucial. To eliminate the influence of surface morphology in poly-Si, three kinds of laser energy density were used during crystallization to control the protrusion height. The device with lowest protrusions demonstrates the smallest degradation after undergoing longterm bending. KEYWORDS: Foldable electronics, LTPS TFTs, Long-term mechanical bending, Polycrystalline silicon protrusion, Surface engineering


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INTRODUCTION Recently, portable electronic products combining display panels1-5 and memory devices6-9 have become more popular for consumers. Flexible thin film transistors (TFTs) have shown much potential for applications in flexible technologies, including wearable devices, high resolution foldable displays, and as e-paper. When compared to a-Si, oxide-based, or organic TFTs, low temperature polycrystalline-silicon (LTPS) TFTs are the most promising for foldable electronics requiring small size and high speed, since they combine beneficial electrical characteristics such as good carrier mobility (40-100 cm2/Vs, superior to the 1 cm2/Vs of a-Si and 10 cm2/Vs of metal oxide material), good stability, and the possibility to exploit CMOS architectures (making it more competitive than metal oxide semiconductors) as well as virtual reality applications. When used for displays, LTPS TFTs can integrate both the pixel array and peripheral circuits. These advantages keep LTPS in the mainstream of portable device applications, as well as possessing the potential for application in state-of-the-art foldable devices. Currently, however, few studies have demonstrated the resilience necessary to achieve foldable devices, and further gains in strength must be realized for broad flexible applications. Electrical characteristics under strain in LTPS TFTs on a flexible substrate have been previously reported

10-14.

However, the specific degraded

region in TFTs and its degradation mechanisms have not yet been adequately studied. In the course of development of polycrystalline silicon, the surface morphology issues (protrusion) in poly-Si have addressed15-18; however, the process means are too complicated and the effects of the protrusions are not significant enough to adversely affect the current generation of products. With the evolution of the display industry, however, flexible panels will likely be mainstreamed in the future. Therefore, the protrusions in poly-Si will be a serious issue which requires amelioration in further



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flexible applications. In this letter, the electrical behaviors which consider the surface morphology of polycrystalline film are clarified. This letter investigates the variation of electrical characteristics after employing 5 hours of long-term bending stress. Also, mechanical stress simulation was utilized to inspect the stress distribution in the TFT. In addition, long-term high electrical field bias stresses are utilized in this report in order to examine reliability after mechanical bending. Finally, the devices with different protrusion heights have also been demonstrated to clarify the mechanism of the influence of protrusions. By manipulating the protrusion height, the endurance of mechanical stress of the devices can be enhanced. EXPERIMENT The p-channel LTPS TFTs were fabricated on a polyimide substrate with top-gate structures. First, a buffer-layer which contains Si3N4 and SiO2 was deposited on the polyimide substrate. Next, a 45 nm amorphous-Si film was deposited by plasma enhanced chemical vapor deposition (PECVD) on the buffer-oxide, followed by dehydrogenation via the furnace annealing process.

Then the channel was crystallized

by a 308 nm XeCl excimer laser, with laser energy densities of 560, 580, and 610mJ/cm2. The P- channel doping is carried out by boron after crystallization. After the active region crystallization and thermal activation, 50 nm thick SiO2 and 20nm Si3N4 layers were deposited as gate insulator (GI) by PECVD. Next, molybdenum was deposited by sputtering as a gate metal. After the gate metal definition process, source/drain regions were self-aligned by boron implantation to form the P+. Thermal activation of the dopant impurities after the source/drain region implantation was via the furnace annealing process. Next, 300nm-Si3N4 and 300nm-SiO2 were deposited by PECVD as the interlayer dielectric (ILD). Finally, the contact holes were patterned by dry etching and Ti/Al/Ti metallization was performed. The overall view of device and


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its structure is shown in Fig. 1(a) and (b). The TFTs were measured by utilizing the I– V measurements, performed using an Agilent B1500A semiconductor device analyzer. The devices were fixed on a stainless-steel plate with bent radius of 5 mm and samples were fixed by heatproof adhesive tape when performing mechanical stress, as shown in Fig. 1(c).

Fig. 1 (a) overall view and (b) cross-section of device used in this study. (c) Stainless-steel plate with bending radius of 5 mm used for long-term bending. (d) The ID-VG electrical characteristics after 5hr of channel-width axis bending.

RESULT AND DISCUSSION Figure 1(d) shows the ID–VG transfer characteristics of the flexible LTPS TFTs after 5 hours of channel width-axis compression at R = 5mm. As can be seen, the electrical characteristics degrade, through positive Vth shift, ION increase and hump generation. Previous reports have indicated the degradations are due to stress-induced GI defects and microcracks in the grain boundary10-14, 19. Instead of the influence of grain boundary cracks/defects generation, the influence of GI quality is considered to be the main factor



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for the following two reasons. First, there is no possibility the ION increases if more grain boundary cracks are generated. Second, the leakage is strongly concerned with the grain boundary traps; however, IOFF does not increase. Therefore, instability of GI quality dominates the degradation in this study. The degradation behavior is similar to our previous study19, which illustrates the p-type LTPS TFTs will bring about positive Vth shift and increase of ION after undergoing 100,000 repeated mechanical bending repetitions. The main reason was thought to be the electron trapping which occurs while measuring from positive to negative. The positive bias of sweep causes the electron to inject into the GI. The ION increase was considered to be a shortening of channel length because pronounced stresses existed in the GI near the source and drain side, which can also result in carrier trapping effects. However, no protrusion effects on mechanical stress are proposed in any previous manuscript.

A complete explanation of protrusion

effects on bending stress and sub-channel effects will be specifically offered below.


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Fig. 2 (a) TEM photo and (b) optical microscopic photo top view of the TFT used in this study. (c) Simulation of stress distribution of M-M’ in Fig. 2(b). (d) Vertical energy band diagram of A-A’, B-B’, C-C’, and D-D’.

The TEM photo in Fig. 2(a) shows the surface protrusion, marked by the dashed lines, of the poly-Si TFT used in this study. The reason for the protrusion formation is the difference in density between liquid state and solid state poly-Si; during cooling, this difference in density results in redundant volume near the grain boundary which extrudes upward during crystallization20-22. The channel width-axis bending at radii 5mm is simulated in Fig. 2(c). The cross section of Fig. 2(c) is the enlargement of MM’ in Fig. 2(b). As can been seen, the stress in GI (SiO2) is non-uniform, and is especially concentrated at the side wall region (A-A’) and the two sides of the protrusion (C-C’). Hence, the stress would likely induce a break of the S-O bond in SiO2 near A-A’ and C-C’ rather than in other regions (B-B’ and D-D’). The vertical energy band is shown to express this defect generation in Fig. 2(d).



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Fig. 3 Electrical characteristics after undergoing 5 hours of (a) width-compressive, (b) lengthcompressive, (c) width-tensile, and (d) length-tensile bending.

Figure 3 shows the electrical characteristics after undergoing 5 hours of various mechanical bending, including different bending axes (channel-length axis and channel-width axis) and different bending types (compression and tension). The degree of degradation (Vth shift, ION increase) and degradation behavior (hump generation) are similar. If the stress near the side wall dominates the degradation, mechanical bending along different axes should demonstrate clear differences in degradation. Hence, the results indicate that the non-uniform stress induced by protrusion dominates the degradation mechanism, rather than side wall stress.

Fig. 4. (a) Electron trapping process during sweeping. (b) Leakage path of the devices after 5 hours of bending. (c) The sub-channel region in TFTs.

According to this stress-induced GI defect mechanism, there is a possibility of electron trapping in the GI through thermionic-field emission when positive voltage is


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exerted on the gate electrode during +10 (V) to -10 (V) sweeping. The source of electrons in p-type silicon is the conduction band in poly-Si, electrons which originated from the valence band and moved via grain boundary trap-assisted tunneling. The excited valence band electrons will further inject into GI when positive voltage is exerted on the gate. This process is illustrated in Fig. 4(a). From the simulated results shown in Fig. 4(c), it can be deduced that the electron trapping region is that indicated in Fig. 4(c). Additional leakage paths are formed near these regions because electron trapping will absorb hole channels much easier. The leakage path will exist along both side wall regions and the two sides of the grain boundary, which is shown in Fig. 4(b). Therefore, the reason why the hump appears after undergoing 5 hours bending is the generation of these two sub-channels.

Fig. 5 (a) Electrical characteristics in saturation region before/after mechanical bending. (b) The energy band diagram in OFF state.

In Fig. 5(a), it can be seen that the leakage decreases after 5 hours of mechanical bending. In poly-Si TFTs, the leakage is generated from thermionic field emission23-24.



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Since there is pronounced stress at the GI near the S/D sides, as has been previously reported19, the electron will inject into the GI and then reduce the electric field near these regions, which lowers the probability of thermionic field emission, shown in Fig. 5(b).

Fig. 6 Long-term electrical stress of (a)-30V and (b)+30V after 5 hours bending stress. (c)(d)The vertical band diagrams for the main-channels and sub-channels under stresses of (a) and (b)

To further clarify the aforementioned theory, electrical reliability tests of +30/-30V on gate electrode for 1000sec were performed after undergoing 5 hours bending stress. Due to the non-uniform trap distribution, both of the side walls and the two sides of the protrusion possess a larger amount of traps in GI. As can be seen in Fig. 6(a), the hump disappears after 1000sec of -30V stress. Regardless of whether in the main- or subchannel, the Vth shifts negatively. This results from holes being trapped into the GI traps, which occurs after bending and neutralizes the electron trapping after bending, shown


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in Fig. 6(c). The variation in the sub-channel is more pronounced than in the mainchannel due to the difference in GI defects. Similarly, if +30V is exerted on the gate electrode for 1000sec, the hump generation and Vth shift become severe since the amount of trapped electron increases radically, which is shown in Fig. 6(b) and (d). The Vth shifts of sub-channels are both severe regardless of the electrical polarity on the gate electrode, results which further prove that the carrier trapping effects and larger amounts of traps are generated around the side wall and the two sides of the protrusion due to non-uniform stress distribution25.

Fig. 7 SEM photos of top view of poly-Si film formed with (a) 610 mJ/cm2 (c) 580 mJ/cm2 and (e) 560 mJ/cm2 laser energy density. TEM cross-section view of poly-Si with (b) 610 mJ/cm2 (d) 580 mJ/cm2 and (f) 560 mJ/cm2 laser energy density.

Different laser energy densities were utilized to control the protrusion height at the poly-Si interface. As demonstrated in Fig. 7, with the increase of laser energy density, the height of the protrusions increases. Previous reports


20-21

have identified three


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regions in the ELA crystallization process. The first is a partial-melting region (region I), which allows small grains to grow upward from the seeds at the interface, becoming large columnar grains. The second is a completely-melted region (region II) which allows these large grains to grow laterally due to a reduction in the number of nucleation sites; this means that fewer grains will nucleate from the interface. The grain sizes reach the largest grain in this region. Above the critical laser energy density value (region III), the grain size actually decreases due to the lack of any discrete “islands” (crystal seeds) of solid silicon at the interface, and the entire a-Si film is melted. The grain sizes were controlled in region II in this study. Hence, the grain sizes become larger with the increase of laser energy density. From the SEM top view photo of poly-Si film in Fig. 7 (a), the grain diameter is approximately 500 nm while the energy density is 620 mJ/cm2. From the TEM cross-section photo of poly-Si film, the height of protrusions can be observed to be about 100nm (Fig. 7(b)). The relationship between grain size and protrusion height is in accordance with a previous report22.

Fig. 8 (a) Raman spectrum and (b) its parameter table for poly-Si films formed by different laser energy densities. (c) Mobility extraction of poly-Si TFT with different laser densities.


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In addition, the Raman spectroscopy was also measured in this report. From previous studies

26-27,

the wavenumber of single crystalline silicon is about 520 (cm-1). As can

be seen from light spectrum measurements in fig. 8(a), the curve for the device formed using a laser energy density of 610mJ/cm2 poly-Si most closely approaches the wavenumber of 520 (cm-1) and has the narrowest FWHM (fig. 8(b)). This means that devices with 610 mJ/cm2 are most similar to single crystalline silicon. Hence, from fig. 8(c) the mobility of the device formed using 610 mJ/cm2 is highest among these devices.

Fig. 9 (a) Electrical characteristics and (b) extraction of compiled statistics for Vth shifts of different laser energy density devices after undergoing 5 hour mechanical bending. (c) Stress simulation of devices under mechanical bending with different protrusion heights.

Figure 9 shows the endurance of mechanical bending stress of devices with different protrusion heights. From Fig. 9(a), the lowest protrusion demonstrates the least degree of degradation. From the compiled statistics of Vth shift (Fig. 9(b)), it can be determined that devices with the lowest protrusions obtained the best endurance of long-term



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mechanical strain. Therefore, stress simulations, which are shown in Fig. 9(c), were utilized to inspect the stresses while undergoing mechanical bending. With decreasing protrusion height, the stresses near protrusions become milder, which leads to less GI degradation. Therefore, by properly manipulating the grain size and protrusion, the endurance to long-term mechanical strain instability in flexible LTPS TFTs can be effectively enhanced. CONCLUSION In this study, stress distribution under mechanical bending is simulated to explain why there are two channel effects and a positive Vth shift after undergoing long-term mechanical bending. The results indicate that the stress near the protrusions dominate the degradation mechanism. The electrical performance and reliability is affected by the localized, strong stress. By applying 1000sec electrical stresses, the two channel effects are more amplified, which further verifies that the localized and strong stress dominates the main degradation mechanism in LTPS TFTs. After clarifying that the protrusion height dominates the degree of degradation, surface morphologies were manipulated to eliminate the stress near protrusions by changing the XeCl laser energy density during crystallization. Simulation results indicated that the degree of degradation becomes milder by this lowering of protrusion heights, which is accordance with experimental results. Therefore, it can be concluded the endurance to mechanical stress can be effectively enhanced by appropriately controlling the protrusion height.


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AUTHOR INFORMATION Corresponding Author *Ting-Chang Chang: E-mail: [email protected] ORCID Ting-Chang Chang: 0000-0002-5301-6693 Notes The authors declare no competing financial interest.

ACKNOWLEDGEMENT This work was performed at National Science Council Core Facilities Laboratory for Nano-Science and Nano-Technology in Kaohsiung-Pingtung area, and assisted with New Display Process Research Division, AU Optronics Co. and Display Technology Center of Industrial Technology Research Institute. The authors acknowledge the financial support of the Ministry of Science and Technology, Taiwan (MOST) under Contract No. MOST-103-2112-M-110-011-MY3.

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Page 18 of 18

Surface Engineering of Polycrystalline Silicon for Long-Term

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