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Surface Functionalization of Black Phosphorus via Potassium towards High Performance Complementary Devices Cheng Han, Zehua Hu, Lidia C. Gomes, Yang Bao, Alexandra Carvalho, Sherman Jun Rong Tan, Bo Lei, Du Xiang, Jing Wu, Dianyu Qi, Li Wang, Fengwei Huo, Wei Huang, Kian Ping Loh, and Wei Chen Nano Lett., Just Accepted Manuscript • Publication Date (Web): 19 Jun 2017 Downloaded from http://pubs.acs.org on June 20, 2017

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Surface Functionalization of Black Phosphorus via Potassium towards High Performance Complementary Devices Cheng Han†1,2,3,4, Zehua Hu†3,4, Lidia C. Gomes4, Yang Bao2, Alexandra Carvalho4, Sherman J. R. Tan2,5, Bo Lei3,4, Du Xiang2,4, Jing Wu6, Dianyu Qi1,3,4, Li Wang7, Fengwei Huo8, Wei Huang8, Kian Ping Loh1,3,4, & Wei Chen*1,2,3,4,9

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SZU-NUS Collaborative Innovation Center for Optoelectronic Science and Technology, Shenzhen University, Shenzhen 518060, China

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Department of Chemistry, National University of Singapore, Singapore 117543, Singapore 3

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Department of Physics, National University of Singapore, Singapore 117542, Singapore

Centre for Advanced 2D Materials and Graphene Research Centre, National University of Singapore, 6 Science Drive 2, 117546, Singapore 5

NUS Graduate School for Integrative Sciences and Engineering, Centre for Life Sciences #05-01, 28 Medical Drive, 117456, Singapore 6

Institute of Materials Research and Engineering (IMRE), 2 Fusionopolis Way, Singapore 138634, Singapore

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Institute for Advanced Study and Department of Physics, Nanchang University, 999 Xue Fu Da Dao, Nanchang 330031, China

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Key Laboratory of Flexible Electronics (KLOFE) & Institute of Advanced Materials (IAM), Jiangsu National Synergetic Innovation Center for Advanced Materials (SICAM), Nanjing

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ACS Paragon Plus Environment

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Tech University (Nanjing Tech), 30 South Puzhu Road, Nanjing 211816, P.R. China 9

National University of Singapore (Suzhou) Research Institute, 377 Lin Quan Street, Suzhou Industrial Park, Jiang Su 215123, China

†

These authors contributed equally to this work.

*

Author to whom correspondence should be addressed. Electronic mail: [email protected]

(W. Chen)

Abstract Two-dimensional black phosphorus configured field-effect transistor devices generally show a hole-dominated ambipolar transport characteristic, thereby limiting its applications in complementary electronics. Herein, we demonstrate an effective surface functionalization scheme on few-layer black phosphorus, through in situ surface modification with potassium, with a view towards high performance complementary device applications. Potassium induces a giant electron doping effect on black phosphorus along with a clear bandgap reduction, which is further corroborated by in situ photoelectron spectroscopy characterizations. The electron mobility of black phosphorus is significantly enhanced to 262 (377) cm2V-1s-1 by over one order of magnitude after potassium modification for two-terminal (four-terminal) measurements. Using lithography technique, a spatially controlled potassium doping technique is developed to establish high performance complementary devices on a single black phosphorus nanosheet, e. g. the p-n homojunction-based diode achieves a

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near-unity ideality factor of 1.007 with an on/off ratio of ~104. Our findings coupled with the tunable nature of in situ modification scheme enable black phosphorus as a promising candidate for further complementary electronics.

Keywords: black phosphorus, potassium, giant electron doping, electron mobility enhancement, complementary devices

Introduction The use of two-dimensional (2D) layered materials as the building blocks of the next generation nanoelectronic devices, represented by graphene1, 2 and transition metal dichalcogenides (TMDs)3, provides the possibilities to extend the scaling limits in conventional silicon (Si)-based complementary metal oxide semiconductor (CMOS) devices. Despite the extremely high charge carrier mobility (> 100,000 cm2V-1s-1)4 and a wealth of fantastic fundamental properties5, graphene lacks a finite bandgap, thus seriously limiting its applications in logic electronics that require a large current on/off ratio. On the other hand, semiconducting TMD materials possess a sizeable and thickness-dependent bandgap, and however they suffer from the low charge carrier mobility3. The emergence of 2D layered black phosphorus (BP)6-8 fills the gap between graphene and TMDs owing to its high carrier mobility (up to ~6000 cm2V-1s-1)9 and moderate direct bandgap (tunable from ~0.3 eV for bulk to ~2 eV for monolayer)10-12. Few-layer black phosphorus flake can be isolated via mechanical exfoliation from

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bulk layered crystal, where each phosphorus atom is covalently bonded to three neighboring atoms, forming a puckered orthorhombic structure in a unit cell13-15. Such crystalline structure also causes highly anisotropic electronic and optoelectronic characteristics in exfoliated BP flakes16-18. Unlike the direct-to-indirect bandgap transition in most cases of TMDs3, BP has a direct bandgap for all number layers10-12, possessing great potentials for BP-based optoelectronic applications18-20. This intrinsic sizeable bandgap enables ultrathin BP to be configured as field-effect transistor devices with a high current on/off ratio of 104-105.6 Arising from the oxygen-induced electron trapping on BP21 as well as the formed Schottky barrier at metal/BP interfaces22-24, BP-based FETs generally shows a hole-dominated ambipolar transport characteristic, where the hole mobility and on-current are orders of magnitudes higher than the electron side, thereby seriously restricting its applications in complementary electronics. In order to achieve BP-based complementary devices with high performance, it is of great significance to largely improve the electron mobility in BP devices and develop methods to dope BP in a controlled and non-destructive manner. In conventional semiconductors, substitutional doping by introducing alien atoms into crystal lattice is commonly employed to realize n- or p-type behaviors. However, this is seldom used in 2D material systems due to the introduction of significant defects via this doping process25, 26. The charge carrier concentration and type of 2D materials can be tuned by applying an external electrostatic field27-31, but the efficiency is limited for the lack of good interfaces between dielectrics and 2D materials in the sophisticated device structures. Attributed to the atomically thin nature of 2D

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materials, chemical doping based on modifying the surface with a specific adlayer provides a strong and non-volatile doping capability on 2D materials with the ease of device fabrication. Since the first study of chemical doping on black phosphorus FETs via metal oxides (Cs2CO3 and MoO3)32, several organic and inorganic species have been utilized on BP surface to either modulate its transport properties or protect BP from degradation in air ambient. Covalent33 and non-covalent functionalization34 by coating polymer layers is demonstrated to effectively enhance the stability of BP against oxidization. Very recently, metal adatoms35, 36 and cross-linked Poly(methyl methacrylate) (PMMA)37 were spatially coated on a single BP flake to achieve complementary devices, such as logic invertor and p-n homojunction-based diode. Nevertheless, these electron donors did not induce significant n-doping effect on BP, resulting in limited device performance for the lateral homojunction-based devices. Alkali metal potassium (K), one of strongest electron donors, has been used as surface dopant to dramatically modify the electronic properties of graphene38 and TMDs39. For the case of BP, J. Kim et al. recently report a widely tunable bandgap of BP with potassium doping measured by angle-resolved photoelectron spectroscopy (ARPES) due to the giant Stark effect40. However, to date, a detailed experimental investigation of how potassium impacts on the device performance of BP-based FETs is still absent. Considering the super high reactivity of K in air, it is necessary to undertake in situ characterizations on K-modified BP devices. Here, we report a giant electron doping of few-layer BP from FET perspective via the in situ surface functionalization with potassium. K modification is found to

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remarkably enhance the electron transport of BP, and in particular the electron mobility is increased to 262 (377) cm2V-1s-1 by over one order for two-terminal (four-terminal) measurements after a 1.6 nm-thick K film is deposited. In situ photoelectron spectroscopy (PES) characterizations reveal the significant interfacial charge transfer between BP and K doping layer. In addition, a clear bandgap reduction of BP induced by a vertical electrical field from K dopants is extracted from FET measurements, and further corroborated by the in situ PES/ARPES results. By spatially masking the BP channel, high performance complimentary devices are achieved in a single BP flake after K doping, demonstrating an ideal p-n homonjunction-based diode with a near-unity ideality factor of 1.007 and high current on/off of ~104. The realization of both n- and p-type conduction in a BP channel gives the logic inverter device as well.

Results and discussions Ultrathin BP flakes were isolated on a heavily p-doped silicon substrate with 300 nm oxides using standard micromechanical exfoliation, and subsequently configured as two-terminal FET devices for electrical measurements (see methods). Figure 1a displays a typical atomic force microscopy (AFM) image of an as-fabricated BP device. The line profile indicates a 6.5 nm-thick BP flake in the FET device, corresponding to ~12 atomic layers considering interlayer distance of 0.53 nm. Raman spectrum of exfoliated few-layer BP (Fig. 1b) exhibits three characteristic peaks nearly located at 364, 438 and 465 cm-1, corresponding to three different

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vibration modes, labeled as Ag1, B2g and Ag2, respectively. All the electrical measurements of the as-made BP devices were conducted in a high vacuum condition (~10-8 mbar) due to the environmental instability of BP41, 42. Figure 1c shows the typical transfer transport characteristic (Isd-Vg) of the fabricated BP FETs at Vsd = 0.1. Applying the gate voltage ranging from -80 V to 50 V, the source-drain current increased from OFF to ON state along both negative and positive sweeping direction (inset of Fig. 1c), corresponding to the hole and electron transport, respectively. Moreover, the current for negative Vg sweeping increased much faster than the positive side, indicating an obvious hole-dominated ambipolar transport characteristic. The inset logarithmic plot presents a current on/off ratio of ~104, in good agreement with previous reports6. Extrapolating the current onset in the linear region of both hole and electron side, the threshold voltage Vth was determined to be ~-38 V for holes and ~23 V for electrons. On the basis of Vth, The carrier concentration induced by a specific gate voltage Vg can be estimated by the equation: n = −Ci (Vg − Vth ) e , where Ci denotes the capacitance per unit area between BP and

back gate given by Ci = ε 0ε r d ( ε r and d are the dielectric constant and thickness of SiO2, respectively). For example, the electron concentration at Vg = 25 V was derived to be 1.3 × 1011 cm-2. Similarly, extracted from the linear regime of transfer curve, the field-effect mobility of BP was evaluated in two-terminal FET configurations by the formula below:

µ=

L dI sd WCV i sd dVg

where dIsd ⁄ dVg represents the slope of the linear region in transfer plot, and L, W are 7


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the length and width of conduction channel, respectively. For the device in Fig. 1c, the hole and electron mobility were estimated to be 716 cm2V-1s-1 and 18 cm2V-1s-1, respectively. The source-drain current versus source-drain voltage characteristics of the same device are shown in Fig. 1d. Excellent linearity with Vsd ranging from -0.1 V to 0.1 V under different Vg reveals the ohmic contacts between metal electrodes and BP flake.

In order to investigate the surface functionalization of K on tuning the electronic properties of few-layer BP, K was in situ evaporated onto BP FETs in high vacuum for electrical characterizations (details see methods). Figure 2a demonstrates the typical transfer characteristic evolution in logarithmic scale of BP devices with respect to K thickness. It is worth noting that the thickness shown in this work is nominal thickness calibrated by quartz crystal microbalance (QCM). The initial transfer curve of the pristine BP presents a current minimum nearly located at zero gate voltage, indicating a neutral conduction behavior without electrostatic field. With increasing K thickness, the current minimum dramatically shifted towards negative gate voltages, in particular by over 60 V after coating 0.8 nm K, and rapidly exceeds the safe gate voltage compliance (-80V) with further K deposition. This suggests a giant electron doping effect on K-modified BP device, originating from the significant interfacial electron transfer from K dopants to the underlying BP flake. More importantly, the on-current of electron side was increased by over one order of magnitude after 1.6 nm K deposition, revealing a remarkably enhanced electron

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transport in K-doped BP. As a result, the hole-dominated transfer characteristic of the pristine BP progressively evolved to electron-dominated behavior, and eventually reached the pure n-type transport in the limited Vg range, with the gradual deposition of K, as shown in Fig. 2b. The electron concentration (Vg = 25 V) and mobility of BP were calculated from the method aforementioned and plotted as a function of K thickness in Fig. 2c. The estimated electron concentration at 25 V Vg sharply increased from 1.3 × 1011 cm-2 to 1.0 × 1012 cm-2 after 0.2 nm K decoration, and almost saturated at higher coverage. Intriguingly, K-functionalized BP shows over one order of magnitude enhancement of electron mobility from 18 cm2V-1s-1 for the pristine BP to 262 cm2V-1s-1 for 1.6 nm K-decorated device. Although the field-effect mobility extracted from our two-terminal devices is an underestimate of the intrinsic mobility, it still approaches the record values of electron mobility from four-terminal measurements at room temperature in the literature, such as 275 cm2V-1s-1 for Al-contacted BP FETs24 and 380 cm2V-1s-1 for Cu-doped BP on boron nitride (BN)35. To better compare the electron mobility of K-modified BP with literatures, we further fabricated the BP FETs in four-terminal configurations for in situ electrical measurements, as shown in supporting information Fig. S2. The electron mobility of BP extracted from four-terminal measurements significantly increased from 61 cm2V-1s-1 to 377 cm2V-1s-1 after 1.6 nm K deposition, thus approaching to the record electron mobility value of Cu-doped BP on BN (380 cm2V-1s-1). Both two- and four-terminal electron mobility of K-decorated BP were compared with previous works in supporting information Table S1. Through the in situ surface modification of

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K, we obtained the electron mobility that almost reached the highest record of Cu-doped BP on BN at room temperature, even if the BP FETs were simply established on SiO2/Si substrate for the most commonly used back-gated configurations. Our previous work21 shows that oxygen molecules in air can either physi- or chemi-sorbed on the BP surface, thus introducing high concentration of electron trapping sites that cannot be fully released even under high vacuum. We propose that the n-type doping via K can significantly increase the electron concentration in BP to fill up these trapping sites as well as to effectively screen the trapped charges, thereby greatly enhancing the electron mobility of BP. In addition to the greatly improved electron transport, K-functionalized BP also demonstrates an obvious bandgap reduction obtained from the transfer measurements in Fig. 2a. Evaluating the minimum current of the BP device, we notice that the off-state gradually increased from 2.0 × 10-9 A to 1.9 × 10-8 A after the deposition of 0.8 nm K as plotted in inset of Fig. 2d, and further kept this trend of evolution with higher K thickness. Following the previously reported methodology in bilayer MoS2 FETs43, the threshold voltages in the ambipolar transfer curves were utilized to extract the size of bandgap. At the threshold voltage of n-branch (labeled as Vn-th), the Fermi level at the source is aligned to the conduction band of BP; while the Fermi level at the drain moves to align with the valence band as Vg reaches the threshold voltage of p-branch (labeled as Vp-th). Thus, the bandgap of BP can be simply estimated using the formula below: V − Vp-th   Eg = e  Vsd + n-th  β   10


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where β is the band movement factor: β = 1 + CT COX . CT and COX are the interface trap capacitance and oxide capacitance, respectively. Alternatively, close to the device off-state, the subthreshold swing (SS) defined as dVg d ( log I sd ) equals 60 × β mV/decade, resulting in the extraction of β factor from experimentally measured SS in individual transfer plot. As shown in Fig. 2d, the estimated bandgap of BP apparently decreased from 0.45 eV to 0.35 eV after 0.4 nm K modification. This mainly results from the Stark effect induced by a giant vertical electric field via K doping, as reported in the previous ARPES work40. Further deposition of K shifted Vp-th beyond the measurable Vg range, making it difficult to estimate the bandgap of BP at higher doping level. However, the tendency for the reduction of BP bandgap with increasing K coverage is clear and continuous.

In situ ultraviolet photoelectron spectroscopy (UPS) and X-ray photoelectron spectroscopy (XPS) characterizations were further implemented on K-modified bulk BP to elucidate the underlying interfacial charge transfer mechanism between K and BP. Figure 3a shows the evolution of UPS spectra at low kinetic energy during the deposition of K on BP. By linearly extrapolating the low kinetic energy onset (secondary electron cutoff), the vacuum level of K-coated BP was measured to extract the work function. After the deposition of 3.2 nm K, the work function largely decreased from 4.16 eV (clean BP) to 2.78 eV, or a downshift of vacuum level by 1.38 eV, originating from the substantial interfacial electron transfer from K to BP. This significant charge transfer was further verified by the XPS core level spectra of P 2p

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as shown in Fig. 2b. Pristine BP exhibits a single P 2p peak with the spin-orbit split located at 129.45 eV. Upon the K deposition, the P 2p peak quickly shifted to the higher binding energy, markedly by 0.55 eV to 130 eV after 3.2 nm K decoration. This demonstrates a remarkable downward band bending that suggests the Fermi level of BP moving towards or even above its conduction band minimum (CBM), resulting from the increase of electron concentration in K-doped BP. Similar to the previously reported surface transfer doping of 2D materials44-46, the large work function difference between K and BP results in the significant charge transfer at K/BP interface that leads to the accumulation of excess delocalized electrons in the BP layer, thereby resulting in a significant downward shift of the entire band structure of BP with reference to the Fermi level. The observed vacuum level shift comprises the downward band bending in BP and the interface dipole formed at K/BP interface. This gives rising to a clear interface dipole extracted from the difference between vacuum level shift and band bending as illustrated in Fig. 3c. On the other hand, the UPS spectra of the valence band in K-modified BP were also measured at low binding energy as shown in supporting information Fig. S5. With the deposition of K, the CBM of BP originally located above the Fermi level was dragged downward below the Fermi level, as clarified by the corresponding ARPES spectra measured at room temperature. This allows the position of the CBM to be pinpointed in the UPS spectra, thereby leading to the direct observation of bandgap. Hence, a decrease of BP bandgap was identified and subsequently plotted versus K thickness in supporting information Fig. S6. In addition, first-principle calculations were also performed on

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the K-functionalized BP system to further support the significant n-type doping effect of K on BP, as shown by the supporting information Fig. S8.

On the basis of the giant n-doping nature of K, a spatially controlled K doping scheme was developed to fabricate p-n diode devices on a single BP flake. Prior to the K doping, half of the BP channel was masked by a photoresist layer using a second e-beam lithography (EBL) process (see methods), while leaving the other half exposed to surface dopants. The schematic illustration and optical microscopy image of the device structure are presented in Fig. 4a. In order to generate a steep p-n homojunction between the capped and uncapped BP, 1.6 nm K was deposited onto the half-protected device for in situ electrical characterizations. Figure 4b and c exhibit the typical rectification characteristics (Isd-Vsd) of BP diodes under gate voltages ranging from -10 V to -50 V with a step of 5 V in logarithmic and linear scale, respectively. It was observed that the current at negative bias rapidly dropped with increasing Vg and then reached the minimum at -30 Vg; while the positive bias regime shows a much slower current decrease. This yields the remarkable increase of rectification ratio (defined by the ratio of the forward current to the reverse current at the same bias magnitude of 1V) as Vg increased, which further achieves a maximum ratio of ~104 at Vg = -30 V, as plotted in the inset of Fig. 2c. Such gate-dependent rectification behavior reveals the tunable potential barrier built up cross the capped/uncapped BP boundary by the modulation of external electrostatic field. Similar to the previously reported BP diodes via surface doping36, 37, the homojuntion

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on the half-doped BP device experiences the transition from p-p junction, across p-n junction, and finally to n-n junction along with the positive Vg sweeping, as discussed in details in supporting information Fig. S9. By selecting the gate voltage of -30 V, the I-V output of the BP diode with optimized device performance is shown in Fig. 4a. The reverse current is found to be < 3 nA at Vsd = -1 V, representing the promising characteristics for low-power electronics. At forward bias, the BP diode was promptly switched on and obtains the on-current as high as 15 µA under 1 V Vsd, a hallmark of diode behavior. Furthermore, the logarithmic plot demonstrates an almost linear regime of current onset with the positive bias even extending to 0.2 V, making the diode characteristics fit for the Shockley model. Regardless of the parasitic resistance in the junction, the relationship between Isd and Vsd across an ideal p-n diode can be expressed as the Schokley equation:

  eV   I sd = IS exp  sd  − 1  η kBT    where IS is the saturation current, and ƞ denotes the ideality factor. By linear fitting of the current onset in logarithmic scale, the ideality factor of the BP diode was determined to be 1.007. This near-unity ideality factor combined with the rectification ratio of ~104 suggests a near-ideal p-n diode established on the half-doped BP flake, arising from the giant built-in potentials across the p-n homojunction.

Using the similar method to fabricate the BP diode, the logic inverter device was also constructed on an individual BP flake via the integration of a K-doped BP FET with a 14


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pristine BP FET. The BP flake was transferred onto a 30 nm-thick BN nanosheet that serves as the dielectric layer with the bottom gate of graphene. Figure 5a schematically shows the device structure with two different BP channels in series. One BP channel was capped by a photoresist mask, labeled as P-FET; while N-FET was realized in the uncapped channel by K doping. The input voltage VIN was applied to the back gate, and the three planar contacts sequentially served as ground GND, output VOUT, and power supply VDD, respectively, as exhibited in Fig. 5b. The transfer characteristics of two parallel FETs on a single BP flake were illustrated in Fig. 5c. Prior to the K deposition, the uncapped FET shows a similar transport behavior compared to the capped one, owing to the use of identical BP flake in the two FETs. After the deposition of 0.2 nm K, the transfer output of uncapped BP channel shifted towards the negative Vg, accompanied by a highly improved electron transport. This leads to intersection of the n-branch of uncapped channel with the p-branch of capped channel in the pink-shaded region, where the conductance ratio between two channels were suddenly reversed, thus producing an inverted output signal VOUT as increasing input voltage VIN. Figure 5d exhibits the output characteristic and obtained gain of the BP inverter as a function of VIN at VDD = 5 V. In the first regime, with VIN between -4 to 0 V, the output voltage was in the “high” state that approaches the supply voltage 5V. When the input voltage increased from 0 to 4 V, the output voltage shows a transition from “high” to “low” state (~0 V) with a steep slope. The gain of the inverter, defined by the slope of output characteristics ( G = dVOUT dVIN ), follows a Dirac-δ function like behavior with a highest value of ~5 occurring at the transection

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between the subthreshold regions of P-FET and N-FET. As the VIN further increased, the VOUT stayed steadily at the “low” state with near zero value. An ideal logic inverter has an infinite gain that results from an immediate transition from “high” to “low” state. The limited gain of our BP inverter is possibly attributed to the poor BP/BN or BN/graphene interfaces (e. g. interfacial bubbles) induced by the sensitive transfer process. We also fabricated the BP invertor device on 90 nm and 300 nm SiO2/Si substrate to clarify the effect of gate dielectric on limiting the inverter performance. As shown in supporting information Fig. S10 and S11, the inverter on 90 nm and 300 nm SiO2/Si substrate demonstrates a lower gain of ~2 and ~0.8, respectively, compared to that on BN. Thus, using a thinner or high-k dielectric can improve the modulation efficiency of back gate and thereby enhance the gain of the BP inverter.

Conclusion In summary, we clearly demonstrate a giant electron doping effect on few-layer BP FETs through in situ functionalization of potassium. K can significantly improve the electron transport of BP, resulting in the remarkable increase of electron mobility up to 262 (377) cm2V-1s-1 for two-terminal (four-terminal) measurements after the deposition of 1.6 nm K. In situ UPS and XPS measurements confirm the interfacial charge transfer occurring at K/BP interface. The giant vertical electrical field induced by K dopants apparently decreased the bandgap of BP, as extracted by FET measurements. Complementary devices were subsequently established on a single BP

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flake using a spatially controlled K doping scheme, realizing a near-ideal p-n diode with an ideality factor of 1.007 and rectification ratio of ~104 and a logic inverter with a highest gain of ~5. Our results promise a facile approach to dramatically electron dope few-layer BP, and thus effectively tailor its electron properties for the realization of high performance BP-based complementary electronic devices.

Methods Sample preparation and device fabrication Few-layer BP flakes were mechanically exfoliated from bulk BP crystals (Smart Elements) using a scotch tape, and subsequently transferred onto a degenerately p-type doped silicon substrate with 90 or 300 nm SiO2 for the FET fabrication. For the preparation of stacking structures, graphene sheets were initially exfoliated on a SiO2/Si substrate. BN and BP flakes were then exfoliated on a viscoelastic stamp (polydimethyl siloxane (PDMS)) and subsequently transferred to the desired substrate via the standard dry transfer method. After locating the exfoliated BP flake by a high-resolution

optical

microscope

(Nikon

Eclipse

LV100D),

polymethyl

methacrylate (PMMA) photoresist was immediately spin coated on the substrate to protect BP from degradation in air. The conventional e-beam lithography (EBL) technique was subsequently employed to pattern the source and drain electrodes precisely on the BP flake, followed by the thermal evaporation of 5 nm Ti and 60 nm Au as metal contacts. After liftoff in acetone, the as-fabricated devices were wire-bonded onto a lead chip carrier for the FET measurements.

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To build up the partially-masked BP devices, a second EBL process was applied on the two-terminal BP channel, followed by the liftoff step. PMMA photoresist also served as the capping layer to prevent half of the BP channel from K doping. The open window was carefully defined at the desired position of BP channel following a precise alignment procedure. The half-capped BP devices were also wire-bonded to a chip carrier before loading to the vacuum chamber.

In situ device characterization All the as-made BP devices were loaded into a custom-built high vacuum system (~10-8 mbar) for the in situ electrical characterizations. The device measurements were carried out using an Agilent 2912A source measure unit at room temperature. Potassium sources were in situ evaporated from an alkali metal dispenser (SAES Getter) onto the devices under high vacuum conditions. The nominal thickness of K layers was calibrated by a quartz crystal microbalance (QCM) exactly located in front of the sample stage.

In situ PES characterization In situ UPS and XPS measurements on K-modified bulk BP were conducted in a home-built ultrahigh vacuum chamber (~10-10 mbar) with He I (21.2 eV) and Mg Ka (1,253.6 eV) as excitation sources, respectively. By applying a sample bias of -5V, the sample work function was determined by the secondary electron cutoff at the low kinetic energy region. The Fermi level was calibrated to a sputter-cleaned Au-foil and

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the experiments were performed at room temperature. The nominal thickness of in situ deposited K layers was estimated by measuring the attenuation of P 2p peak before and after K deposition and further calibrated by QCM. In situ ARPES measurements were carried out in a ultrahigh vacuum system with a differentially-pumped UVS300 helium discharge lamp (SPECS GmbH) as the light source, which provides monochromatized photon beam with the energy of 21.2 eV (He I), through a toroidal mirror monochromator (SPECS GmbH). Detection was done by a PHOIBOS 150 hemispherical energy analyzer (SPECS, GmbH) equipped with a 3D delay line detector (3D-DLD, SPECS GmbH). The Fermi level was calibrated to Au and the experiments were performed in a chamber of base pressure better than 8 × 10-10 mbar.

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ASSOCIATED CONTENT Supporting information The Supporting Information is available free of charge on the ACS Publications website at DOI: Transfer characteristics of K-modified BP FET via backward gate sweeping, four-terminal

characterizations

on

K-modified

BP FET

devices,

transport

characteristics of K-modified BP FETs with different flake thickness, UPS valence band, ARPES and XPS K 2p core level spectra of K-modified bulk BP, STM

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investigations on K-deposited BP surface, DFT calculations on K-deposited BP, operation mechanism of gate-tunable BP diode, BP-based logic inverter on 90 nm and 300 nm SiO2/Si substrate.

AUTHOR INFORMATION Corresponding Author *E-mail: [email protected] Author contributions C. H. and Z. H. contributed equally to this paper. W. C. supervised the experiments. C. H., Z. H. and Y. B. performed the experiments. L. C. G. and A. C. carried out the theoretical calculations. C. H. and W. C. wrote the main manuscript text. C. H., Z. H., S. J. R. T. and L. C. G. prepared Figures 1-5 and Figures S1-11. All authors reviewed the manuscript. Notes The authors declare no competing financial interest.

Acknowledgements Authors acknowledge the financial support from China NSFC program (21573156), Singapore MOE Grant R143-000-652-112, National Key Basic Research Program of China (2015CB856505), Natural Science Foundation of SZU (grant No. 2017029), Singapore NRF Medium Sized Centre Programme and CRP grant R144-000-295-281, and Singapore NRF-CRP grant R143-001-608-281, and the technical support from

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Centre for Advanced 2D Materials and Graphene Research Centre for the device fabrication. This work is also partially supported by the Science and Technology Planning Project of Guangdong Province (grant No. 2016B050501005) and the Educational Commission of Guangdong Province (grant No. 2016KCXTD006).

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Figures

Figure 1. Few-layer BP back-gated FET and device characterization. (a) AFM image of an as-fabricated BP FET in two-terminal configurations. The line profile suggests a multilayer BP flake of ~6.5 nm (~12 layers). (b) Raman spectrum of the exfoliated BP flake on the 300 nm SiO2/Si substrate. (c) Transfer characteristic (Isd-Vg) of a BP device at Vsd = 0.1 V. Inset: logarithmic plot of the transfer curve. The transfer plot demonstrates a hole-dominated ambipolar transport characteristic with the hole and electron mobility of 716.0 cm2V-1s-1 and 18 cm2V-1s-1, respectively. (d) Isd-Vsd characteristics (Vsd from -0.1 V to 0.1 V) of the same device with increasing gate voltages from 0 V to -80 V.

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Figure 2. Transport characteristics of K-modified BP FET devices. (a) Transfer characteristics (Vg from -80 V to 50 V) evolution of a BP FET measured at Vsd = 0.1 V in logarithmic scale with increasing K thickness. (b) Linear plot of the same transfer characteristics. Inset: schematic illustration of BP devices during the deposition of K. (c) The plot of extracted electron concentration at Vg = 25 V and mobility as a function of K thickness. The electron mobility of the BP device was significantly enhanced by one order of magnitude to 262 cm2V-1s-1 after 1.6 nm K decoration. (d) Estimated bandgap of the few-layer BP with respect to K thickness. The inset shows the current minimum of the transfer curves as a function of K thickness.

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Figure 3. UPS and XPS characterizations on K-modified bulk BP. (a) UPS spectra evolution at low kinetic energy region (secondary electron cutoff) during the deposition of K. (b) XPS P 2p core level spectra of BP as a function of K thickness. (c) The shift of sample work function and P 2p core level versus K thickness.

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Figure 4. BP-based p-n homojuction diode. (a) Schematic illustration and optical image of the as-fabricated p-n diode on a single BP flake. (b) The Isd-Vsd characteristics (Vsd from -1 V to 1 V) of a 1.6 nm K-coated BP diode in logarithmic scale upon gate voltages ranging from -50 V to -10 V with a step of 5V. A gate-tunable rectification behavior is identified, corresponding to a diode performance. (c) The linear plot of the rectification characteristics. Inset: the plot of calculated rectification ratio with respect to K thickness. (d) The rectification characteristic of the BP diode at an optimized gate voltage of -30 V in both logarithmic and linear scale. The linear regime in the logarithmic plot indicates a near-unity ideality factor of 1.007, revealing a near-ideal diode performance.

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Figure 5. BP-based logic inverter. (a) Schematic of the device structure for BP-based logic inverters on an individual BP flake. (b) The optical image of an as-made BP inverter on BN (graphene as back gate) with three planar electrodes that serve as VDD, VOUT and ground, respectively. (c) The transfer characteristics of capped and uncapped BP channels in the BP inverter. P- and N-FET were realized in the capped BP and uncapped BP with 0.2 nm K, respectively, facilitating the presence of inverted output in the pink-shaded region. (d) The output characteristic and extracted gain of the BP inverter as a function of input voltage at VDD = 5 V. A highest gain of ~5 was obtained near 2 V VIN.

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