Symmetric Ambipolar Thin-film Transistors and High-gain CMOS-like

Subscriber access provided by Nottingham Trent University

Functional Inorganic Materials and Devices

Symmetric Ambipolar Thin-film Transistors and High-gain CMOSlike Inverters using Environmentally Friendly Copper Nitride Kosuke Matsuzaki, Takayoshi Katase, Toshio Kamiya, and Hideo Hosono ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.9b12068 • Publication Date (Web): 28 Aug 2019 Downloaded from pubs.acs.org on August 28, 2019

Just Accepted “Just Accepted” manuscripts have been peer-reviewed and accepted for publication. They are posted online prior to technical editing, formatting for publication and author proofing. The American Chemical Society provides “Just Accepted” as a service to the research community to expedite the dissemination of scientific material as soon as possible after acceptance. “Just Accepted” manuscripts appear in full in PDF format accompanied by an HTML abstract. “Just Accepted” manuscripts have been fully peer reviewed, but should not be considered the official version of record. They are citable by the Digital Object Identifier (DOI®). “Just Accepted” is an optional service offered to authors. Therefore, the “Just Accepted” Web site may not include all articles that will be published in the journal. After a manuscript is technically edited and formatted, it will be removed from the “Just Accepted” Web site and published as an ASAP article. Note that technical editing may introduce minor changes to the manuscript text and/or graphics which could affect content, and all legal disclaimers and ethical guidelines that apply to the journal pertain. ACS cannot be held responsible for errors or consequences arising from the use of information contained in these “Just Accepted” manuscripts.

is published by the American Chemical Society. 1155 Sixteenth Street N.W., Washington, DC 20036 Published by American Chemical Society. Copyright © American Chemical Society. However, no copyright claim is made to original U.S. Government works, or works produced by employees of any Commonwealth realm Crown government in the course of their duties.

Page 1 of 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Applied Materials & Interfaces

Symmetric Ambipolar Thin-film Transistors and High-gain CMOS-like Inverters using Environmentally Friendly Copper Nitride Kosuke Matsuzaki,a,* Takayoshi Katase,b,c Toshio Kamiya,a,b and Hideo Hosonoa,b,*

aMaterials

Research Center for Element Strategy, Tokyo Institute of Technology, 4259

Nagatsuta-cho, Midori-ku, Yokohama 226-8503, Japan bLaboratory

for Materials and Structures, Institute of Innovative Research, Tokyo Institute of

Technology, 4259 Nagatsuta-cho, Midori-ku, Yokohama 226-8503, Japan cPRESTO,

Japan Science and Technology Agency, 7 Goban-cho, Chiyoda, Tokyo, 102-0076,

Japan

KEYWORDS ambipolar transistors, ionic semiconductors, copper nitride, electric double-layer transistor, CMOS-like inverters

ACS Paragon Plus Environment

1

ACS Applied Materials & Interfaces 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 2 of 23

ABSTRACT Oxide semiconductor thin-film transistors (TFTs) are currently used as the fundamental building blocks in commercial flat-panel displays because of the excellent performance of nchannel TFTs. However, except for a few materials, their p-channel performances have not been acceptable. Although some p-type oxide semiconductors exhibit superior hole transport properties, their TFT performances are greatly deteriorated, which is a major obstacle for the development of complementary metal oxide semiconductor (CMOS) circuits. Herein, an ionic nitride semiconductor, copper nitride (Cu3N), composed of environmentally benign elements is shown to exhibit highly symmetric hole and electron transport, indicating its suitability for application in CMOS circuits. We performed two step investigation. The first step was to examine the ultimate potential of Cu3N using an electric-double-layer transistor structure with epitaxial Cu3N channels measured at 220 K, which demonstrated ambipolar operation with hole and electron mobilities of ~5 and ~10 cm2(Vs)−1, respectively, and a high on/off ratio of ~105 is demonstrated. The second step is to demonstrate feasibility for TFT circuits with polycrystalline channel on non-single-crystal (SiO2/Si) substrates. CMOS-like inverters composed of two polycrystalline Cu3N ambipolar TFTs on a SiO2/Si substrate exhibited a high voltage gain of ~100.


2

Page 3 of 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


INTRODUCTION As demonstrated by the success of amorphous oxide semiconductor thin-film transistors (TFTs) in flat-panel displays,1-3 ionic semiconductors offer great advantages over conventional covalent semiconductors such as silicon for large-area electronics on non-single-crystalline substrates. That is, ionic semiconductors exhibit excellent performances as n-type devices, even when fabricated at low temperatures on glass/plastics because they have high electron mobilities and low-density electron traps as will be explained in the next paragraph. However, this strong ionicity generally causes serious asymmetry between n- and p-type carrier transport and device performances; i.e., although ionic semiconductors exhibit high electron mobility and produce good n-channel TFTs, their hole mobilities are low and, except for a few materials, they do not exhibit p-type conduction. P-channel TFT performances are far from satisfactory even using these exceptional p-type oxide semiconductors. Currently, complementary metal–oxide–semiconductor (CMOS) circuits are employed in Si ultra-largescale integrated circuits to ultimately minimize the leakage current and power consumption.4 For CMOS circuits, semiconductor layers with well-balanced electron and hole transport properties (p/n symmetry) are favored from the viewpoint of circuit design and integration as has been demonstrated for hydrogenated a-Si, polycrystalline Si and carbon nanotube on glass substrates and flexible plastics. The development of such CMOS-like circuits using ionic semiconductors with bipolar conduction is also expected owing to the capability of lowtemperature formation and its potential for further high device performance and stability; however, their strong p/n asymmetry presents a major obstacle. Thus, an ionic semiconductor


3


Page 4 of 23

with symmetric p/n properties is desired for the development of flexible CMOS circuits. However, most ionic compounds such as fluorides, oxides, and nitrides tend to exhibit n-type unipolar transport,2,

3, 5

and therefore, high-performance p-type semiconductors with

acceptably high hole mobility have been limited.6-8 The above advantages of ionic semiconductors for n-type devices originate from their defect-tolerant chemical bonding; i.e., their conduction band minimum (CBM) consists mainly of the largely spread unoccupied s orbitals of post-transition metal cations, and the formation of an anion vacancy tends to form the corresponding defect states at a very deep level above the valence band maximum (VBM) (near-VBM states),2, 9, 10 as observed in amorphous In–Ga– Zn–O (a-IGZO)11. However, such near-VBM states work as hole traps. These hole traps are present in native p-type Cu2O and originate from localized VBM states formed by admixed O 2p and Cu 3d orbitals and from the variable ionic valences of transition metals, leading to deterioration of p-channel TFT performance.12 Thus, p-channel13, 14 and ambipolar TFT15, 16 operation have only been reported for narrow-gap p-type SnO (indirect gap = 0.7 eV) in various ionic semiconductors. Herein, we propose copper nitride (Cu3N) composed of earth-abundant and environmentally benign constituent elements as a new platform for both p- and n-channel TFT applications including CMOS circuits. Cu3N has the anti-ReO3 cubic structure with a relatively large open space at the center, as illustrated in Figure 1a. Undoped Cu3N is an n-type semiconductor with low electron density and an indirect bandgap of ~1.0 eV.17 Bipolar control


4

Page 5 of 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


is attained through interstitial doping at the center vacancy site surrounded by eight Cu ions, i.e., doping of electropositive elements (Li18,

19

and Cu17,

20)

for n-type conductivity and

electronegative F17 for p-type conductivity. We previously demonstrated that Cu3N epitaxial thin films exhibit highly symmetric hole and electron mobilities of 80 and 200 cm2(Vs)−1, respectively, through direct nitriding using nitrogen precursors with high chemical potential.17 The Cu 3d and N 2p orbitals form highly hybridized VBM (i.e., highly extended) owing to higher energy levels of N 2p orbitals than O 2p orbitals (in oxides such as Cu2O).. Thus, the generated hole moves to the VBM composed primarily of N 2p orbitals, which suppress formation of hole traps by Cu2+ states, resulting in a defect-tolerant nature favorable for p-channel operation. However, as undoped Cu3N is a native n-type semiconductor, nchannel TFT operation would be expected. Therefore, Cu3N is promising for the channel layers in CMOS-like devices for which symmetric hole and electron transport is a key requirement to achieve high performance (Figure 1b). In this paper, we report the first demonstration of ambipolar transistor operation and of a CMOS-like inverter using a Cu3N channel layer. An electric double-layer transistor (EDLT) with a Cu3N epitaxial channel exhibited ambipolar operation with high and symmetric fieldeffect mobilities of ~ 5 cm2(Vs)−1 for p-channel transport and ~ 10 cm2(Vs)−1 for n-channel transport. CMOS-like inverters composed of two of the same polycrystalline Cu3N ambipolar TFTs on SiO2/Si substrates operated with a high voltage gain of ~ 100.


5


Page 6 of 23

RESULTS AND DISCUSSION We first employed the EDLT structure on the Cu3N epitaxial channel using the ionic liquid DEME-TFSI because this system is suitable for investigating the ultimate potential of novel semiconductors as the ionic liquid results in less processing damage to the channel layer and induces very high charge densities.21 Another advantage of DEME-TFSI is chemical etching of the surface22 to remove the adsorbates that force surface upward band bending.17 EDLTs were fabricated using the following process: a Cu3N epitaxial channel (W/L=200 µm/500 µm) with a thickness of ~60 nm was grown on a LaAlO3(001) substrate using molecular beam epitaxy (MBE) (see Figure S1 for the film structures). Hall effect measurements confirmed that the pristine Cu3N epitaxial film exhibited n-type conduction with a Hall mobility, e,Hall, of ~ 15 cm2(Vs)−1 and a carrier concentration of 1013–1014 cm−3.17 Figure 2a presents the cyclic transfer curve (the drain–source current (IDS) as a function of the applied gate voltages (VG)) of the Cu3N EDLT measured at 220 K, which is slightly higher than the glass transition temperature (190 K) of the ionic liquid.23 VG was swept from 5 V → 0 V → +5 V → 0 V → 5 V at a rate of ~30 mV/s. IDS significantly increased both with positive and negative VG. At the initial VG = 5 V, the EDLT operated in the p-channel accumulation mode, and IDS decreased with increasing VG, with a minimum IDS at VG = ~ +1.0 V (off state). IDS then increased upon further increasing VG, forming a valley-like off state and exhibiting n-channel operation. This behavior indicates that the EDLT operated as an ambipolar TFT with an accumulation pchannel mode and an enhancement n-channel mode. During the following backward scan of


6

Page 7 of 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


VG from +5 to 5 V, the EDLT remained in n-channel operation mode down to VG = ~ −1.0 V, resulting in counter-clockwise hysteresis in the transfer curve. This behavior is attributed mainly to the slow motion of mobile ions in the ionic liquid at the low measurement T of 220 K.23 Electrochemical reaction, i.e., ion intercalation or extraction, may also occur during the accumulation process because of the low amount of residual oxygen and water molecules in the DEME-TFSI ionic liquid, which could potentially affect the hole and electron accumulation in the bulk. However, the suppressed gate leakage current (IGS = ~ 10−8–10−10 A) and the clear observation of the ambipolar intermediate off state near VG = 0 V for both the pand n-channel regimes indicate that the contribution of the electrochemical reaction was negligible. In the p-channel regime, a hole current of IDS = ~ 3×10−6 A was observed at the negative VG with an on/off ratio of ~104, whereas in the n-channel regime, an electron current of IDS = ~ 8×10−6 A was observed at positive VG with an on/off ratio of ~105. Figure 2b presents the output curves (IDS–VDS) of the EDLT in the p- and n-channel regimes. Assuming a gate capacitance of 9.2 μF/cm2 at 220 K,24 the field-effect mobilities in the linear region (lin) were estimated to be ~ 5 cm2V−1s−1 for the p-channel (threshold voltage, Vth = 2.3 V) and ~ 10 cm2V−1s−1 for the n-channel (Vth = +1.5 V), indicating highly symmetric p- and n-channel operations favorable for CMOS-like circuits. These lin values are comparable to the Hall mobilities of pristine n-type Cu3N (e,Hall = ~15 cm2(Vs)−1) and p-type (h,Hall = ~15–30 cm2(Vs)−1) films in which hole doping was induced by chemical adsorption but are lower than the highest hole mobility of 80 cm2(Vs)−1 achieved by F-doping and the electron mobility of 200 cm2(Vs)−1 achieved by unintentional electron doping.17 The on current for both the p- and


7


Page 8 of 23

n-channel at VG = −4 and +4 V, respectively, remained in the semiconducting regime, as confirmed by –T measurements; however, their activation energies were very small (EA = 4–7 meV) (Figure S2b). Having demonstrated the ambipolar transistor operation in the high-quality epitaxial layers, we next evaluated the operation of polycrystalline TFTs on amorphous SiO2/crystalline Si substrates. Bottom-gate TFTs using ~80-nm-thick polycrystalline Cu3N channel layers (W/L = 120 µm/20 µm) were prepared on thermally oxidized SiO2 (~15 nm)/n+-Si substrates using room-temperature (RT) sputtering deposition. The samples were treated by two-step postdeposition annealing, first in NH3/O2 at 450 °C to improve the crystalline quality in the direct nitriding atmosphere and then in pure NH3 at 350 °C to remove residual oxygen impurities in the films (see Figure S3 for the film structures).17 In addition, UV desorption treatment in vacuum was further applied to remove the chemical adsorbates such as O2− that would act as electron traps, as it has been confirmed that the electron mobility is enhanced by vacuum annealing (TA,VAC = 125–175 °C) for epitaxial films (Figure S4). The electrical conductivity () of the as-prepared pristine films after UV irradiation was reduced to ~0.5–2×10−5 Scm−1, which is one order of magnitude lower than that of the epitaxial films ( = ~10−4 Scm−1), and increased to ~10−4 Scm−1 at TA,VAC ≥ 150 °C (Figure S4). Although we tried to measure Hall effect, definite Hall voltages could not be obtained due to the measurement limit of our apparatus. Figure 3a shows the typical transfer characteristics of the pristine and annealed polycrystalline TFTs. The annealed TFTs were treated in vacuum at annealing temperatures


8

Page 9 of 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


TA,VAC of 100 °C–200 °C. Similar to the behavior observed for the EDLT operation, all the TFTs exhibited ambipolar operation by applying positive and negative VG with a narrow off-region, which confirms that both the electron and hole conduction are modulated by the VG. The pristine channel TFT (black curves) operated in an accumulation p-channel mode and an inversion n-channel mode in conjunction with the ambipolar intermediate off region, as also confirmed by the sign inversion of the thermopower (S) by the VG (Figure S5). The output curves of the annealed TFT in the p- and n-channel operation regimes are presented in Figure 3b. All the output curves exhibit clear pinch-off and current saturation, indicating that the TFT operation follows the standard theory of field-effect transistors (Figure S6). The subthreshold voltage swing (SS), saturation mobility (sat), and threshold voltage (Vth) are summarized in Figure 3c. µsat and the linear mobility (µlin) of the as-prepared TFT were ~0.08 and ~0.13 cm2(Vs)−1 for the p-channel operation mode, respectively, and ~8.0×10−3 and ~9.0×10−3 cm2(Vs)−1 for the n-channel operation mode, respectively. By annealing at TA,VAC = 100 °C, the Vth values of both the p- and n-channels were negatively shifted, and IDS for the nchannel operation was clearly increased, as observed in the transfer curve (Figure 3a). The corresponding output curves for the annealed TFT reveal comparable IDS for p- and n-channel operation with a clear pinch-off behavior, as depicted in Figure 3b. The SS was improved from 0.9 to 0.6 Vdec−1 for the p-channel operation and from 2.5 to 1.5 Vdec−1 for the n-channel operation, respectively, suggesting that the density of trap states in the channel layer and at the interface/surface was reduced for both hole and electron transport. The mobilities were

µsat = ~0.06 and µlin = ~0.13 cm2(Vs)−1 for the p-channel operation mode and µsat = ~0.10 and ACS Paragon Plus Environment

9


Page 10 of 23

µlin = ~0.11 cm2(Vs)−1 for the n-channel operation mode. At higher annealing temperatures of TA,VAC = 125 °C–200 °C, the TFT parameters in the p-channel mode deteriorated, whereas those of the n-channel mode improved; i.e., µsat decreased (increased) and the corresponding SS parameter increased (decreased) for p(n)-channel transport (Figure 3c). This change is due to the Fermi level shift toward the CB, as confirmed by the increased electron concentration from ~1013 to ~1016 cm−3 by the vacuum annealing (Figure S4), which in general improves n-channel TFT operation while leading to deterioration of p-channel TFT operation (Figure S7). Finally, we demonstrated the operation of a CMOS-like inverter using bottom gate Cu3N ambipolar TFTs with a TA,VAC = 100 °C channel that exhibits balanced hole and electron transport. Owing to the similar sat values for the p- and n-channel regimes, two TFTs with the same geometry (W/L =700/100 m) and operation characteristics were employed to prepare an inverter circuit, as depicted in Figure 4a. The inverter was characterized by the voltage at the output node (VOUT) under voltage sweeping at the common input gate (VIN). Figures 4b and c show the transfer characteristics of the inverter at positive (b) and negative (c) supply voltages (VDD). The inverter exhibited excellent switching of VOUT both in the first (positive VDD and VIN) and third (negative VDD and VIN) quadrants. Note that the inverter operation in the first and third quadrants is highly symmetric owing to the well-balanced ambipolar properties. The extracted voltage gains, defined as −(∂VOUT/∂VIN), which reached ~96 in the first quadrant and ~106 in the third quadrant, also benefited from the balanced hole and electron transport. These values are comparable to the highest values of ~100 for the state-


10

Page 11 of 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


of-the-art SnO ambipolar transistor16 and ~120 for an ionic-oxide-based vertical CMOS inverter25.

CONCLUSIONS In summary, we have demonstrated that ambipolar transistors with a Cu3N active layer operate with highly symmetric hole and electron mobilities. The field-effect mobilities using epitaxial channels in an EDLT structure were ~5 cm2(Vs)−1 for p-channel operation and ~10 cm2(Vs)−1 for n-channel operation. It was also confirmed that a manufacturing-compatible device, a polycrystalline channel TFT formed on a SiO2/Si substrate, exhibits symmetric ambipolar transistor operation with saturation field effect mobilities of 0.05–0.1 cm2(Vs)−1 for

p-channel operation and ~0.1 cm2(Vs)−1 for n-channel operation. The operation of CMOS-like inverters composed of two identical polycrystalline ambipolar Cu3N TFTs was successfully demonstrated, reaching a high gain of ~100. Cu3N is suitable for cost-effective and scalable manufacturing because of its earth-abundant and environmentally benign constituent elements with a commercially compatible process, as demonstrated for nitride semiconductors.17, 26, 27 Therefore, Cu3N TFTs offer the possibility of high-performance, lowcost, and large-area electronic circuits and applications using both p- and n-channel transistors.


11


Page 12 of 23

EXPERIMENTAL SECTION Fabrication and characterization of epitaxial Cu3N EDLT. 60-nm-thick Cu3N(100) epitaxial films were grown on LaAlO3(100) substrates by MBE28 using a shadow mask to pattern a sixterminal Hall bar channel structure (Figure S2. (b)), followed by two-step annealing, first in NH3/O2 (O2: 6 vol%) at 600 °C and then in NH3 at 350 °C.17 Next, 50-nm-thick source and drain Au electrodes (W/L = 200 m/500 m) were deposited using EB evaporation with a metal shadow mask at RT. The ionic liquid N,N-diethyl-N-(2-methoxyethyl)-N-methylammonium bis(trifluoromethylsulfonyl)imide (DEME-TFSI) was employed as the medium for the gate insulator. The ionic liquid was placed on the channel using a silica glass tube, and a Pt wire gate electrode was dipped in the ionic liquid. The transfer and output characteristics were measured at 220 K using a semiconductor parameter analyzer (Agilent 4155C). Details of the fabrication and characterization of the EDLT using the ionic liquid DEME-TFSI are given elsewhere.29

Fabrication and characterization of polycrystalline Cu3N TFTs and CMOS-like inverters. The TFT and inverter structures were defined using conventional photolithography and lift-off. First, ~80-nm-thick Cu3N polycrystalline thin films (~10×10 mm2) were prepared on SiO2/n+c-Si substrates using conventional radio-frequency (RF) magnetron sputtering with a Cu target, RF power of 20 W, and a gas flow rate of N2/Ar = 10/10 sccm at RT. The as-grown Cu3N thin films were treated by two-step annealing, first in a NH3/O2 (O2: 4 vol%) atmosphere at


12

Page 13 of 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


450 °C for 30 min and then in a NH3 atmosphere at 350 °C for 30 min. Source and drain Au electrodes formed by electron beam evaporation were patterned before the NH3 annealing. UV irradiation in vacuum at RT and subsequent vacuum annealing at TA,VAC = 100 °C–200 °C were performed in the same chamber. All the TFT and inverter characteristics were measured at 300 K using a semiconductor parameter analyzer after the heat treatment. For thermopower (S) measurements, two heaters were placed under the substrate to generate a temperature difference between the source and drain electrodes at 300 K. S of the Cu3N device was measured under steady-state condition in vacuum by giving a temperature difference (ΔT) up to 0.8 K in the in-plane direction.30 The thermo-electromotive force (ΔV) and ΔT were simultaneously measured, and S was determined from the slope of the ΔV–ΔT plot. Cu3N:F and Cu3N:Li(100)/SrTiO3(100) were prepared by NH3/O2 annealing at 600 °C followed by NH3/NF3 annealing for F-doping17 and the intercalation reaction of Li with n-butyllithium (1.6 M solution in n-hexane) for Li-doping18.

Characterization of thin films. X-ray diffraction (XRD) patterns of the polycrystalline films were obtained by performing a 2 scan with glancing incident beam geometry using a Cu K1 + K2 source, and high-resolution (HR)-XRD patterns of the epitaxial films was obtained using a monochromated Cu K1 source with a Ge (220) crystal from a rotary anode (50 kV, 300 mA). The film surface morphology was studied using atomic force microscopy. ASSOCIATED CONTENT


13


Page 14 of 23

Supporting Information. The following files are available free of charge. HR-XRD patterns and an atomic force microscopy (AFM) image of an epitaxial film; Transfer characteristics of the EDLT and temperature dependence of the channel conductivity; XRD and AFM image of a polycrystalline film; Effects of TA,VAC on electrical conductivity of thin films; Thermopower and TFT characteristics; Transfer and output characteristics of polycrystalline channel TFT; Schematic energy diagrams of the TFT channel; (PDF) AUTHOR INFORMATION Corresponding Author *E-mail: [email protected] *E-mail: [email protected] Author Contributions The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript. ACKNOWLEDGMENT This work was financially supported by the MEXT Elements Science and Technology Project and Elements Strategy Initiative to Form Core Research Center, JSPS KAKENHI Grant Nos. 19H02427, 19K22228 and 19H02425 and JST PRESTO Grant No. JPMJPR16R1.


14

Page 15 of 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60



15


Page 16 of 23

FIGURES

Figure 1. (a) Crystal structure of Cu3N (visualized by VESTA

31).

Interstitial doping at the

center vacancy site (the dotted circle) provides efficient doping routes; i.e., p-type doping by F− 17 and n-type doping by Li+ 18, 19 or Cu+ 17, 20. (b) Device structure of CMOS-like inverter using two of the same ambipolar Cu3N TFTs, where the drain-side TFT operates as the pchannel and vice versa, on a SiO2/Si substrate.

Figure 2. Operation characteristics of EDLT using Cu3N(100) epitaxial channels (W/L = 200 µm/500 µm). (a) Transfer curves (IDSVG) and (b) output curves (IDSVDS) measured at 220 K (see also Figure S2a). The gate voltage (VG) in (a) was swept from 5 V → 0 V → +5 V → 0 V → 5 V at a rate of ~30 mV/s. The inset in (b) shows the device structure of the Cu3N EDLT.


16

Page 17 of 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Figure 3. Bottom-gate TFT characteristics and TFT parameters of polycrystalline Cu3N channel layer (W/L = 120 µm/20 µm) on SiO2 (15 nm)/n+-Si substrate treated at various vacuum annealing temperatures (TA,VAC) of 100 °C–200 °C. (a) Transfer (IDSVGS) curves under VDS = +1 V of as-prepared and annealed devices at TA,VAC = 100 °C and 200 °C. The solid and dashed lines represent the forward and reverse sweeps, respectively. (b) Output (IDSVDS) curves for annealed TFT at TA,VAC = 100 °C operating in p- (left panel) and n- (right panel) channel modes. (c) TA,VAC dependence of TFT parameters of SS, sat, and Vth for p-channel (red circle) and nchannel (blue circle) operation of as-prepared and annealed TFTs (see also Figure S6).

Figure 4. CMOS-like inverter characteristics composed of two polycrystalline Cu3N TFTs (W/L = 700 µm/100 µm). (a) Schematic diagram (left panel) and photograph (right panel) of inverter circuit with a common SiO2 (15 nm)/n+-Si bottom gate (VIN). Voltage transfer characteristics and corresponding voltage gain of inverters for (b) first quadrant and (c) third quadrant with VIN at various supply voltages (VDD).


17


Page 18 of 23

REFERENCES (1) Nomura, K.; Ohta, H.; Takagi, A.; Kamiya, T.; Hirano, M.; Hosono, H., Room-temperature Fabrication of Transparent Flexible Thin-film Transistors Using Amorphous Oxide Semiconductors. Nature 2004, 432, 488-492. (2) Kamiya, T.; Hosono, H., Material Characteristics and Applications of Transparent Amorphous Oxide Semiconductors. NPG Asia Materials 2010, 2, 15-22. (3) Hosono, H., Ionic Amorphous Oxide Semiconductors: Material Design, Carrier Transport, and Device Application. J. Non-Cryst. Solids 2006, 352, 851-858. (4) Fortunato, E.; Barquinha, P.; Martins, R., Oxide Semiconductor Thin-film Transistors: A Review of Recent Advances. Adv. Mater. 2012, 24, 2945-2986. (5) Zhang, S. B.; Wei, S.-H.; Zunger, A., A Phenomenological Model for Systematization and Prediction of Doping Limits in II–VI and I–III–VI2 Compounds. J. Appl. Phys. 1998, 83, 3192-3196. (6) Kawazoe, H.; Yasukawa, M.; Hyodo, H.; Kurita, M.; Yanagi, H.; Hosono, H., P-type Electrical Conduction in Transparent Thin Films of CuAlO2. Nature 1997, 389, 939-942. (7) Hosono, H.; Ogo, Y.; Yanagi, H.; Kamiya, T., Bipolar Conduction in SnO Thin Films.

Electrochem. Solid State Lett. 2011, 14, H13-H16. (8) Arai, T.; Iimura, S.; Kim, J.; Toda, Y.; Ueda, S.; Hosono, H., Chemical Design and Example of Transparent Bipolar Semiconductors. J. Am. Chem. Soc. 2017, 139, 17175-17180. (9) Oba, F.; Nishitani, S. R.; Adachi, H.; Tanaka, I.; Kohyama, M.; Tanaka, S., Ab Initio Study of Symmetric Tilt Boundaries in ZnO. Phys. Rev. B 2001, 63, 045410.


18

Page 19 of 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


(10) Deng, H.-X.; Wei, S.-H.; Li, S.-S.; Li, J.; Walsh, A., Electronic Origin of the Conductivity Imbalance between Covalent and Ionic Amorphous Semiconductors. Phys. Rev. B 2013,

87, 125203. (11) Nomura, K.; Kamiya, T.; Yanagi, H.; Ikenaga, E.; Yang, K.; Kobayashi, K.; Hirano, M.; Hosono, H., Subgap States in Transparent Amorphous Oxide Semiconductor, In–Ga–Zn– O, Observed by Bulk Sensitive X-ray Photoelectron Spectroscopy. Appl. Phys. Lett. 2008,

92, 202117. (12) Matsuzaki, K.; Nomura, K.; Yanagi, H.; Kamiya, T.; Hirano, M.; Hosono, H., Effects of Post-annealing on (110) Cu2O Epitaxial Films and Origin of Low Mobility in Cu2O ThinFilm Transistor. Physica Status Solidi (a) 2009, 206, 2192-2197. (13) Ogo, Y.; Hiramatsu, H.; Nomura, K.; Yanagi, H.; Kamiya, T.; Hirano, M.; Hosono, H., Pchannel Thin-film Transistor Using P-type Oxide Semiconductor, SnO. Appl. Phys. Lett. 2008, 93, 032113. (14) Yabuta, H.; Kaji, N.; Hayashi, R.; Kumomi, H.; Nomura, K.; Kamiya, T.; Hirano, M.; Hosono, H., Sputtering Formation of P-type SnO Thin-film Transistors on Glass Toward Oxide Complimentary Circuits. Appl. Phys. Lett. 2010, 97, 072111. (15) Nomura, K.; Kamiya, T.; Hosono, H., Ambipolar Oxide Thin-film Transistor. Adv. Mater. 2011, 23, 3431-3434. (16) Luo, H.; Liang, L.; Cao, H.; Dai, M.; Lu, Y.; Wang, M., Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters. ACS Appl. Mater. Interfaces 2015, 7, 17023-17031.


19


Page 20 of 23

(17) Matsuzaki, K.; Harada, K.; Kumagai, Y.; Koshiya, S.; Kimoto, K.; Ueda, S.; Sasase, M.; Maeda, A.; Susaki, T.; Kitano, M.; Oba, F.; Hosono, H., High‐Mobility p‐Type and n‐Type Copper Nitride Semiconductors by Direct Nitriding Synthesis and In Silico Doping Design.

Adv. Mater. 2018, 30, 1801968. (18) Yamada, N.; Maruya, K.; Yamaguchi, Y.; Cao, X.; Ninomiya, Y., P- to N-Type Conversion and Nonmetal–Metal Transition of Lithium-Inserted Cu3N Films. Chem. Mater. 2015, 27, 8076-8083. (19) Gulo, F.; Simon, A.; Köhler, J.; Kremer, R. K., Li–Cu Exchange in Intercalated Cu3N— With a Remark on Cu4N. Angew. Chem. Int. Ed. 2004, 43, 2032-2034. (20) Fioretti, A. N.; Schwartz, C. P.; Vinson, J.; Nordlund, D.; Prendergast, D.; Tamboli, A. C.; Caskey, C. M.; Tuomisto, F.; Linez, F.; Christensen, S. T.; Toberer, E. S.; Lany, S.; Zakutayev, A., Understanding and Control of Bipolar Self-Doping in Copper Nitride. J.

Appl. Phys. 2016, 119, 181508. (21) Ueno, K.; Nakamura, S.; Shimotani, H.; Ohtomo, A.; Kimura, N.; Nojima, T.; Aoki, H.; Iwasa, Y.; Kawasaki, M., Electric-field-induced Superconductivity in an Insulator. Nat.

Mater. 2008, 7, 855-858. (22) Shiogai, J.; Ito, Y.; Mitsuhashi, T.; Nojima, T.; Tsukazaki, A., Electric-field-induced Superconductivity in Electrochemically Etched Ultrathin FeSe Films on SrTiO3 and MgO.

Nat. Phys. 2015, 12, 42-46. (23) Yuan, H.; Shimotani, H.; Tsukazaki, A.; Ohtomo, A.; Kawasaki, M.; Iwasa, Y., HighDensity Carrier Accumulation in ZnO Field-Effect Transistors Gated by Electric Double


20

Page 21 of 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Layers of Ionic Liquids. Adv. Funct. Mater. 2009, 19, 1046-1053. (24) Ye, J. T.; Inoue, S.; Kobayashi, K.; Kasahara, Y.; Yuan, H. T.; Shimotani, H.; Iwasa, Y., Liquid-gated Interface Superconductivity on an Atomically Flat Film. Nat. Mater. 2010,

9, 125-128. (25) Dindar, A.; Kim, J. B.; Fuentes-Hernandez, C.; Kippelen, B., Metal-oxide Complementary Inverters with a Vertical Geometry Fabricated on Flexible Substrates. Appl. Phys. Lett. 2011, 99, 172104. (26) Masaaki, A.; Kazuo, U.; Akira, T., Cu3N Thin Film for a New Light Recording Media. Jpn.

J. Appl. Phys. 1990, 29, 1985-1986. (27) Nosaka, T.; Yoshitake, M.; Okamoto, A.; Ogawa, S.; Nakayama, Y., Copper Nitride Thin Films Prepared by Reactive Radio-frequency Magnetron Sputtering. Thin Solid Films 1999, 348, 8-13. (28) Matsuzaki, K.; Okazaki, T.; Lee, Y.-S.; Hosono, H.; Susaki, T., Controlled Bipolar Doping in Cu3N (100) Thin Films. Appl. Phys. Lett. 2014, 105, 222102. (29) Katase, T.; Hiramatsu, H.; Kamiya, T.; Hosono, H., Electric Double-layer Transistor Using Layered Iron Selenide Mott Insulator TlFe1.6Se2. Proc. Natl. Acad. Sci. U. S. A. 2014, 111, 3979-3983. (30) Katase, T.; Endo, K.; Ohta, H., Thermopower Analysis of the Electronic Structure Around the Metal-insulator Transition inV1−xWxO2. Phys. Rev. B 2014, 90, 161105(R). (31) Momma, K.; Izumi, F., VESTA 3 for Three-dimensional Visualization of Crystal, Volumetric and Morphology Data. J. Appl. Crystallogr. 2011, 44, 1272-1276.


21


Page 22 of 23


22

Page 23 of 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Table Of Contents Graphic


23

Symmetric Ambipolar Thin-film Transistors and High-gain CMOS-like

Recommend Documents