NANO LETTERS
Synthesis of Silicon Nanowires and Nanofin Arrays Using Interference Lithography and Catalytic Etching
2008 Vol. 8, No. 11 3799-3802
W. K. Choi,* T. H. Liew, and M. K. Dawood AdVanced Materials for Micro- and Nano-Systems Programme, Singapore-MIT Alliance, Department of Electrical and Computer Engineering, National UniVersity of Singapore, Singapore 117576
Henry I. Smith AdVanced Materials for Micro- and Nano-Systems Programme, Singapore-MIT Alliance, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139
C. V. Thompson AdVanced Materials for Micro- and Nano-Systems Programme, Singapore-MIT Alliance, Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139
M. H. Hong ECE-DSI Laser Microprocessing Laboratory, Department of Electrical and Computer Engineering, National UniVersity of Singapore, Singapore 117576 Received July 17, 2008
ABSTRACT We report results on the synthesis of silicon nanostructures that were fabricated using a combination of interference lithography and catalytic etching. With this technique, we were able to create nanostructures that are perfectly periodic over very large areas (1 cm2 or more), where the cross-sectional shapes and the array ordering can be varied. Furthermore this technique can readily and independently control the sizes and spacings of the nanostructures down to spacings of 200 nm or less. These characteristics cannot be achieved using other known techniques.
The application of vapor-liquid-solid (VLS) processes to fabrication of semiconductor nanowires1-5 has led to intense research activity on potential applications of nanowires in future electronic and optoelectronic devices and systems. For example, silicon nanowires have been successfully implemented in field effect transistiors,6 chemical sensors,7 field emitters,8 and solar cells.9 However, use of the VLS mechanism for growth of nanowires for system-level applications has a number of drawbacks. First, without combination with “top-down” techniques such as lithography, “bottom-up” approaches such as VLS cannot be used to create large ordered arrays of nanowires, and even a combined approach has proven to be difficult. There are also * Corresponding author. E-mail:
[email protected]. 10.1021/nl802129f CCC: $40.75 Published on Web 10/28/2008
2008 American Chemical Society
concerns with use of catalysts such as gold at the temperatures required for VLS processes, because the catalyst metal is likely to be incorporated in the wires. Additionally, the VLS technique only allows formation of cylindrical wires or pillars. In many applications, one-dimensional nanostructures with other cross-sectional shapes would be useful. For example, finlike structures have higher surface-to-volume ratios and would therefore have higher efficiencies for sensing applications. Fin shapes are also of great interest for use in metal-oxide-semiconductor field effect transistors in which the channel current can be more readily controlled than in-planar or cylindrical structures.10,11 In this paper, a new process for creating large, perfectly ordered arrays of one-dimensional nanostructures with different cross-sectional shapes is described.
Figure 1. Schematic diagrams illustrating fabrication of Si nanowire arrays using a combination of interference lithography and catalytic etching.
Recently, two publications reported the fabrication of Si nanowire arrays using catalytic etching of Si wafer surfaces.12,13 These processes made use of locally ordered twodimensional (2D) arrays of polystyrene spheres to form a lift-off mask for the patterning of silver films with arrays of holes. When these structures were immersed in a mixture of H2O, HF, and H2O2, the Ag films catalyzed the etching of Si beneath, resulting in Si nanowire array composed of the unetched single crystal silicon. While the polystyrene spheres, and hence the nanowires, are locally ordered, the structure has defects and domains so that order is not maintained over large areas. Recently, we developed14 a combined top-down and bottom-up approach for the synthesis of Si nanowires on Si substrates. For the top-down component, we used interference lithography (IL) combined with anisotropic etching to create a 4-fold symmetric array of inverted pyramids in a Si wafer. The bottom-up components consisted of the agglomeration of deposited gold to form nanodots inside the pyramids,14,15 which served as catalysts for the synthesis of Si nanowires via the VLS technique. This approach has the potential of producing Si nanowires with selected uniform diameters (controlled from 20 to 150 nm) over large areas (1 cm2 or more). However, the native oxide layer on the pyramid walls prevented epitaxial Si nanowire growth. In this paper, we demonstrate the development of a new technique that makes use of IL under different exposure conditions in combination with a templated catalytic etching process. Figure 1 shows the main experimental steps in our 3800
Figure 2. Scanning electron microscopy (SEM) micrographs of (a) Si nanowires, (b) Si nanofins, and (c) Si nanowires with oval cross sections, obtained through interference lithography with different conditions combined with catalytic etching.
IL/catalytic-etching process for the synthesis of Si nanowire arrays. p-Type (100) Si wafers are coated with layers of photoresist (Ultra-i 123) approximately 400 nm thick and cured at 90 °C for 90 s. The photoresist is then exposed using a Lloyd’s-mirror type IL setup16 with a HeCd laser source (λ ) 325 nm). Exposure of the photoresist with periodic square patterns was achieved by two perpendicular exposures of ∼40 s to 1 min each. The unexposed photoresist was then removed using Microposit MF CD-26 developer17 leaving behind circular-shape photoresist dots on the wafer surface. Because no antireflection layer was used on the Si substrates, the samples were subjected to an oxygen plasma etch (power of 30 W, oxygen pressure of 0.5 mbar, etching time of 30-120 s) to remove the residual unexposed photoresist at the Si interface and to reduce the size of the photoresist dots. Gold was thermally evaporated on the substrate to a thickness of ∼25 nm, at a pressure of 10-6 Nano Lett., Vol. 8, No. 11, 2008
Figure 3. SEM micrographs of Si nanowires of different heights obtained by varying the catalytic etching time: (a) 3, (b) 6, and (c) 10 min.
Figure 4. SEM micrographs of Si nanowires with different diameters: (a) approximately 230 nm and (b) approximately 150 nm.
Torr. The samples were then etched in a solution of H2O, HF, and H2O2 at room temperature.13 The concentrations of HF and H2O2 were 4.6 and 0.44 M, respectively. Note that for the nanowires shown in Figure 2a, the chemical-etch time was fixed at 6 min and resulted in Si nanowires of ∼1.5 µm height. The Au was then removed using a standard Au etchant. Panels a-c of Figure 2 show scanning electron micrographs of nanowires, nanofins, and nanowires with oval cross sections, respectively, all created using the process described above. For creation of the nanowires, the process outlined above was used with the two exposures carried out in perpendicular orientations (corresponding to a half angle θ between the two beams of 20°). For the creation of nanofins, we changed the relative orientation between the two exposures from 90° for the creation of nanowires to 30° for creation of nanofins. For creation of wires with oval cross sections, the first exposure was done at θ ) 20°, and it was followed by a second exposure at θ ) 10°. Note that the order symmetry is also different in the three cases shown in Figure 2, with the wire arrays having square symmetry, the nanofins having body-centered rectangular symmetry, and Nano Lett., Vol. 8, No. 11, 2008
Figure 5. SEM micrographs of Si nanowires with different planar densities: (a) 4 × 106 mm-2, (b) 1 × 106 mm-2, and (c) 3.5 × 105 mm-2.
the oval wires having simple rectangular symmetry. Only hexagonal ordering symmetry can be obtained using polystyrene spheres. As can be seen in Figure 3, the use of IL in conjunction with catalytic etching produces large-area arrays of nanowires with high aspect ratios. Panels a-c of Figure 3 show SEM micrographs of Si nanowires of various heights obtained by varying the etching time of our process from 3, 6, and 10 min, respectively. Figure 4 shows results of tuning the diameter of Si nanowires. With a proper selection of exposure time and oxygen plasma 3801
etching conditions, one can obtain photoresist dots of various diameters (see Figure 4) and hence Si nanowires of different diameters. Control of the nanowire diameters and height was also reported by Huang et al. using the same catalytictemplate-etching process with polystyrene spheres as the mask and Ag as the catalyst.13 The density (D) of the Si nanowires produced using the IL/chemical-etching is given by D)
4 sin2 θ λ2
where the half angle for IL exposure (θ) can readily be varied and the wavelength of the laser source λ (325 nm in our case), can be changed. Figure 5 shows SEM micrographs of Si nanowires obtained by varying the angle of exposure in our IL process. By changing θ from 5.5° to 19°, we are able to tune the nanowire density from 3.5 × 105 mm-2 to 4 × 106 mm-2. Huang et al. obtained a nanowire density of ∼2 × 106 mm-2, which is a function of the size of the polystyrene spheres used in the process. However, the Ag thickness that can be used in a lift-off process is limited by the sphere size, ultimately limiting the wire density that can be achieved. Also, ordering of polystyrene spheres becomes increasingly difficult as the sphere size is reduced. It has been demonstrated that IL can be used for patterning at spacings as low as 100 nm,18 and it should be possible to produce diperiodic structures with further reduced spacings in the future.19 It should also be noted that while periodic structures were made over very large 1 cm2 area, techniques have been developed for use of IL to make perfectly periodic structures over the entire surface of 300 mm wafers.20 In summary, interference lithography combined with catalytic etching provides a method for producing aligned single crystal Si wire arrays that are (i) perfectly periodic over very large areas (1 cm2 or more), (ii) have crosssectional shapes that can be varied, (iii) have array ordering symmetries that can be varied, and (iv) have readily and independently controlled sizes and spacings, down to spacings of 200 nm or less. These characteristics cannot be achieved using other known techniques.
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Acknowledgment. This work was partially supported by a grant from the Singapore-MIT Alliance. L.T.H. would like to thank the Singapore-MIT Alliance for the provision of a research assistantship, and M.K.D. thanks Chartered Semiconductors Manufacturing Ltd. for providing a research scholarship. References (1) Huang, M. H.; Wu, Y.; Feick, H.; Tran, N.; Weber, E.; Yang, P. AdV. Mater. 2001, 13, 113. (2) Wu, Y.; Cui, Y.; Huynh, L.; Barrelet, C. J.; Bell, D. C.; Lieber, C. M. Nano Lett. 2004, 4, 433. (3) Eichfeld, S. M.; Ho, T. T.; Eichfeld, C. M.; Cranmer, A.; Mohney, S. E.; Mayer, T. S.; Redwing, J. M. Nanotechnology 2007, 18, 315201. (4) Hochbaum, A. I.; Fan, R.; He, R. R.; Yang, P. D. Nano Lett. 2005, 5, 457. (5) Suh, D. I.; Lee, S. Y.; Hyung, J. H.; Kim, T. R.; Lee, S. K. J. Phys. Chem. C 2008, 112, 1276. (6) Ng, H. T.; Han, J.; Yamada, T.; Nguyen, P.; Chen, Y. P.; Meyyappan, M. Nano Lett. 2004, 4, 1247. (7) Shao, M. W.; Yao, H.; Zhang, M. L.; Wong, N. B.; Shan, Y. Y.; Lee, S. T. Appl. Phys. Lett. 2005, 87, 183106. (8) Wang, Q.; Li, J. J.; Ma, Y. J.; Bai, X. D.; Wang, Z. L.; Xu, P.; Shi, C. Y.; Quan, B. G.; Yue, S. L.; Gu, C. Z. Nanotechnology 2005, 16, 2919. (9) Kelzenberg, M. D.; Turner-Evans, D. B.; Kayes, B. M.; Filler, M. A.; Putnam, M. C.; Lewis, N. A.; Atwater, H. A. Nano Lett. 2008, 8, 710. (10) Hisamoto, D.; Lee, W. C.; Kedzierski, J.; Takeuchi, H.; Asano, K.; Kuo, C.; Anderson, E.; King, T. J.; Bokor, J.; Hu, C. M. IEEE Trans. Electron DeVices 2000, 47, 2320. (11) Kedzierski, J.; Ieong, M.; Nowak, E.; Kanarsky, T. S.; Zhang, Y.; Roy, R.; Boyd, D.; Fried, D.; Wong, H. S. P. IEEE Trans. Electron DeVices 2003, 50, 952. (12) Peng, K. Q.; Huang, Z. P.; Zhu, J. AdV. Mater. 2004, 16, 73. (13) Huang, Z. P.; Fang, H.; Zhu, J. AdV. Mater. 2007, 19, 744. (14) Choi, W. K.; Liew, T. H.; Chew, H. G.; Zheng, F.; Thompson, C. V.; Wang, Y.; Hong, M. H.; Wang, X. D.; Li, L.; Yun, J. Small 2008, 4, 393. (15) Geirmann, A. L.; Thompson, C. V. Appl. Phys. Lett. 2005, 86, 121903. (16) Walsh, M. On the design of lithographic interferometers and their applications. Ph.D. thesis, MIT, Sept. 2004. (17) Microposit MF CD-26 Developer, Manufactured by Shipley Company, Marlborough, MA 01752. (18) Savas, T. A.; Schattenburg, M. L.; Carter, J. M.; Smith, H. I. J. Vac. Sci. Technol. 1996, B14, 4167. (19) Chang, C.; Zhao, Y.; Heilmann, R.; Schattenburg, M. Opt. Lett., accepted for publication. (20) Chen, C. G.; Heilmann, R. K.; Joo, C.; Konkola, P. T.; Pati, G. S.; Schattenburg, M. L. J. Vac. Sci. Technol. 2002, B20, 3071.
NL802129F
Nano Lett., Vol. 8, No. 11, 2008
