The Role of Ti Buffer Layer Thickness on the Resistive

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The Role of Ti Buffer Layer Thickness on the Resistive Switching Properties of Hafnium Oxide Based Resistive Switching Memories Sk. Ziaur Rahaman, Yu#De Lin, Heng#Yuan Lee, Yu#Sheng Chen, Pang-Shiu Chen, Wei#Su Chen, Chien#Hua Hsu, Kan#Hsueh Tsai, Ming-Jinn Tsai, and Pei#Hua Wang Langmuir, Just Accepted Manuscript • DOI: 10.1021/acs.langmuir.7b00479 • Publication Date (Web): 18 Apr 2017 Downloaded from http://pubs.acs.org on April 23, 2017

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The Role of Ti Buffer Layer Thickness on the Resistive Switching Properties of Hafnium Oxide Based Resistive Switching Memories Sk. Ziaur Rahaman,*,† Yu‒De Lin,† Heng‒Yuan Lee,† Yu‒Sheng Chen,† Pang‒Shiu Chen,‡ Wei‒Su Chen,† Chien‒Hua Hsu,† Kan‒Hsueh Tsai,† Ming‒Jinn Tsai,† and Pei‒Hua Wang† †

Electronic and Optoelectronic System Research Laboratories, Industrial Technology Research

Institute, Hsinchu 310, Taiwan ‡

Department of Materials Science and Engineering, MingShin University of Science and

Technology, Hsinchu 304, Taiwan KEYWORDS: nonvolatile memory, resistive random access memory, resistive switching, bipolar resistive switching, complementary resistive switching, RRAM, HfOx, Ti thickness. ABSTRACT Ti/HfOx ‒based resistive random access memory (RRAM) has been extensively investigated as one of the emerging nonvolatile memory (NVM) candidates due to its excellent memory performance and CMOS process compatibility. Although the importance of the role of the Ti buffer layer is well recognized, the detailed understanding about Ti thickness dependent asymmetric switching nature is still missing. To realize this, the present work addresses the effects of the Ti buffer layer thickness on the switching properties of the TiN/Ti/HfOx/TiN 1T1R RRAM. Consequently, we have demonstrated a simple strategy to regulate the FORMING

1 ACS Paragon Plus Environment

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voltage, leakage current, memory window, and decrease the operation current, etc. by varying the thickness of Ti layer on the HfOx dielectrics. Accordingly, controllable and reliable bipolar, complementary, and reverse bipolar resistive switching (BRS, CRS, and R‒BRS) properties have been demonstrated. This work also provides the direction to avoid unwanted CRS properties during 1st RESET operation by decreasing the FORMING voltage. Furthermore, the memory device shows good nonvolatility at ~1 µA programming current by selecting a proper thickness of Ti buffer layer. To achieve reliable BRS properties for low power application the operation current has been further optimized, whereas the memory device shows pulse endurance of more than 7 million cycles at a low pulse width of 50 ns and excellent data retention properties of more than 40 hours at 150oC measurement temperature. 1. INTRODUCTION Resistive random access memories (RRAMs) based on transition metal oxides (TMOs) have been widely investigated as a future nonvolatile memory (NVM) candidate with encouraging potential to serve both embedded and standalone applications, due to its simple structure, low power consumption, multibit operation and high density scaling while maintaining high switching speed, endurance, high temperature retention etc.1‒7 In the past few years, the resistive switching properties have been observed and widely studied in various types of binary metal oxides (BMOs) such as HfOx,8‒13 TiOx,3,4,14‒16 TaOx,17‒19 AlOx,20 NiOx,21,22 and ZrOx,23 etc. Among the several proposed materials for RRAM, the HfOx is one of the most representative candidates due to its superior electrical performances and excellent compatibility with current CMOS technology.8‒13 There are several reports on resistive switching mechanism, but the systematic study is still lacking for many resistive switching materials, and controversial interpretations are widely presented in the literature. The most commonly accepted switching


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mechanism in oxide based bipolar RRAM is the formation and rupture of conducting filament (CF) based on the migration of ionized defects such as oxygen vacancies or anions through BMOs. Since oxygen vacancies play a crucial role in changing the resistance states under the presence of an electric field, therefore, numerous research efforts have been focused on the technical improvements to control the oxygen vacancy concentrations.24‒31Plenty of significant research has been conducted to understand the nature of resistive switching by precise control of oxygen vacancy concentration. For example, the stoichiometry of the PEALD TiOx films can be controlled by controlling precursor decomposition power of the plasma‒activated reactant mixture (N2+O2), which will allow to precisely control the oxygen vacancy concentration and to control the SET voltage of Pt/TiOx/Pt RRAM as well.24 On the other hand, the vacancy concentration can be controlled by metal doping into the oxide layer or by defect engineering using bilayer structure to acquire improved resistive switching properties.25‒27 Therefore, it is believed that the resistive switching properties can be enhanced by controlling the concentration of oxygen vacancies. Although, it is known that the resistivity of the BMOs strongly depends on the exact oxygen stoichiometry, therefore, it is crucial to design the structure or selection of materials for RRAM to achieve reliable memory properties.14,25‒32 In the previous work, we demonstrated that the HfOx ‒based RRAM with Ti buffer layer in TiN/Ti/HfOx/TiN stacks showed excellent resistive switching properties in terms of lifetime and memory performance for the single and 1 ‒kb array devices.8,9,11 Although, the importance of Ti buffer layer in HfOx ‒based RRAM is fairly understood, however, detailed interpretation of Ti thickness dependent asymmetric switching nature is not entirely understood, which limits its application. To realize this, here, we further propose an effortless Ti thickness modulation based


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methodology to control the oxygen vacancy concentrations in HfOx layer and, hence, the switching behavior of 1T1R RRAM. Based on the experimental data, the adjustable FORMING voltage, leakage current, resistance ratio, and operation current, etc. can be achieved by regulating the thickness of Ti layer on the HfOx dielectrics. It has been found that too high or too low concentration of oxygen vacancies generated initially by varying the Ti thickness could limit the performances of the Ti/HfOx ‒based RRAM devices. The memory device using 3 nm thick Ti layer shows controllable bipolar, reverse bipolar, and complementary resistive switching (BRS, R‒BRS, and CRS) scenarios by applying proper operating conditions. Whereas, the memory device using 5 nm thick Ti layer shows excellent BRS properties including pulse cycling (>7 million cycles) and multilevel data retention (>40 hours at 150oC) properties at low operation current. The remainder of this paper is organized into three sections. Section 2 is divided into three subsections: Section 2.1 provides experimental details of Ti/HfOx ‒based 1T1R RRAM test array; Section 2.2 describes the measurement procedure and systems used for this study; Section 2.3 provides the information for physical characterization. Section 3 presents experimental results, which is divided into three subsections: Section 3.1 explains the key functionality of Ti buffer layer thickness on the performance of HfOx ‒based RRAM; Section 3.2 presents the pre‒FORMING ultra‒low power operation resistive switching properties. Controllable BRS, R‒BRS, and CRS scenarios and corresponding mechanism behind different types of resistive switching are discussed in section 3.3. Besides, the pulse endurance of BRS, R‒BRS, and CRS properties have been investigated in this section. Hereafter, suitable Ti thickness and optimized operation current will be discussed for low power application. Finally, conclusions are drawn in Section 4. 2. EXPERIMENTAL DETAILS


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2.1. Memory Devices Fabrication. The RRAM devices studied here are based on the 1T1R test array on 0.18 µm CMOS technology platform to provide current compliance (ICC).8,9 Figure 1a shows the schematic of the fabricated HfOx ‒based 1T1R RRAM device, where MIM stacked layer

integrated

with

metal‒oxide‒semiconductor

field‒effect

transistor

(MOSFET).

Corresponding cross‒sectional transmission electron microscopy (XTEM) image of fabricated 1T1R test array is shown in Figure 1b. The resistive memory devices consisting of TiN/Ti/HfOx/TiN stacked layers were fabricated on 8‒inch Ti/SiO2/Si wafers. During the back‒ end‒of‒line (BEOL) processing, a 80 nm thickness of physical vapor deposited (PVD) TiN metal layer served as bottom electrode (BE) was patterned and planarized by chemical mechanical polished (CMP) on the top of the tungsten plug connected to the drain junction (D) of the transistor. On top of the BE, a 5.5 nm thick HfOx layer was employed as resistive switching layer, followed by the atomic layer deposition (ALD) process (ASM, Polygon 8200) at a temperature of 300oC. Hafnium tetrachloride (HfCl4) and water vapor (H2O) were used as reactants for the deposition of HfOx films. Afterwards, for the intention of this work, five different thicknesses of Ti buffer layer (namely T3: 3 nm, T5: 5 nm, T7: 7 nm, T8.5: 8.5 nm and T10: 10 nm) on the top of HfOx layer were deposited by sputtering. For comparison, we had also prepared the device without the inclusion of Ti layer on HfOx dielectrics (device T0). TiN top electrode (TE) with the thickness of 40 nm was then deposited by the same sputtering system without breaking the vacuum. The memory stacked layers were then patterned via a standard lithography and passivated by low‒temperature oxide (LTO). Finally, post metal annealing (PMA) treatment was performed at 400oC for 5 minutes in the nitrogen ambient. The possible chemical reaction at the interface between Ti and HfO2 during the fabrication process can be written as:


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+ → + The interfacial layer induced by the Ti buffer layer is believed to act as a series resistor and oxygen reservoir during resistive switching.6‒9,11,30 In our previous work, the diffusion of oxygen atoms from HfO2 dielectrics to Ti buffer layer during PMA process have been analyzed using micro‒Auger electron spectroscopy.33 Figure 1c displays the XTEM micrograph of the fabricated RRAM with the inset being an enlarged view of typical TiN/Ti/HfOx/TiN stacked layers (device: T5). The junction area of RRAM was about 0.48 µm × 0.48 µm used in this study to analyze the resistive switching behaviors for all prepared devices. 2.2. Electrical Measurements. The electrical properties were measured using an Agilent 4156C semiconductor parameter analyzer, 81110A pulse/pattern generator, and Versatest V4400 test system. Figure 1d shows the measurement strategy during FORMING, SET and RESET operations of fabricated 1T1R RRAM. The FORMING and SET operations (denoted by green color) were performed by applying positive pulses at Bit Line (BL) or top of the memory stacked layer and Word Line (WL) or gate junction of the transistor, while Source Line (SL) or source junction of the transistor was grounded. Whereas, the RESET operations (denoted by red color) were performed by applying positive pulses at SL and WL, while BL was grounded. A minimum of 50 ns pulse width was applied by 81110A during pulse endurance measurement. 2.3. XTEM Analysis. The memory device for TEM observation was prepared using a dual beam FIB (FEI NOVA 600) system and Gatan 691 Precision Ion Polishing system. The microstructure of the TiN/Ti/HfOx/TiN stacked layers were investigated by XTEM using an FEI Tecnai G2 F20 system with an operating voltage of 200 kV. 3. RESULTS AND DISCUSSION


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3.1. Role of oxygen vacancy and buffer layer on resistive switching. It is well known that the material properties of metal oxides such as electrical, optical and electro‒optic properties are highly influenced by the defects and impurities. Hence, properties of the device are significantly dependents on the morphology of the metal oxides, quality of the surface/interface structure, and chemistry. It is widely accepted that under the presence of an electric field the drift of charged oxygen vacancies are crucial for filament formation and rupture during electro‒FORMING/ SET and RESET processes of RRAM technology.34‒38 However, details of the physical mechanism regarding CF formation and rupture and the composition of the filament, a role of defects and impurities are still challenging. Considering, the composition of CF formed during resistive switching in our fabricated TiN/Ti/HfOx/TiN 1T1R RRAM devices are believed to be consisting of mainly oxygen vacancies. It is well known that the buffer layer such as Ti, Ta, Hf, Zr, etc. are playing a significant role in achieving reliable resistive switching in HfOx ‒based RRAM, in that it allows to control the dielectric strength of the HfOx layer.5‒11,28‒32 Because of the buffer layer acts as an oxygen gettering material, thus introducing oxygen deficient HfOx layer during the fabrication process, as discussed in the experimental section. Based on the Ti thickness variation, the electrical properties such as FORMING voltage (VF), leakage current (IL), and resistance ratios during SET and RESET operations of TiN/Ti/HfOx/TiN 1T1R RRAM is depicted in Figure 2. Note that, more than 150 RRAM devices were tested for each structure to compare. The mean value of VFs of our fabricated RRAM devices with five different thickness such as 3, 5, 7, 8.5 and 10 nm of Ti buffer layers are 2.6, 2.2, 2.0, 1.9 and 1.8 V respectively as shown in Figure 2a. Correspondingly, the ILs are 3.02×10-13, 3.17×10-12, 3.56×10-11, 5.15×10-10 and 4.15×10-9 A respectively. It is observed that the VF (or IL) decreases (or increases) with the increase of Ti thickness, because of high oxygen gettering ability of Ti


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buffer layer, probably this introduces initially higher oxygen vacancy concentration in HfOx layer with increasing Ti thickness, thus introduces higher leakage. The experimental data also shows the higher IL for inserting thick Ti layer on HfOx, which means the dielectric strength of the HfOx layer is reduced by increasing the thickness of Ti layer. In contrast, the device w/o inserting Ti buffer layer device (device: T0) shows much higher VF of ~ 3.6 V; thus changes of VF and IL have observed clearly with introducing different thickness of Ti layer. The FORMING free devices can also be achieved by decreasing the thickness of HfOx layer, however, which will limit the memory device in low power operation.39 Additionally, other researchers have also examined the relationship between VF and IL by changing the thicknesses of Ti or HfOx or both layers in Ti/HfOx ‒based RRAM.28,40 Figure 2b shows the distributions of low resistance state (LRS) and high resistance state (HRS) for different thicknesses of Ti layers. It is noted that the same ICC of ~ 100 µA is applied during DC voltage sweeping mode for all structures (T3 to T10 devices) to compare the resistance state distributions. The figure demonstrates the resistance ratios during resistive switching operation can also be controlled by varying the thickness of Ti buffer layer. Ti thickness dependent controllable VF and higher resistance ratios can be achieved by controlling the thickness of Ti layer in HfOx ‒based RRAM is also reported by Fang et al.28 Moreover, we found that the degradation of HRS with increasing Ti thickness in TiN/Ti/HfOx/TiN structure RRAM devices, this suggests that the initially created oxygen vacancy concentration plays an important role during switching cycles also.26,28 It is also noted that very poor and unstable resistive switching has been observed for T0 device (see Supporting Information Figure S1) at higher ICC after FORMING process, thus sub‒stoichiometric HfOx dielectrics are required to prevent permanent breakdown during FORMING either by controlling


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process deposition parameters or by introducing buffer layers or doping to achieve subsequent reliable resistive switching.8,27,28,32 Based on the above results, the schematic diagram of the generalized model to understand the role of Ti buffer layer thickness on the performance of resistive switching in HfOx ‒based RRAM during SET and RESET operations are depicted in Figures 2c and 2d respectively. The selection of thin Ti layer on HfOx dielectrics is not a good choice to get stable bipolar resistive switching because of the higher VF (Figure 2a), due to the presence of less amount of vacancies as discussed in the previous section. It is worth noting that, although lower VFs can be achieved by the selecting thick Ti buffer layer (device: T10), however, much lower resistance ratio is obtained (Figure 2b), which can be explained by remaining excessive oxygen vacancies in the filament gap region during the RESET operation as compared to the thin buffer layer device (device: T3), thus which will further limit to low current operation. Due to the presence of higher vacancy concentration by inserting thick Ti layer in HfOx ‒based RRAM the expected gap region will be shorter than thin Ti layer, thus HRS degradation occurred. The gap region can be increased with the increase of RESET stop voltages.8,9 However, this method is very risky during SET and RESET cycles which may degrade the device properties and performance as well, because for oxide based bipolar RRAM a suitable RESET voltage is essential to conquering the over RESET problem during cycling.41‒43 During the RESET operation, when the memory device goes to the HRS, the memory state can be disturbed by the presence of oxygen vacancies near the remaining filament region due to the presence of higher vacancy concentration for thick Ti layer memory device. The disturbance of HRS state while reading the memory state may not be prominent for thin Ti layer due to the presence of less vacancy concentration and also due to the larger gap height between the remaining filament and anode. During the switching cycles, the


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initially generated higher defect concentrations can degrade the HRS reported by Lee et al. in Pt/Ta/TaOx/Pt RRAM structure.26 The presence of oxygen vacancies outside of the filament during switching operation may influence the device properties, also reported by Terai et al.44 Thus, in order to achieve the reliable switching in low power operation, the design of the memory element is crucial. Based on the statistical data analysis of HRS distributions (Figure 2b), corresponding currents from T3 to T10 memory device structures for the case of the worst 1T1R test cell (showing minimum HRS) are 1.16×10-8, 1.29×10-8, 4.18×10-7, 9.24×10-7, 2.50×106

A respectively. This suggests that the memory device using ≥ 7 nm thickness of Ti layer on 5.5

nm thick HfOx dielectric layer is not suitable for low power operation. It has been reported that the resistive switching uniformity can be improved when the thickness ratio of Ti/HfOx layer is 1 in Pt/Ti/HfOx/Pt structure.45 In addition, based on the experimental data, Fang et al. reported that the better resistive switching can be achieved when the Ti thickness is about 1 to 2 times of HfOx layer in TiN/Ti/HfOx/TiN RRAM.28 Therefore, it is important to note that the too high or too low concentration of oxygen vacancies by varying Ti buffer layer thickness could limit the performances of the Ti/HfOx ‒based resistive memory devices. 3.2. Pre‒FORMING ultra‒low power operation. The typical I‒V features of T3 and T5 memory devices are shown in Figure 3. In order to realize the suitable thickness of Ti buffer layer on 5.5 nm thick HfOx dielectrics for low current operation, however, the I‒V measurements in Figure 3 have been carried out without applying the FORMING process. The memory device using 3 nm thick Ti layer is showing very unstable resistive switching properties at 0.7 nA ICC, which is shown in Figure 3a. However, no RESET current is observed with increasing ICC up to ~1 µA, which is due to the very unstable filament formation in HfOx layer. The T3 memory device does not show any RESET currents with ten consecutive cycles also as shown in Figure


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S2 (see the Supporting Information). It is believed that the process‒induced initially generated an insufficient amount of oxygen vacancies in HfOx layer will lead to creating the unstable filament at such low ICC. Since the T3 memory device shows very low RESET current ~ 44 pA at ICC ~10 µA, which suggests that this ICC is not enough for the T3 device to form stable CF. Moreover, when ICC was further increased to ~20 µA, the changes of HRS current ~104 order has been observed as shown in Figure 3b. In contrast, the change of HRS current has been observed at ~10 µA ICC for 5 nm thick Ti layer (device: T5) as shown in Figure 3d, due to the presence of higher vacancy concentration compared to the T3 memory device. Due to this, the T5 device did not show any resistive switching at low ICC ~0.7 nA, as shown in Figure 3c. The memory device using 5 nm thick Ti layer is showing resistive switching properties at ICC ~10 nA, and the corresponding ultra‒low RESET current is ~1 pA. Whereas, the corresponding RESET current at ICC ~1 µA is ~0.6 nA. The increasing RESET currents with the increase of ICC’s are attributed towards forming stable CF. To ensure this, we have performed the retention measurement of T3 and T5 memory devices at different ICCs as shown in Figure 4. Based on the nature of RESET properties, the retention test has been carried out from ICC ~1 µA for the T3 device, which is shown in Figure 4a. Randomly selected five cells were measured after the memory devices programmed at ICC ~1 µA. However, the T3 memory device shows completely volatility phenomena at ICC ~1 µA. Although the memory device using 3 nm thickness of Ti layer (device: T3) can be operated at 0.7 nA ICC, the memory device shows nonvolatility at ~15 µA ICC (Figure 4a). To confirm the volatility nature at a low operating current of the T3 memory device, we have adopted Agilent V4400 test system to check the LRSs at different ICCs such as 1, 5, 10 and 15 µA respectively. It can be seen that the memory state changed very quickly even at 30 milliseconds after stressing the memory cells at 1‒10 µA ICCs. We have also adopted constant


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voltage stress (CVS) method,46 whereas the memory cells were stressed at 2.3 V for 1500 seconds; nevertheless, the T3 memory device does not show any retention properties (see Figure S3 in the Supporting Information). Although the T3 memory device shows nonvolatility at ICC ~15 µA, the gradual degradation of memory state towards HRS has been observed even after 60 seconds (not shown here). In contrast, the memory device using 5 nm thick Ti layer (device: T5) shows the nonvolatility properties starting from ~0.2 µA ICC as shown in Figure 4b. Although, the T5 memory device shows the retention for a short time ~20 minutes and good LRS and HRS data retention have been observed at ICC ~1 µA for more than 43 hours at 85oC measurement temperature (Figure 4b). To confirm the nonvolatility of LRS at ICC ~1 µA, we have randomly selected five cells; however, no significant difference is observed. Thus, the memory device using 5 nm thick Ti layer on 5.5 nm thick HfOx dielectrics in TiN/Ti/HfOx/TiN RRAM structure are promising for low current operation. By correlating with the nature of I‒V curves and retention properties for both devices, it should be noted that the process‒induced initially created oxygen vacancies are performing a critical role in obtaining stable retention properties. Therefore, controlling the oxygen vacancy concentration in the switching layer is essential in achieving reliable resistive switching. There are several studies based on the ICC and RESET current dependent retention properties have been demonstrated in the recent years in various RRAM structures.20,22 However, it is reasonably understood that the size of the CF can be controlled by controlling ICC, the retention at low operation current is still challenging due to the forming unstable and narrow CF. Based on our study in Ti/HfOx ‒based 1T1R RRAM, the 5 nm thick Ti layer shows better switching at low operation current compared to 3 nm thick Ti layer on 5.5 nm thick HfOx dielectrics. However, the discussion will be continued for both devices (T3 and T5) due to asymmetric resistive switching properties after the FORMING processes.


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3.3. BRS, CRS and R‒BRS scenarios. The nature of 1st RESET properties after FORMING the T3 and T5 memory devices at ICC ~100 µA are depicted in Figure 5a. In general, for the oxide based bipolar RRAM, the 1st RESET requires higher RESET voltage than subsequent RESET to rupture the CF due to the higher FORMING energy. Therefore, 1st RESET plays a significant role in evaluating the scalability of 1T1R bipolar RRAM. As can be seen in Figure 5a, the memory device using 3 nm thick Ti layer on HfOx dielectrics shows unusual RESET phenomena, i.e., CRS during 1st RESET. In contrast, the T5 memory device shows regular 1st RESET properties. As we know, the T3 memory device required higher VF compared to the T5 device due to the presence of lower oxygen vacancy concentration into the HfOx dielectrics device as explained in the previous sections. Thus, the higher VF may induce the T3 memory cell into CRS after the FORMING operation.47 To increase the density of the simple MIM structure RRAM for future NVM applications; however, the memory device can be implemented in a passive crossbar arrays whereas the resistive switching materials are sandwiched between the series of a perpendicular bottom and parallel top electrodes.3 Thus, using the concept of crossbar architecture, in theoretically by increasing the number of stacking layers the integration density can be further decreased to 4F2/n, where F is the minimum feature size, and n is the number of stacking layer of the crossbar arrays.3,15,48 The concept of the CRS has been realized to elucidate the undesired sneak path issues without the introduction of a selection device.48 However, a typical CRS device consists of two anti‒serially connected bipolar RRAM cells by sharing a common metal electrode, i.e., in M‒I‒M‒I‒M fully stacked configuration. To do this, the CRS device suffers the complexity in fabricating such stacked layers and possible degradation of the intermediate common metal electrode. To solve these problems, recently particular attention has been given to single and bilayer metal oxide layer with eliminating intermediate electrode to


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realize CRS properties.18,49‒55 In this study, the controllable CRS or BRS phenomena can be obtained in TiN/Ti/HfOx/TiN RRAM cell structure by regulating the thickness of Ti buffer layer and further applying proper operating conditions. The CRS properties of the T3 device can be achieved at low and high operating currents by optimizing appropriate biasing schemes as shown in Figure 5b. The CRS properties at low operating current can be accomplished by controlling the FORMING current, however, a further study required to enable repeatable CRS at such low current. The resulting CRS after the FORMING at ICC ~100 µA of the T3 memory device can be further optimized by controlling the sweeping voltage sequence as follows: 0 V → +1.3 V → 0 V → -1.3 V → 0 V. During the switching cycles the maximum current has been reached to ~120 µA before going to HRS at the both positive (+1.2 V) and negative (-1.1 V) voltage regions. Figure 5c and 5d shows the typical scenarios between the conversions of CRS ↔ BRS properties by applying proper biasing conditions. As we have seen the T3 memory device has shown the CRS after applying the FORMING process, as marked by curve 1 (black color) in Figure 5c, and the repeatable CRS properties can be obtained by keeping the same operating conditions. However, the memory device can be converted from CRS to BRS by increasing the positive sweeping voltage to +1.5 V, as marked by curve 2 (red color). Thus, a slight increase of sweeping voltage will allow converting the memory device from CRS to BRS. After this conversion, the memory device can show repeatable BRS phenomena by controlling the ICC, which is important to obtain reproducible bipolar switching. However, further increase (curve 3: blue color) and decrease (curve 4: greenish‒blue color and curve 5: purple color) of operating voltage will not effect on BRS properties as shown in Figure 5c. The conversion from BRS to CRS and from CRS to BRS properties have been depicted in Figure 5d. The conversion of CRS properties can be obtained by applying higher ICC or when the current clamp function from the


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memory unit has been removed, as shown in curves 6 (black color), 9 (greenish‒blue color) and 10 (purple color) respectively in Figure 5d. The curve 7 (red color) shows the transition from CRS to BRS again and the repeatable BRS properties (curve 8: blue color and curve 11: green color) by increasing positive bias voltage and by limiting the ICC using current clamp function of the memory unit. Besides, Egorov et al. have also shown the transition between CRS ↔ BRS can be achieved by applying an asymmetrical sweeping voltage in TiN/HfOx/TiN memory structure.53 Although, during the BRS operation in a 1T1R bipolar RRAM test array, the activation of unwanted self‒CRS from BRS is very risky. Once the CRS is activated during bipolar operation, its feature of indistinguishable resistance states at low voltage bias can significantly degrade the memory window.41 However, in the present study, we have seen that the initially created oxygen vacancy concentration in HfOx dialectics are critically important to activate the memory device into BRS or CRS by changing the thickness of Ti layer. We next turn towards the mechanism behind different types of resistive switching properties of our memory device which is illustrated schematically in Figure 6a. Corresponding I‒V curves of different resistive switching scenarios are shown in Figures 6b‒e. To explain different types of resistive switching such as BRS, CRS, and R‒BRS properties, let us begin the consideration of BRS properties. Figure 6b shows the normal BRS properties have been achieved by applying following sweeping voltage sequence of 0 V → +1.6 V → 0 V → -1.4 V → 0 V and the ICC was limited to ~100 µA. Corresponding SET and RESET voltages are +0.8 V and -0.7 V respectively. Under the positive bias on TE, the charged oxygen vacancies are drifted towards the cathode, leading to the creation of localized CF between cathode and anode. At the same instant, an annihilation reaction will occur by drifting oxygen ions towards the anode, where oxygen ions released two electrons and converted into an oxygen atom. The RESET operation or


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rupture of the CF takes place by applying negative bias, creating a gap between the electrode and residual filament, the negatively charged oxygen ions migrate back to the oxide from the anode and recombine with the oxygen vacancies. The LRS and HRS states are denoted by {S1} and {R1} respectively in Figure 6b, the corresponding mechanism during SET and RESET operations are denoted by {S1} and {R1} respectively in Figure 6a, whereas oxygen vacancies are contributing to connect and disconnect the CF by applying both positive and negative biases respectively. As shown in Figure 6c, the CRS properties demonstrated four‒step switching processes to complete one cycle: A) SET‒1 occurred with increasing positive voltage started from 0 V, whereas an instantaneous current jump has been seen at a threshold voltage of +0.7 V (denoted as VTH1). The SET process at the positive bias regions will follow the mechanism same as the SET process for BRS (denoted by {S1} in Figure 6C and corresponding mechanism is denoted by {S1} in Figure 6a), whereas the oxygen vacancies are accumulated on the virtual cathode remained at BE and subsequently grow through the switching material towards to the TE to form CF. The corresponding current at 0.8 V is ~80 µA, because of the current is not limited by the transistor, so the current is increasing continuously and reaches 120 µA at 1.2 V. During this period, more oxygen vacancies will believe to be accumulated at the TE sites; thus another filament has started to grow at the top interface, as denoted by {S2} in Figures 6a and 6c respectively. B) RESET‒1 occurred, when the bias voltage is further increased to 1.3 V threshold voltage (denoted as VTH2) another current jump (i.e., decreases) from 120 µA to 22 µA has been observed. At higher positive voltage the current is decreasing due to the depletion of oxygen vacancies, as denoted by {R2} in Figures 6a and 6c respectively. C) SET‒2 occurred at negative voltage sweeping regions, there is an instantaneous current jump appeared again at -0.7 V threshold voltage (denoted as VTH3) as shown in Figure 6c. Corresponding filament formation


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process due to SET‒2 process at negative bias voltage is denoted by {S3} in Figure 6a. However, the shape and growth direction of CF during SET‒2 process will be altered than SET‒1 process, due to applied negative voltage. The corresponding current at -0.8 V is ~89 µA. Further increase of negative voltage will allow the memory device to reach into minimum resistance level at -1.1 V (current ~ 120 µA) due to the absence of current clamp unit. Meanwhile, the oxygen vacancies have started to accumulate at the BE sites by increasing negative voltage from -0.8 V, denoted by {S4} in Figures 6a and 6c respectively. D) RESET‒2, a further negative voltage increase to -1.2 V threshold voltage (denoted as VTH4) leads memory device to change the state from LRS to HRS, due to the rupture of the CF close to the TE sites as denoted by {R3} in Figures 6a and 6c respectively. The asymmetry shape of CF during CRS is due to the depletion of charged oxygen vacancies towards the top or bottom electrodes.49,51 In the case of BRS, the LRS can be controlled by the controlling of ICC during the SET operation, in this way the formation of effective CF size is controllable. Consequently, during SET operation at given ICC in BRS the formation of effective filament size in the gap region is limited.49,51 As we have seen, the transition from BRS to CRS has occurred when the current clamp unit from the memory device is eliminated during the SET operation. For the CRS, the growth of the CF in the gap region is only limited by the available conductive defects, due to the absence of current clamp unit in the memory device.49,51 Figure 6d shows the transition between BRS ↔ CRS, can be achieved by controlling the proper operating conditions in the T3 memory device. However, the memory device using a 3 nm thick Ti layer on HfOx dielectrics in TiN/Ti/HfOx/TiN memory device structure shows R‒BRS properties as shown in Figure 6e. The R‒BRS properties can be achieved by further increasing the sweeping voltage and which is optimized by controlling the following sweeping voltage sequences: 0 V → +2 V → 0 V → -2 V → 0V. Corresponding SET


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and RESET voltages are -0.8 V and +1.7 V respectively. Corresponding SET and RESET mechanism for R‒BRS has been denoted by {S3} and {R4} in Figure 6a and 6e respectively. It is believed that the CF growth direction for R‒BRS will be reversed than normal BRS due to the application of opposite bias polarity. However, different shape and size of CF are expected for R‒BRS due to applied dissimilar operating condition between BRS and R‒BRS.42,56 The asymmetrical resistive switching properties between BRS and R‒BRS can be explained by the asymmetry of the potential barrier at the top and bottom interfaces. In order to realize the repeatability of different kinds of resistive switching, we have further performed the pulse endurance test by applying proper operating conditions as shown in Figure 7. The memory device using 3 nm thick Ti layer on HfOx dielectrics in TiN/Ti/HfOx/TiN memory device structure shows excellent pulse endurance characteristics for >1000 continuous SET/RESET cycles under BRS, CRS, and R‒BRS operations. Due to the asymmetry nature of CF, slight degradation of HRS with increasing number of cycles has been observed for CRS and R‒ BRS. Based on the current investigation the T3 memory device shows stable BRS and R‒BRS properties under the high operating currents. Moreover, we have demonstrated a way to achieve reliable bipolar and complementary resistive switching properties in a single memory layer structure. It is worth noting that the coexistence of BRS, CRS and URS properties have been previously reported in TiN/HfOx/TiN memory layer structure.49 More interestingly, this study provides stable CRS properties by regulating Ti buffer layer thickness in TiN/Ti/HfOx/TiN memory device structure. In CRS phenomena, there are two RESET (RESET‒1 and RESET‒2) processes occurred at both positive and negative polarities; thus the memory device shows two HRS at positive bias region and negative bias region. The major advantage of using CRS properties that each program sequence ends up with a RESET operation as can be seen in Figure


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6c, thus the memory cells always remains in the HRS, due to this the CRS can effectively suppress the sneak current issues in passive crossbar arrays. Therefore, the present results demonstrate that the CRS properties obtained in the T3 memory device are a good candidate for future ultra‒dense crossbar memory arrays. However, a more detailed analysis is currently being conducted, and it is intended to investigate the further reduction of operation current, stable and long endurance properties, etc. in the BRS, CRS, and R‒BRS regimes. In the last section, we will switch to study the T5 memory device which shows excellent BRS properties at low operation current, as discussed in the previous sections. To consider it as a low operating power reliable candidate, we have analyzed the T5 memory device using similar measurement procedures as a T3 memory device, which is shown in Figure 8. Interestingly, the CRS properties were not observed in the T5 memory device with increasing ICC from 10 µA to >400 µA; thus selection of VF by adjusting Ti/HfOx thickness ratios are essential. To confirm this, we had applied the voltage up to maximum level through WL of the transistor to allow maximum current pass through the memory stacked layer. Corresponding typical I‒V characteristics with continuing 100 DC cycles are depicted in Figure S4a (see Supporting Information). As can be seen in Figure S4b (see Supporting Information), the LRS has increased from ~2.2 kΩ resistance level to ~200 kΩ resistance level at the 3rd cycle, thereafter the memory state has returned to its original states. The increase of LRS during cycling tests can be explained by worn filament model as discussed in the previous study.41,47 Although the T5 memory device shows CRS properties with continuing cycles at higher ICCs, nevertheless we are not interested in operating the memory device at such high programming current because of considering for low power application. As we have seen in the typical case after FORMING and RESET operations, the T5 memory device shows stable BRS properties starting from ~10 µA ICC by applying the sweeping


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voltage as follows: 0 V → +1.4 V → 0 V → -1.3 V → 0 V, shown in Figure 8. Corresponding SET and RESET voltages are +1 V and -0.4 V respectively. The increase of RESET currents and RESET voltages have been observed with increasing ICCs, due to the forming strong CF at higher operating currents.8,42 Although the T5 memory device shows good nonvolatility at low operation current of ~ 1 µA as shown in Figure 4b, however in real applications the endurance properties at such low current is still challenging. To realize this, we have optimized the suitable operation current (~10 µA) to obtain stable endurance and retention properties as well for the T5 memory device. Figure S5 (see Supporting Information) shows the pulse cycling tests of five randomly selected cells of the T5 memory device, however, no significant difference is observed with continuous reading up to 100 consecutive cycles. To ensure this, we successfully reached >7 million cycles using without verifying method, as shown in Figure 9a. Figure 9b shows retention evolution of T5 memory device at 150oC measurement temperature for >40 hours, where LRSs are programmed at different ICC’s to ensure the multilevel (MLC) operation. 4. CONCLUSION This paper investigates the Ti thickness modulation based simple strategy to regulate the oxygen vacancy concentration in the HfOx film and implemented to realize the asymmetric resistive switching nature in the TiN/Ti/HfOx/TiN 1T1R RRAM test arrays. Accordingly, we have demonstrated a way to control the VF, IL, resistance ratios, and reduction of operation current by regulating the thickness of Ti layer on HfOx dielectrics. The VF (or IL) decreases (or increases) with the increase of the thickness of Ti layer due to the higher oxygen gettering ability of Ti buffer layer, this introduces initially higher oxygen vacancy concentration in HfOx layer with increasing Ti thickness. Moreover, we found that the degradation of HRS during bipolar operation with increasing Ti thickness on HfOx dielectrics, thus the initially created oxygen


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vacancy concentration plays an important role to control the resistance ratios. Based on the experimental data it has been confirmed that the too high or too low concentration of oxygen vacancies by varying Ti buffer layer thickness could limit the performances of the Ti/HfOx ‒ based memory devices. The memory device using 3 nm thick Ti layer on HfOx dielectrics shows controllable BRS, CRS, and R‒BRS properties, however, the obtained CRS properties can effectively suppress the sneak current issues in large scale integration of passive crossbar arrays. In addition, various and controllable resistive switching scenarios can be achieved by controlling the proper operating conditions. The present work also provides the way to eliminate the CRS properties during 1st RESET operation by decreasing the VF in Ti/HfOx ‒based RRAM device. Moreover, the memory device using 5 nm thick Ti layer on HfOx dielectrics shows good nonvolatility at ICC ~1 µA for more than 43 hours at 85oC measurement temperature. To achieve reliable BRS properties for future low power nonvolatile memory application the operation current has been further optimized, whereas the memory device shows excellent pulse endurance of >7 million cycles and data retention properties of >40 hours at ~10 µA ICC and at 150oC measurement temperature. ASSOCIATED CONTENT Supporting Information available: I‒V curves of w/o Ti buffer layer memory device, I‒V curves at 1 µA ICC, CVS method and corresponding retention properties, I‒V curves at high operating current and corresponding resistance states during cycling, and pulse cycling measurements of five randomly selected cells. This information is available free of charge via the Internet at http://pubs.acs.org. AUTHOR INFORMATION Corresponding Author


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*E‒mail: [email protected], [email protected]; Tel: +886‒3‒5917592; Fax: +886‒3‒5917690; Address: Rm. 334, Bldg. 11, 195, Sec. 4, Chung Hsing Road, Chutung, Hsinchu, 31040, Taiwan, R.O.C. Notes The authors declare no competing financial interest.

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(35) Calka, P.; Martinez, E.; Delaye, V.; Lafond, D.; Audoit, G.; Mariolle, D.; Chevalier, N.; Grampeix, H.; Cagli, C.; Jousseaume, V.; Guedj, C. Chemical and Structural Properties of Conducting Nanofilaments in TiN/HfO2‒Based Resistive Switching Structures. Nanotechnology, 2013, 24, 085706. (36) Zhao, L.; Sergiu, C.; Köpe, B. M.; Jurczak, M.; Nishi, Y. Ab initio Modeling of Oxygen‒ Vacancy Formation in Doped‒HfOx RRAM‒ Effects of Oxide Phases, Stoichiometry, and Dopant Concentration. Appl. Phys. Lett. 2015, 107, 013504. (37) Jeon, S. H.; Son, W. J.; Park, B. H.; Han, S. Multiscale Simulation on Electromigration of the Oxygen Vacancies in Metal Oxides. Appl. Phys. A 2011, 102, 909‒914. (38) Traoré, B.; Blaise, P.; Vianello, E.; Perniola, L.; Salvo, B. D.; Nishi, Y. HfO2‒Based RRAM: Electrode Effects, Ti/HfO2 Interface, Charge Injection, and Oxygen (O) Defects Diffusion Through Experiment and Ab Initio Calculations. IEEE Trans. Electron Devices 2016, 63, 360‒368. (39) Chen, Y. S.; Lee, H. Y.; Chen, P. S.; Wu, T. Y.; Wang, C. C.; Tzeng, P. J.; Chen, F.; Tsai, M. J.; and Lien C. An Ultrathin Forming‒Free HfOx Resistance Memory with Excellent Electrical Performance. IEEE Electron Device Lett. 2010, 31, 1473‒1475. (40) Fisher, K. G. Y.; Bersuker, G.; Butcher, B.; Padovani, A.; Larcher, L.; Veksler, D.; Gilmer, D. C. Leakage Current–Forming Voltage Relation and Oxygen Gettering in HfOx RRAM Devices. IEEE Electron Device Lett. 2013, 34, 750‒752. (41) Lee, H. Y.; Chen, Y. S.; Chen, P. S.; Tsai, C. H.; Gu, P. Y.; Wu, T, Y.; Tsai, K. H.; Rahaman, S. Z.; Chen, W. S.; Chen, F.; Tsai, M. J.; Lee, M. H.; Ku, T. K. Impact of Self‒ Complementary Resistance Switch Induced by Over‒Reset Energy on the Memory Reliability of Hafnium Oxide Based Resistive Random Access Memory. Jpn. J. Appl. Phys. 2014, 53, 08LE01. (42) Balati, S.; Ambrogio, S.; Wang, Z.; Sills, S.; Calderoni, A.; Ramaswamy, N.; Ielmini, D. Voltage‒Controlled Cycling Endurance of HfOx‒Based Resistive‒Switching Memory. IEEE Trans. Electron Devices 2015, 62, 10, 3365‒3372. (43) Yu. S.; Guan, X.; Wong, H. S. P. On the Stochastic Nature of Resistive Switching in Metal Oxide RRAM: Physical Modeling, Monte Carlo Simulation, and Experimental Characterization. IEEE International Electron Device Meeting (IEDM) 2011, 413‒416.


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(44) Terai, M.; Sakotsubo, Y.; Saito, Y.; Kotsuji, S.; Hada, H. Memory‒State Dependence of Random Telegraph Noise of Ta2O5/TiO2 Stack ReRAM. IEEE Electron Device Lett. 2010, 31, 11, 1302‒1304. (45) Hua, P.; Ning, D. A Forming‒Free Bipolar Resistive Switching in HfOx‒Based Memory with a Thin Ti Cap. Chin. Phys. Lett. 2014, 31, 10, 107303. (46) Kalantarian, A.; Bersuker, G.; Gilmer, D.C.; Veksler, D.; Butcher, B.; Padovani, A.; Pirrotta, O.; Larcher, L.; Geer, R.; Nishi, Y.; Kirsch, P. Controlling Uniformity of RRAM Characteristics Through the Forming Process.

IEEE International Reliability Physics

Symposium 2012, 6C.4.1‒6C.4.5. (47) Lee, H. Y.; Chen, P. S.; Chen, Y. S.; Tsai, C. H.; Gu, P. Y.; Wu, T, Y.; Tsai, K. H.; Rahaman, S. Z.; Lin, Y. T.; Chen, W. S.; Chen, F. T; Tsai, M. J.; Ku, T. K. Scalability Issue in Ti/HfO Bipolar Resistive Memory with 1T‒1R Configuration by Resistance Pinning Effect During 1st RESET and its Solution. IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2013, 6545586. (48) Linn, E.; Rosezin, R.; Kügeler, C.; Waser, R. Complementary Resistive Switches for Passive Nanocrossbar Memories. Nat. Mater. 2010, 9, 403‒406. (49) Nardi, F.; Balatti, S.; Larentis, S.; Ielmini D. Complementary Switching in Metal Oxides: Toward Diode‒Less Crossbar RRAMs. IEEE International Electron Device Meeting (IEDM) 2011, 709‒712. (50) Yang, Y.; Sheridan, P.; Lu, W. Complementary Resistive Switching in Tantalum Oxide‒ Based Resistive Memory Devices. Appl. Phys. Lett. 2012, 100, 203112. (51) Balati, S.; Larentis, S.; Gilmer, D. C.; Ielmini, D. Multiple Memory States in Resistive Switching Devices through Controlled Size and Orientation of the Conductive Filament. Adv. Mater. 2013, 25, 1474‒1478. (52) Tang, G.; Zeng, F.; Chen, C.; Liu, H.; Gao, S.; Song, C.; Lin, Y.; Chen, G.; Pan, F. Programmable Complementary Resistive Switching Behaviours of a Plasma‒Oxidised Titanium Oxide Nanolayer. Nanoscale 2013, 5, 422‒428. (53) Egorov, K. V.; Kirtaev, R. V.; Lebedinskii, Yu. Yu.; Markeev, A. M.; Yu.; Matveyev, A.; Orlov, O. M.; Zablotskiy, A. V.; Zenkevich A. V. Complementary and Bipolar Regimes of Resistive Switching in TiN/HfO2/TiN Stacks Grown by Atomic‒Layer Deposition. Phys. Status Solidi A, 2015, 212, 4, 809–816.


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(54) Zhang, H. Z.; Ang, D. S.; Gu, C. J.; Yew, K. S.; Wang, X. P.; Lo, G. Q. Role of Interfacial Layer on Complementary Resistive Switching in the TiN/HfOx/TiN Resistive Memory Device. Appl. Phys. Lett. 2014, 105, 222106. (55) Brivio, B.; Frascaroli, J.; Spiga, S. Role of Metal‒Oxide Interfaces in the Multiple Resistance Switching Regimes of Pt/HfO2/TiN Devices. Appl. Phys. Lett. 2015, 107, 023504. (56) Yoon, K. J.; S. Song, J.; Seok, J. Y.; Yoon, J. H.; Park, T. H.; Kwon, D. E.; Hwang C. S. Evolution of the Shape of the Conducting Channel in Complementary Resistive Switching Transition Metal Oxides. Nanoscale, 2014, 6, 2161‒2169.

FIGURE CAPTION Figure 1: (a) Schematic of the Ti/HfOx based 1T1R RRAM test structure, where TiN/Ti/HfOx/TiN stacked layer integrated with MOS transistor. (b)‒(c) TEM cross section image of the typical RRAM cell integrated with the standard 0.18 µm CMOS transistor and HRTEM image of the typical TiN/Ti/HfOx/TiN stacked layers. The thickness of the HfOx layer is about 5.5 nm. (d) Schematic of the 1T1R RRAM test structure during FORMING/SET and RESET operations. SET and RESET operations for typical bipolar cases. Figure 2: The measured electrical properties such as VF, IL, and LRS/HRS during SET and RESET operations. More than 150 RRAM devices were tested for each structure to compare. (a) Dependence of VF and IL on the thickness of Ti buffer layer in TiN/Ti/HfOx/TiN 1T1R RRAM. The VF (or IL) decreases (or increases) with the increase of Ti thickness. (b) Distribution of LRSs, HRSs, and corresponding resistance ratios (HRS/LRS) of the prepared memory devices from T0 to T10. Same ICC of ~100 µA is applied during DC voltage sweeping mode for all cases. Schematics of the role of (c) thin and (d) thick Ti buffer layer thickness of HfOx ‒based RRAM during SET and RESET operations. Selection of buffer layer thickness is critically important, too


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high or too low concentration of oxygen vacancies by varying Ti buffer layer thickness may limit the performances of the Ti/HfOx ‒based resistive memory devices. Figure 3. Typical pre‒FORMING I‒V features of T3 and T5 memory devices. (a) Unstable resistive switching properties are obtained at 0.7 nA ICC. T3 memory device does not show any RESET current with increasing ICC up to ~1 µA, whereas ~44 pA RESET current is obtained at ~10 µA ICC. (b) The changes of HRS current ~104 order is observed at ~20 µA ICC for the T3 memory device. (c) The T5 memory device shows resistive switching starting from 10 nA ICC due to the presence of higher vacancy concentrations in HfOx dielectrics compared to the T3 memory device. Corresponding ultra‒low RESET current of ~1 pA is observed. (d) The change of HRS current is obtained at ~10 µA ICC for the T5 memory device. Figure 4. Retention measurements of T3 and T5 memory devices. (a) LRS retention properties of the T3 memory device at different ICCs such as 1 µA, 5 µA, 10 µA and 15 µA respectively using HP4156C and Agilent V4400 measurement systems. The memory device shows nonvolatility properties at ~15 µA ICC. (b) The T5 memory device shows nonvolatility properties at ~0.2 µA ICC for ~20 minutes and stable memory states are observed at ICC ~1 µA for more than 43 hours at 85oC measurement temperature. Figure 5. Bipolar and complementary resistive switching scenarios. (a) The nature of 1st RESET after FORMING operations of T3 and T5 memory devices. The T3 memory device shows abnormal RESET phenomena. The normal RESET phenomena are observed for the T5 memory device. (b) Typical CRS properties of the T3 memory device at low and high operating currents. (c) and (d) Typical scenarios between the CRS to BRS and BRS to CRS conversations by applying proper operating conditions of the T3 memory device. Figure 6. (a) Possible schematic diagrams explaining the mechanism behind different types of resistive switching obtained in Ti/HfOx ‒based RRAM devices. Possible shape and size of the CFs during SET from {S1} to {S4} and RESET from {R1} to {R4} operations have been illustrated. Corresponding typical (b) BRS, (c) CRS, (d) transition between CRS↔BRS, and (e) R‒BRS I‒V curves. The asymmetry shape of CF during CRS is due to the depletion of charged oxygen vacancies towards the top or bottom electrodes. The CF growth direction for R‒BRS will be opposite than normal BRS due to the application of reverse bias polarity. Figure 7. Pulse endurance measurements of the T3 memory device. The memory device shows excellent pulse endurance characteristics for >1000 continuous SET/RESET cycles under BRS,


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CRS, and R‒BRS operations by applying proper operating conditions. A minimum pulse width of 50 ns is applied during SET/RESET cycles for all cases. Figure 8. Typical I‒V characteristics of T5 memory device operated at different ICCs. The CRS properties are not observed in the T5 memory device with increasing ICC from ~10 µA to ~420 µA. The memory device shows stable BRS properties at ~10 µA ICC, corresponding SET and RESET voltages are +1 V and -0.4 V respectively. Figure 9. (a) Excellent unverified pulse endurance characteristics of >7 million cycles are obtained at low ICC of ~10 µA for the T5 memory device. (b) MLC retention tests of the T5 memory device. Both LRS and HRS states can maintain >40 hours at 150oC measurement temperature without any degradation.


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Figure 1: (a) Schematic of the Ti/HfOx based 1T1R RRAM test structure, where TiN/Ti/HfOx/TiN stacked layer integrated with MOS transistor. (b)‒(c) TEM cross section image of the typical RRAM cell integrated with the standard 0.18 µm CMOS transistor and HRTEM image of the typical TiN/Ti/HfOx/TiN stacked layers. The thickness of the HfOx layer is about 5.5 nm. (d) Schematic of the 1T1R RRAM test structure during FORMING/SET and RESET operations. SET and RESET operations for typical bipolar cases. 367x278mm (300 x 300 DPI)

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Figure 2: The measured electrical properties such as VF, IL, and LRS/HRS during SET and RESET operations. More than 150 RRAM devices were tested for each structure to compare. (a) Dependence of VF and IL on the thickness of Ti buffer layer in TiN/Ti/HfOx/TiN 1T1R RRAM. The VF (or IL) decreases (or increases) with the increase of Ti thickness. (b) Distribution of LRSs, HRSs, and corresponding resistance ratios (HRS/LRS) of the prepared memory devices from T0 to T10. Same ICC of ~100 µA is applied during DC voltage sweeping mode for all cases. Schematics of the role of (c) thin and (d) thick Ti buffer layer thickness of HfOx ‒based RRAM during SET and RESET operations. Selection of buffer layer thickness is critically important, too high or too low concentration of oxygen vacancies by varying Ti buffer layer thickness may limit the performances of the Ti/HfOx ‒based resistive memory devices. 368x286mm (300 x 300 DPI)


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Figure 3. Typical pre‒FORMING I‒V features of T3 and T5 memory devices. (a) Unstable resistive switching properties are obtained at 0.7 nA ICC. T3 memory device does not show any RESET current with increasing ICC up to ~1 µA, whereas ~44 pA RESET current is obtained at ~10 µA ICC. (b) The changes of HRS current ~104 order is observed at ~20 µA ICC. (c) The T5 memory device shows resistive switching starting from 10 nA ICC due to the presence of higher vacancy concentrations in HfOx dielectrics compared to the T3 memory device. Corresponding ultra‒low RESET current of ~1 pA is observed. (d) The change of HRS current is obtained at ~10 µA ICC for the T5 memory device. 359x272mm (300 x 300 DPI)


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Figure 4. Retention measurements of T3 and T5 memory devices. (a) LRS retention properties of the T3 memory device at different ICCs such as 1 µA, 5 µA, 10 µA and 15 µA respectively using HP4156C and Agilent V4400 measurement systems. The memory device shows non‒volatility properties at ~15 µA ICC. (b) The T5 memory device shows non‒volatility properties at ~0.2 µA ICC for ~20 minutes and stable memory states are observed at ICC ~1 µA for more than 43 hours at 85oC measurement temperature. 362x133mm (300 x 300 DPI)


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Figure 5. Bipolar and complementary resistive switching scenarios. (a) The nature of 1st RESET after FORMING operations of T3 and T5 memory devices. The T3 memory device shows abnormal RESET phenomena. The normal RESET phenomena are observed for the T5 memory device. (b) Typical CRS properties of the T3 memory device at low and high operating currents. (c) and (d) Typical scenarios between the CRS to BRS and BRS to CRS conversations by applying proper operating conditions of the T3 memory device. 361x263mm (300 x 300 DPI)


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Figure 6. (a) Possible schematic diagrams explaining the mechanism behind different types of resistive switching obtained in Ti/HfOx ‒based RRAM devices. Possible shape and size of the CFs during SET from {S1} to {S4} and RESET from {R1} to {R4} operations have been illustrated. Corresponding typical (b) BRS, (c) CRS, (d) transition between CRS↔BRS, and (e) R‒BRS I‒V curves. The asymmetry shape of CF during CRS is due to the depletion of charged oxygen vacancies towards the top or bottom electrodes. The CF growth direction for R‒BRS will be opposite than normal BRS due to the application of reverse bias polarity. 395x455mm (279 x 279 DPI)


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Figure 7. Pulse endurance measurements of the T3 memory device. The memory device shows excellent pulse endurance characteristics for >1000 continuous SET/RESET cycles under BRS, CRS, and R‒BRS operations by applying proper operating conditions. A minimum pulse width of 50 ns is applied during SET/RESET cycles for all cases. 360x278mm (300 x 300 DPI)


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Figure 8. Typical I‒V characteristics of T5 memory device operated at different ICCs. The CRS properties are not observed in the T5 memory device with increasing ICC from ~10 µA to ~420 µA. The memory device shows stable BRS properties at ~10 µA ICC, corresponding SET and RESET voltages are +1 V and -0.4 V respectively. 351x276mm (300 x 300 DPI)


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Figure 9. (a) Excellent unverified pulse endurance characteristics of >7 million cycles are obtained at low ICC of ~10 µA for the T5 memory device. (b) MLC retention tests of the T5 memory device. Both LRS and HRS states can maintain >40 hours at 150oC measurement temperature without any degradation. 363x136mm (300 x 300 DPI)


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Table of Contents/Abstract Graphic 363x146mm (300 x 300 DPI)


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The Role of Ti Buffer Layer Thickness on the Resistive

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