NANO LETTERS
From Si Source Gas Directly to Positioned, Electrically Contacted Si Nanowires: The Self-Assembling “Grow-in-Place” Approach
2004 Vol. 4, No. 11 2085-2089
Yinghui Shan, A. Kaan Kalkan, Chih-Yi Peng, and Stephen J. Fonash* Center for Nanotechnology Education and Utilization, The PennsylVania State UniVersity, UniVersity Park, PennsylVania 16802 Received July 12, 2004; Revised Manuscript Received September 9, 2004
ABSTRACT Our “grow-in-place” approach to Si nanowire devices uses a silicon precursor gas (e.g., SiH4) to directly produce self-assembled, electrically contacted, crystalline Si nanowires without any intervening silicon material formation or collection/positioning steps. The approach uses the vapor−liquid−solid (VLS) growth mechanism and lithographically fabricated, permanent, nanochannel growth templates to control the size, shape, orientation, and positioning of the nanowires and ribbons. These horizontal templates are an integral component of the final devices and provide contacts, interconnects, and passivation/encapsulation. The approach results in self-assembly of the Si nanowires (SiNWs) and nanoribbons (SiNRs) into interconnected devices without any “pick-and-place” or printing steps, thereby avoiding the most serious problems encountered in process control, assembly, contacting, and integration of SiNWs and SiNRs for IC applications. As an initial demonstration of our approach, we have fabricated SiNW and SiNR resistors with built-in electrical contacts and encapsulation and report conductivity measurements.
Semiconducting nanowires have attracted much attention recently owing to their innate submicron feature size and to the potential for exploiting unique fundamental properties. It has been suggested that silicon wires of less than 100 nm in diameter may be used for developing high-speed field effect transistors,1 bio/chemical sensors,2 and light-emitting devices3 with extremely low power consumption.4 This interest has produced a considerable effort focused on nanowire synthesis techniques. Many of the silicon investigations have employed the vapor-liquid-solid (VLS) growth mechanism first introduced by R. S. Wagner et al.5 In VLS Si nanowire (SiNW) growth, metal droplets or slugs (e.g., Au) are generally used to catalyze the decomposition of a Si-containing source gas, to function as a Si reservoir by eutectic liquid formation, and to become supersaturated with Si. With these steps the metal slugs thereby precipitate Si as a solid and build up the SiNW. While the growth of nanowires has received considerable study, a manufacturable approach to the assembly of nanowires into nanoscale devices and circuits, required to enable nanoelectronics and photonics,6 is much less developed. “Pick-and-place” methods have been tried for many types of nanowire materials, including Si, but these methods are very time-consuming and arduous.7-10 Solution and dry printing methods have also been tried and have proven to be most effective for Si when dry printing an aligned block 10.1021/nl048901j CCC: $27.50 Published on Web 10/08/2004
© 2004 American Chemical Society
of SiNWs onto plastic.11,12 In this case, aligned SiNWs are constructed on SOI wafers by traditional silicon fabrication and then dry printed onto a plastic substrate. Alignment and positioning are inherent to this approach, but issues such as SOI wafer cost and effective, reproducible contact welding to pads on the plastic remain. A third method, closest to our grow-in-place approach, uses prepositioned catalysts and electric fields to do the self-assembling/self-positioning.13 However, this method, demonstrated for carbon nanotubes, has no control over the number of tubes at a site and the nanotube alignment varies. Clearly, semiconductor nanowire devices and circuits will not realize their full potential until these various issues are solved and an economically feasible, manufacturable approach to nanowire growth, positioning, number at a position, orientation, contacting, and passivation is developed. This paper presents what we believe to be such an economically feasible, manufacturable approach to producing semiconductor nanowire/nanoribbon devices and circuits, which we term “grow-in-place”. The technique demonstrated here using Si allows the number, positioning, and orientation of nanowires/nanoribbons to be precisely controlled while simultaneously contacting, interconnecting, and passivating the resulting devices. Using a variety of characterization techniques, this paper demonstrates that the grow-in-place approach produces precisely positioned and oriented, size/
Figure 1. Process flow for the fabrication of self-assembling/ positioning Si nanowires/nanoribbons using nanochannel templates. (a) Sacrificial/catalyst metal (Au) lines defined by e-beam lithography and lift-off. (b) Deposition and patterning of the capping layer. (c) Partial etching of the sacrificial metal to form the nanochannels with catalyst in the middle. (d) Si nanowire/nanoribbon growth by the VLS mechanism.
shape-controlled, encapsulated, and electrically contacted crystalline SiNWs and Si nanoribbons (SiNRs). The integrated nanochannel templates basic to the growin-place approach were fabricated by electron-beam lithography14 and a controllable sacrificial metal line etching technique in this demonstration. The use of e-beam lithography allows nanoscale control of the channel dimension, orientation, and interchannel separation, which eventually transform into precise control of nanowire dimensions, orientation, and positioning.15 We stress, however, that the grow-in-place approach is in no way restricted to e-beam lithography. Other nanoscale pattern generation approaches such as nanoimprinting and step and flash also can be used equally well. In this demonstration, the metal line was gold. It functioned as both the sacrificial material defining the enclosed channels and as the catalyst for VLS silicon nanowire growth. The overall process flow is shown in Figure 1. First, open trenches of desired size, number, orientation, and location were patterned by e-beam direct writing on a resist film. The resist was on a silicon oxide layer that was grown thermally on a silicon substrate. Second, titanium (1.5 nm) was e-gun evaporated as the adhesion layer and then gold was thermally evaporated to a desired thickness (e.g., 20 nm) defining the height of the channel and thereby the height of the SiNWs to be grown. Subsequently, the resist film was lifted off to reveal the gold lines on the substrate 2086
(Figure 1a). Third, a silicon nitride capping layer was deposited over the substrate, patterned by photolithography, and selectively dry etched (Figure 1b). Finally, the gold lines buried under silicon nitride were controllably removed by wet etching to form the nanochannels. For this process, a standard Au etchant (type TFA from Transene Company, Inc.) was employed with 100 rpm stirring at room temperature. A typical etching rate for the 200 nm by 20 nm channel was 1.6 µm/min, while the etching rate was observed to decrease with decreasing channel width (e.g.,1.3 µm/min for a 50 nm wide channel). The etching was stopped by immersion in DI water. A relatively short (e.g., 2-10 µm) length of Au (slug) was retained (i.e., not etched away) in the middle of the channels to serve as the VLS catalyst for the SiNW/SiNR growth (Figure 1c). In some cases electrical contacts were built into the channels by contact deposition onto the sacrificial Au prior to nitride deposition and to Au etching. In this way, we made a series of template channels, 100 µm long and 20 nm high with different widths from 20 to 200 nm, each accommodating an Au slug catalyst in the middle. For ease of observation and characterization, the channels of each size were arranged in sets of five. VLS growth resulting in SiNWs and SiNRs was then carried out in a LPCVD reactor at 500 °C and 13 Torr, using a 5% SiH4 diluted in H2 with a total flow rate of 100 sccm16 (Figure 1d). Optical microscope images of grow-in-place SiNWs and SiNRs of various sizes self-assembled by VLS inside our permanent nanochannel templates are shown in Figure 2. These images were taken through the nitride encapsulation/ passivation layer. We have found that, when the Au catalyst slug in a nanochannel is longer than about 10 µm in length, then SiNW/Rs grow at each end of the Au slug (gold is seen as the brighter shade located in the middle of each channel in Figure 2a). For this case, the silicon cannot saturate the whole gold slug, but locally saturates the tips of the gold slugs. The result is two SiNWs, each growing from its own cap. These grow in the nanochannel with one SiNW on each side of a central slug seen in Figure 2a. When the gold slug is shorter (e.g., 2 µm), the whole Au slug becomes saturated with Si and is split into two caps. In this case there is only one growing nanowire and it has a cap located at each end. This leaves no central Au region, as seen in Figure 2b. We studied the size and shape of our SiNWs and SiNRs with atomic force microscopy (AFM) and field emission scanning electron microscopy (FESEM). AFM is very helpful for height determinations of our grown-in-place SiNW/Rs, while it is less accurate in measuring widths due to the tip angle (20°) and radius (15 nm) effects. Using a combination of AFM (Digital Instruments Dimension 3100) height measurements and FESEM (Leo 1530) width measurements, the size and shape of our SiNW/Rs were determined. To perform FESEM and AFM, we had to remove the capping layer. This was done using photolithography and etching. The former was needed to allow selective etching of only half of the capping layer, ensuring that the remaining half remained to immobilize the SiNW/Rs. Subsequently, FESEM and AFM were used to characterize the exposed SiNW/Rs. Nano Lett., Vol. 4, No. 11, 2004
Figure 2. Optical microscope images and corresponding schematics for SiNW/Rs grown inside nanochannel templates by our grow-inplace VLS approach. Growth patterns are shown for the (a) long Au slug case and (b) the short Au slug case discussed in the text.
Figure 3a shows the FESEM overview image of the SiNW/R groupings from 200 to 20 nm in width after capping layer removal. As in Figure 2, the brighter regions are gold slugs and the SiNW/Rs look darker. The Au slugs in narrower channels are seen to be slightly longer. This may be attributed to the slower etching rate of the Au sacrificial/catalyst material due to the restricted diffusion of reactants and products during the wet etching process. Figures 3b and c show the 200 and 20 nm width SiNRs and SiNWs, respectively, in high magnification. From this FESEM work, the width for these ribbons and wires was measured to be 250 and 35 nm, respectively. Figures 3d and e depict the AFM height profiles for the 200 and 20 nm width ribbon and wire groups, respectively. As is seen, the height of the ribbons/wires is about 25 nm and is independent of the width, as desired. Hence, both nanoribbons and wires of carefully controlled cross sectional dimensions are obtainable by our approach. We believe that, since the growth front is liquid in the VLS method, it fills in the complete cross section of the nanochannel during growth, thereby ensuring that the precipitating Si inherits the exact shape of the nanochannel volume. For the same reason, the interface between the grown Si and the built-in contacts should also be very conformal, minimizing the contact resistance as is observed and discussed below. The crystallinity of the SiNW/Rs was investigated by Raman spectroscopy. Raman spectra were collected with a double stage Dilor XY spectrometer equipped with a confocal microscope (Olympus BH-2) and a Princeton Instruments Nano Lett., Vol. 4, No. 11, 2004
model LN/CCD-1024 TKB detector. The laser excitation of 514.5 nm and 6 mW was focused in the backscattering geometry using an Olympus MSPlan 100×, 0.95 NA microscope objective to a spot size of approximately 2 µm. To optically isolate the underlying Si substrate, an additional process step was introduced into Figure 1 for the samples used for Raman. This consisted of coating a reflective and opaque nickel layer (200 nm) on the silicon substrate prior to the fabrication of the channel templates. Figure 4 shows the Raman shift spectra for our various width SiNW/Rs as well as for a 〈111〉 single-crystal Si wafer for comparison. The Raman peak located within 518-521 cm-1 for our SiNW/Rs is assigned to the first order optical phonon (at the Brilliouin zone center) scattering in a Si lattice and identifies our SiNW/Rs as crystalline. However, this peak is slightly downshifted and asymmetrically broadened when compared to that in bulk single crystalline Si, as it can be seen in Figure 4. In agreement with Piscanec et al.,17 we attribute this downshift and asymmetric broadening of the Raman peak to intense local heating by the laser excitation and not to quantum confinement effects. As the “control” data of Figure 4 show, no Raman peak was obtained when the laser beam was focused outside nanochannel regions (i.e., on the silicon nitride capping layer). This ensures that the Raman signal shown in Figure 4 is not attributable to the underlying Si wafer or any residual Si deposit on the capping layer. To demonstrate the potential of our grow-in-place approach for the self-assembling of interconnected devices and 2087
Figure 3. (a) FESEM image of SiNW/R group series having widths from 200 nm (left) to 20 nm (right). (b) FESEM image of a 200 nm width nanoribbon group. (c) FESEM image of a 20 nm width nanowire group. (d) AFM height profile of a 200 nm width SiNR group. (e) AFM height profile of a 20 nm width SiNW group. (f) AFM height profile of a single ribbon in the 200 nm width nanoribbon group.
circuits, simple nanowire/ribbon resistor structures were fabricated by building electrical contacts inside the nanochannels. As discussed earlier, these contacts were built-in using a deposition/photolithography step prior to the capping layer deposition. Figure 5 shows the current-voltage (I-V) characteristics of a 200 nm wide, 20 nm high SiNR obtained using such built-in contacts with 20 µm and 40 µm spacings. These data, which are seen to scale with contact spacing, show the SiNR has a conductivity of ∼2 × 10-4 S/cm and that contact resistance is not an issue. The SiNR conductivity value implies our grow-in-place process is capable of 2088
achieving low Au doping. These same measurements were performed for 20 nm high nanowires with widths as narrow as 30 nm. We obtained linear I-V behavior as seen in Figure 5 in all these cases. Also seen in Figure 5, the I-V characteristics of an empty channel (prior to growth) in these measurements showed only noise of the measurement system and no I dependence on V. Therefore, the currents measured from our SiNWs/SiNRs are not attributable to any leakage through the walls of our nanochannels or to noise, but they actually arise from the transport through the SiNWs/ SiNRs. Nano Lett., Vol. 4, No. 11, 2004
nanowires and nanoribbons with predetermined locations and orientations and with desired sizes and shapes. In addition, contacts and interconnects, as well as device encapsulation/ passivation, are built into the templates. We believe this grow-in-place approach points the way to a manufacturable and high-throughput methodology for fabricating nanowire/ ribbon devices which self-assemble and self-position into integrated circuits.
Figure 4. Raman spectra obtained for a single-crystal silicon wafer, various size SiNW/Rs (widths from 30 to 200 nm), and the control region (as described in the text).
Acknowledgment. We are grateful to Joan Redwing for allowing us to use her LPCVD reactor for growing our nanowires/nanoribbons. We also thank John Badding and Bryan Jackson for making their Raman spectrometer available to us. This research made extensive use of the facilities of the Penn State site of the National Science Foundation (NSF) National Nanofabrication Infrastructure Network. The work was supported in part by NSF Grant No. DMI-0210229. References
Figure 5. I-V characteristics of a single 200 nm wide, 20 nm high channel without the SiNR (empty, 20 µm contact spacing) and with a grown SiNR using contacts with 20 µm (b) and 40 µm (2) spacings.
This paper demonstrates for the first time that it is possible to go directly from a silicon precursor gas (e.g., SiH4) to self-assembled/self-positioned crystalline Si devices without any intervening silicon material formation or collection/ positioning steps. The growth nanochannels, which are key to our approach, are horizontally arrayed and become a permanent part of the device structure. We show that the nanochannel templates can enable the VLS growth of
Nano Lett., Vol. 4, No. 11, 2004
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