Transformable Functional Nanoscale Building Blocks with Wafer

Jan 21, 2011 - Department of Electrical Engineering, KAIST, 335 Gwahangno, Yuseong-gu, Daejeon ... Copyright © 2011 American Chemical Society ... (12...
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Transformable Functional Nanoscale Building Blocks with Wafer-Scale Silicon Nanowires Sung-Jin Choi, Jae-Hyuk Ahn, Jin-Woo Han, Myeong-Lok Seol, Dong-Il Moon, Sungho Kim, and Yang-Kyu Choi* Department of Electrical Engineering, KAIST, 335 Gwahangno, Yuseong-gu, Daejeon 305-701, Republic of Korea

bS Supporting Information ABSTRACT: Through the fusion of electrostatics and mechanical dynamics, we demonstrate a transformable silicon nanowire (SiNW) field effect transistor (FET) through a wafer-scale topdown approach. By felicitously taking advantage of the proposed electrostatic SiNW-FET with mechanically movable SiNWs, all essential logic gates, including address decoders, can be monolithically integrated into a single device. The unification of various functional devices, such as pn-diodes, FETs, logic gates, and address decoders, can therefore eliminate the complex fabrication issues associated with nanoscale integration. These results represent a step toward the creation of multifunctional and flexible nanoelectronics. KEYWORDS: Silicon nanowire, field effect transistor, logic gates, address decoders, nanoelectromechanical systems

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creating high-quality electrical contacts remains a challenge. As noted in previous reports regarding semiconductor nanowire logic gates,12,13 they are often composed of significantly different structures based on crossed nanowires, such as pn-diodes and FETs; hence, the realization of cointegrated nanoelectronic circuits is difficult and the throughput of such devices raises serious questions regarding their configuration and architecture. One important advantage of using top-down approaches is in the ability to control the position of functional device arrays precisely. Silicon technologies in top-down approaches are advantageous for other types of semiconductor technology due to the considerable research pertaining to the use of silicon and the many silicon-related materials and mature nanofabrication technologies available. As a solution to the questions posed above, we now report the “transformable” functional nanoscale devices created by the fusion of electrostatically operating silicon nanowires (SiNWs) building blocks and mechanically movable SiNWs using a wafer-scale top-down approach. This fused device has several noteworthy aspects. The properties are changeable and reconfigurable on the same SiNW-FET (i) by moving or bending the SiNWs and (ii) by modifying the threshold voltage. In other words, functional operations (i.e., logic gates: NOT; OR; AND; NOR; NAND gates and address decoders) with substantial gains can be implemented on the same single SiNWFET through mechanical modifications. Hence, our approach introduces the nanoelectronics to wafer-scale mass production

he rapid miniaturization of electronic devices has been a key force in driving scientific and economic progress over the past 40 years in microelectronics. Nanoscale-electronics (nanoelectronics) is now a closely watched upcoming frontier.1-6 One-dimensional structures such as nanowires and carbon nanotubes, created through bottom-up approaches, are the ideal building blocks for nanoelectronics given their ability to function as both devices and wires.7,8 Previous methods regarding the formation of functional nanoscale building blocks, particularly those involving semiconductor nanowires, have focused mainly on bottom-up approaches that allow control of the carrier type (electrons in n-type; holes in p-type), the carrier concentration, and the wire diameter (near-atomic-scale precision) during the growth phase or during chemical synthesis. With bottom-up approaches, semiconductor nanowires have been used as building blocks in the assembly of various types of nanodevices, including field effect transistors (FETs),8-17 pn-diodes,10-13 bipolar junction transistors (BJTs),11 and logic gates.12,13 Moreover, functional nanoscale electronic devices in the form of crossed nanowire pn-diodes and FETs have enabled bottomup approaches to be used in the assembly of nanoelectronic circuits that can ultimately be integrated with memory arrays for read/write operations or can be used to manufacture stand-alone processors. However, currently, manufacturing methods relying on bottom-up approaches do not provide controllability that is precise enough to integrate high-density ordered arrays. Moreover, a specific transfer technique is typically required in the assembly of devices on a separate substrate, although bottom-up synthesized semiconductor nanowire devices have excellent electronics transport properties. Moreover, a reproducible means of r 2011 American Chemical Society

Received: December 3, 2010 Revised: December 27, 2010 Published: January 21, 2011 854

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Figure 1. Transformable functional SiNW-FETs from the top-down approaches. (A) Schematic illustrating the proposed SiNW-FET. The SiNW is in contact with two electrodes, the S and D, to measure the SiNW conductance. Two separated gates (G1, G2) sit vertically on the SiNW and face each other. (B) Conductance versus tied gate voltage (VG = VG1 = VG2) of the transformable SiNW p-FET and n-FET devices. The back-gate (silicon substrate) is grounded during all measurements. (Inset) An SEM image of a SiNW-FET. Scale bar, 300 nm. (C) Conductance versus the independent gate voltage (VG1 and VG2) of a transformable SiNW p-FET and n-FET devices with a SiNW width of 50 nm.

and thereby represents a step closer to the creation of multifunctional and flexible nanoelectronics. The proposed transformable functional nanoscale device is very similar to a double-gate FinFET18 except for the separated gate consisting of the primary gate (gate1, G1) and the secondary gate (gate2, G2). They sit vertically on the sidewall of the SiNW and face each other through a chemical-mechanical polishing (CMP) process (Figure 1A and Supporting Information Figure S1). Conductance modulated by the tied gate voltage (i.e., VG = VG1 = VG2) (Figure 1B) shows the complementary switching behavior involving an n-channel FET (n-FET) and a p-channel FET (p-FET). Substantial gate controllability is demonstrated as the two gates give a strong response to the SiNW channel. Fieldemission scanning electron microscopy (FESEM) was used to image the proposed device (Figure 1B, inset). As symmetric/ asymmetric biases can be applied to the two separated gates, SiNW conductance is also controlled independently (Figure 1C). The ability to control the SiNW conductance independently enables the SiNW-FET itself to be used as a logic gate. To demonstrate the flexibility of the proposed SiNW-FET elements, we investigated a single p-FET as a logic gate. A two-input NAND logic gate can be realized using a single SiNW p-FET with two separated gates (i.e., G1 and G2) as inputs and a highly pþ-doped drain region as the output (Figure 2A). The highly pþ-doped source region is biased at 5 V (VDD), and the output node is connected to an off-chip bias resistor (300 MΩ). As a result, the pull-up and -down networks are comprised of the single SiNW p-FET and the resistor. In this device, the output depends on the resistance ratio between the conductance of the SiNW and the constant exterior resistor. A logic 1 state is observed when

Figure 2. (A) Symbol of the electronic circuit for electrical measurement of the NAND logic gate with a single SiNW p-FET. (B) The output voltage of the NAND logic gate with a single SiNW p-FET versus four possible logic address level inputs: (0, 0), (0, 1), (1, 0), and (1, 1), where the logic 0 input is 0 V and the logic 1 input is 5 V (identical to that shown in Figure 2). (Inset) The VOUT-VIN relationship. The solid (dashed) line shows the VOUT-VIN relationship when the other input is logic 1 (0).

either one or both inputs are low. In this case, the p-FET is on and the channel resistances are much lower than that of the constant resistor. As a result, most of the voltage drops across the constant resistor. A logic 0 state can only be achieved when the p-FET is off, that is, when both inputs are high. The output-input (VOUT-VIN) (VG1) relationship (Figure 2B, inset) shows a constant high VOUT when the other input is set low. Analysis of the data demonstrates that these two-input NAND gates routinely exhibit gains larger than five, which can be increased with a thinner gate dielectric layer. Moreover, this type of single 855

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Figure 3. Transformation of a SiNW-FET as pn-diodes. (A) Schematic illustrating the transformation from a SiNW-FET to pn-diodes and SEM images before and after the transformation of a SiNW-FET with a width of 50 nm. A SiNW p-FET (pþ-S/D, n-SiNW, and nþ-poly-Si) was used in this study. The initial gate dielectric (SiO2) of 20 nm is etched using a BOE solution, and the n-type SiNW adheres to the nþ poly-Si through an applied bias to the gate (G1). (B) TEM images before and after transformation of a SiNW-FET with a width of 50 nm. (C) The gate current (IG1) versus the gate voltage (VG1) behavior in the transformation from a SiNW-FET to pn-diodes. (Inset) Symbol of the electronic circuit in the OR logic gate. (D) Current (IS, ID) versus voltage (VS, VD) characteristics of transformed pn-diodes embedded in a SiNW-FET. (E) The output voltage of the OR logic gate versus the four possible logic address level inputs. (Inset) VOUT-VIN, in which the solid (dashed) line corresponds to VOUT-VIN when the other input is 0 (1).

SiNW-FET logic circuit can reduce the chip area, leakage current, and active power dissipation by reducing the number of transistors. We also note that the combination of a single n-FET and the constant resistor produces a NOR gate with a high gain.19 Basically, the conducting path along the source-channeldrain in the FET structure cannot be turned on owing to the embedded back-to-back connected diodes,20 i.e. nþ(source)p(channel)-nþ(drain) for the n-FET and pþ(source)n(channel)-pþ(drain) for the p-FET. Two back-to-back connected diodes are only used for the formation of the potential barriers in the initial state of the FETs.21 Our transformable SiNW-FET was created based on the goal of independently utilizing embedded diodes in a single SiNW-FET. The SiNW formulated in this study was initially formed as a core/shell Si/ SiO2 structure in which the oxide shell serves to control the thickness of the gate dielectric, later to be subsequently removed through wet-etching of the SiO2. Thus, the solid-state gate dielectric is replaced by an air-state nanogap (Supporting Information Figure S2). Negative voltage is then applied to one of the two gates (G1 or G2) for a p-FET SiNW-FET. The induced electrostatic force therefore attracts the SiNW. If the electrostatic force is larger than the elastic restoring force of the SiNW, the

SiNW can mechanically adhere to the negatively biased gate (Figure 3A). High-resolution transmission electron microscopy (HRTEM) images do not show evidence of voids and asperities in the contacted interface (Figure 3B). At an air-gap thickness of approximately 20 nm, the voltage of the adhesion of the SiNW is relatively high (near 19 V) (Figure 3C). At the moment of adhesion, high forwarded diode current flows between the gate and the source/drain (S/D). Once the SiNW comes into contact with the gate, the state can be sustained due to the adhesion force that arises at the contact interface (i.e., Van Der Waals forces).22 Because the gate materials consist of in situ nþ-doped polycrystalline silicon (poly-Si) in this study, the contact between the SiNW channel (n-type for a p-FET) and the gate is easily produced. Hence, a pn-diode is created between the n-SiNW channel when it is in contact with the nþ-doped poly-Si and pþ-source or -drain. Current-voltage measurements show that the pþ-source/n-SiNW or pþ-drain/n-SiNW diode exhibits current rectification characteristics with a typical turn-on voltage of approximately 1 V (Figure 3D). The transformed nanoscale pn-diodes with reproducible and predictable electrical properties enable exploration of the assembly and properties of integrated pn-junction arrays in logic gates. Therefore, a two-input OR gate 856

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Figure 4. Transformation of a SiNW-FET as an address decoder unit. (A) Schematic illustrating the manipulation of the gate dielectric thickness, which can be used to define an address code, and TEM images after modification. The TEM images on the right are a magnification of the red square region in the TEM image on the left. A SiNW n-FET with a width of 50 nm was used in this study. After etching the SiO2 (gate dielectric), the exposed SiNW surfaces are reoxidized at a thickness of 3 nm. The oxidized SiNW then adheres to the gate (VG1) by the biasing of the gate electrode. (B) Conductance versus the gate voltage of a single SiNW-FET before (triangles) and after (squares) modification of the gate dielectric. (C) The actuation voltage (Vactuation) to modify the SiNW-FETs versus the controllable parameters (geometrical width and length of the SiNWs) for the transformable SiNWFETs. (D) Threshold voltage distribution of the transformable SiNW-FETs. The green area indicates the SiNW-FETs after modification, and the magenta area indicates the high-threshold voltage before modification. (Inset) Histogram of the threshold voltage for over 70 as-modified SiNW-FETs showing a narrow distribution around 2 V. High threshold voltage SiNW-FETs with an air-state gap as the gate dielectric show a broad distribution because the data was taken from various SiNW-FETs with widths ranging from 50 to 80 nm and lengths of 700 nm to 1 μm. (E) Real-time monitoring of the gate voltage inputs (inset) and signal output in SiNW-FETs with and without modification. The supply voltage is 0.05 V and load resistance is 1 MΩ.

is easily realized using two diodes embedded in a transformed single SiNW-FET with two highly pþ-doped S/D as inputs and the gate (nþ poly-Si) as the output. In this device, the output is low (logic 0) when both input voltages are low (0 V), and the output is high (logic 1) when either or both of the input voltages is/are high (Figure 3E). It is noteworthy that a high input corresponds to the forward bias of the selected pn-junction. The output-input (VOUT-VINPUT) voltage response (Figure 3E, inset) shows that VOUT increases linearly with VINPUT when one input is set low (0 V), except for the region near 0 V.23 The VOUT-VINPUT data also show a nearly constant high output when the second input is set high (5 V). It is important to note that AND gates can be implemented using an n-FET with a pþ poly-Si gate.24 However, these OR and AND logic gates cannot exhibit a voltage gain; they will show a gain if implemented by connecting the SiNW FET inverter to the output node (Supporting Information Figure S3). The development of strategies of addressing the arrays of nanoscale devices is also important in the implementation of integrated nanosystems such as biological sensor arrays and nanocomputers.15,25-27 Our transformable SiNW-FET can function

as an address decoder by modification of the gate dielectric, in which mechanically changing (or modifying) the thickness of the gate dielectric can serve to define an address code that enables the input lines (gates) to turn on and off specific output lines with the inherent gain of the SiNW-FET. We investigated these types of decoder functions based on a single-gate n-FET (i.e., using G1 or G2). After the etching SiO2 (i.e., the gate dielectric), reoxidation was performed to form a thin gate dielectric (3 nm) on the SiNW and poly-Si surface. Positive gate voltage was then applied, allowing the SiNW to adhere mechanically to the biased gate electrode (Figure 4A, top). HRTEM images show the uniformly distributed gate dielectric layer after adhesion (showing no evidence of voids and asperities) (Figure 4A, bottom). Typical electrical transport data (Figure 4B) recorded on a single SiNWFET before and after modification demonstrates the substantial effect that the modification has on the gate response.28 This suggests that this type of modification can be used to differentiate specific SiNW FET elements in an array to produce an address decoder circuit. The actuation voltage to modify the SiNW-FETs can be reduced as the SiNW becomes narrower and longer due to its low spring force (Figure 4C). Before modification (i.e., an 857

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Nano Letters air-state nanogap as a gate dielectric), the SiNW-FET exhibited a threshold voltage that exceeded 9 V. After modification, however, this threshold shifted to approximately 2 V. Measurements made on more than 70 individual SiNW-FETs show that this large threshold voltage shift is reproducible. Specifically, a histogram (Figure 4D) summarizing the threshold voltages before and after modification of the SiNW-FET with the same geometrical parameters yielded average values of 9.2 and 2.3 V, respectively. In addition, the threshold voltage shift was found to be stable for at least a few months even in atmosphere (Supporting Information Figure S4). We also found that modified SiNW-FETs could be turned on and off at least hundreds of times without significant hysteresis behavior even at air-environment. Therefore, it is possible to turn on specific cross points that are modified in selected SiNW-FETs (1-hot code) by electrical modification of the permittivity and thickness of the gate dielectric. The response on a single SiNW-FET with and without modification of the gate dielectric assures this behavior (Figure 4E). In summary, through mechanical modifications, the proposed predictable and reproducible SiNW-FETs demonstrated various transformable functions, such as critical logic gates and address decoders. This paves the way toward the creation of multifaceted and flexible nanoelectronics with the aid of wafer-scale topdown approaches that offer precise control of the carrier type, concentration, and position. Moreover, the unification of versatile functional devices, such as pn-diodes, FETs, and their logic gates, can eliminate the complex fabrication issues involved in monolithic nanoscale integration. We also note that the transformable SiNW-FET can function as a memory device through selectively programmable pn-diodes and mechanically flip-flopped SiNWs switches due to their long sustainability. Their attaching and detaching operations can be achieved by inducing the electrostatic energy to the primary (G1) and secondary electrodes (G2). Although our studies have only focused on transformable logic gates and address decoders, further studies in this area can easily realize field-programmable nanowire interconnections (FPNIs) and field-programmable gate arrays (FPGAs).

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’ REFERENCES (1) Goldhaber-Gordon, D.; Montemerlo, M. S.; Love, J. C.; Opiteck, G. J.; Ellenbogen, J. C. Proc. IEEE 1997, 85, 521–540. (2) Taur, Y.; Buchanan, D. A.; Chen, W.; Frank, D. J.; Ismail, K. E.; Lo, S.-H.; Sai-Halasz, G. A.; Viswanathan, R. G.; Wann, H.-J. C.; Wind, S. J.; Wong, H.-S. Proc. IEEE 1997, 85, 486–504. (3) Ellenbogen, J. C.; Love, J. C. Proc. IEEE 2000, 88, 386–426. (4) Peercy, P. S. Nature 2000, 406, 1023–1026. (5) Wada, Y. Proc. IEEE 2001, 89, 1147–1171. (6) Tseng, G. Y.; Ellenbogen, J. C. Science 2001, 294, 1293–1294. (7) Hu, J.; Odom, T. W.; Lieber, C. M. Acc. Chem. Res. 1999, 32, 435–445. (8) Dekker, C. Phys. Today 1999, 52, 22–28. (9) Cui, Y.; Duan, X.; Hu, J.; Lieber, C. M. J. Phys. Chem. B 2000, 104, 5213–5216. (10) Duan, X.; Huang, Y.; Cui, Y.; Wang, J.; Lieber, C. M. Nature 2001, 409, 66–69. (11) Cui, Y.; Lieber, C. M. Science 2001, 291, 851–853. (12) Huang, Y.; Duan, X.; Cui, Y.; Lauhon, L. J.; Kim, K.-H.; Lieber, C. M. Science 2001, 294, 1313–1317. (13) Kim, D. R.; Lee, C. H.; Zheng, X. Nano Lett. 2010, 10, 1050– 1054. (14) Duan, X.; Niu, C.; Sahi, J.; Chen, J.; Parce, J. W.; Empedocles, S.; Goldman, J. L. Nature 2003, 425, 274–278. (15) Zhong, Z.; Wang, D.; Cui, Y.; Bockrath, M. W.; Lieber, C. M. Science 2003, 302, 1377–1379. (16) Ng, H. T.; Han, J.; Yamada, T.; Nguyen, P.; Chen, Y. P.; Meyyappan, M. Nano Lett. 2004, 4, 1247–1252. (17) Javey, A.; Nam, S.; Friedman, R. S.; Yan, H.; Lieber, C. M. Nano Lett. 2007, 7, 773–777. (18) Choi, Y. -K.; King, T. -J.; Hu, C. IEEE Electron Device Lett. 2002, 23, 25–27. (19) By implementing an n-FET (i.e., highly nþ-doped source/drain (S/D) and p-SiNW as a channel) as a pull-down network on the proposed SiNW-FET, a NOR logic gate can be readily formed, similar to a NAND logic gate. (20) Sze, S. M. Physics of Semiconductor Devices, 3rd ed.; Willey: New York, 2007; pp 293-298. (21) The pn-diodes are generally used for the formation of potential barriers between the S/D and channel in a FET. However, this structure can be changed through the use of a structure without S/D junctions. Whereas previous work using crossed nanowire FETs only utilized highly doped SiNWs without the formation of S/D junctions, in the present study highly doped S/D junctions were formed to employ builtin diodes. (22) Rueckes, T.; Kim, K.; Joselevich, E.; Tseng, G. Y.; Cheung, C.L.; Lieber, C. M. Science 2000, 289, 94–97. (23) This low response region is due to the finite turn-on voltage of the p-n junctions and produces a logic output that is typically 0.4 to 0.2 V less than the input voltage. A small reduction in VOUT does not affect the operation of our logic gates because the low turn-on voltage contributions are reproducible and can be readily accounted for in defining the 0 and 1 states. (24) An AND logic gate can also be implemented on the transformable SiNW-FET using an n-FET (i.e., highly doped nþ-S/D and p-SiNW) with pþ poly-Si gates. Therefore, previous pull-up networks in complementary metal oxide semiconductor (CMOS) electronics can be transformed to OR logic gates (Figure 2), and pull-down networks can be transformed to AND logic gates. Also see Supporting Information, Figure S2. (25) DeHon, A. IEEE Trans. Nanotechnol. 2003, 2, 23–32. (26) Kong, J.; Franklin, N. R.; Zhou, C.; Chapline, M. G.; Peng, S.; Cho, K.; Dai, H. Science 2000, 287, 622–625. (27) Cui, Y.; Wei, Q.; Park, H.; Lieber, C. M. Science 2001, 293, 1289–1292. (28) The large threshold voltage difference is wholly due to the significantly changed thickness and material of the gate dielectric. The

’ ASSOCIATED CONTENT

bS

Supporting Information. Detailed fabrication process of SiNW-FETs, an experimental section describing modification of gate dielectric layers for transformable operations, further applications of transformable logic gates, and measured sustainability of the modified SiNW-FETs. This material is available free of charge via the Internet at http://pubs.acs.org.

’ AUTHOR INFORMATION Corresponding Author

*E-mail: [email protected]. Tel: 82-42-350-3477. Fax: 82-42350-8565.

’ ACKNOWLEDGMENT This research was supported by the National Research Foundation of Korea funded by the Korean government (Grant 2009-0083079) and by the Nano R&D program through the National Research Foundation of Korea funded by the Ministry of Education, Science, and Technology (Grant 2009-0082583). 858

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equivalent thickness of the gate dielectric before modification (i.e., 3 nm SiO2 on the SiNW surface and 3 nm SiO2 on the poly-Si gate with a 24 nm air-gap) is 62 nm when considering the permittivity of SiO2 and air. However, after modification, the equivalent thickness of the gate dielectric is close to 6 nm. This difference in the thickness and permittivity of the gate dielectric layer can affect the gate capacitance value and in turn, significantly change the threshold voltage.

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