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Wafer-Scale Integration of Highly Uniform and Scalable MoS2 Transistors Yonghun Kim, Ah Ra Kim, Guoqing Zhao, Sun Young Choi, Soo Cheol Kang, Sung Kwan Lim, Kang Eun Lee, Jucheol Park, Byoung Hun Lee, Myung Gwan Hahm, Dong-Ho Kim, Jungheum Yun, Kyu-Hwan Lee, and Byungjin Cho ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b10676 • Publication Date (Web): 04 Oct 2017 Downloaded from http://pubs.acs.org on October 5, 2017

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ACS Applied Materials & Interfaces

Wafer-Scale Integration of Highly Uniform and Scalable MoS2 Transistors

Yonghun Kim,1 Ah Ra Kim,1 Guoqing Zhao,1 Sun Young Choi,1 Soo Cheol Kang,2 Sung Kwan Lim,2 Kang Eun Lee,3 Jucheol Park,4 Byoung Hun Lee,2 Myung Gwan Hahm,5 Dong-Ho Kim,1 Jungheum Yun,1* Kyu Hwan Lee,6* Byungjin Cho7* 1

Department of Advanced Functional Thin Films, Surface Technology Division, 3Composites

Research Division, and 6Electrochemistry Department, Surface Technology Division, Korea Institute of Materials Science (KIMS), 797 Changwondaero, Sungsan-gu, Changwon, Gyeongnam 51508, Republic of Korea 2

School of Materials Science and Engineering, Gwanju Institute of Science and Technology

(GIST), 261 Cheomdan-gwangiro, Buk-Gu, Gwangju 61005, Republic of Korea 4

Structure Analysis Group, Gyeongbuk Science and Technology Promotion Center, Future

Strategy Research Institute, 17 Cheomdangieop 1-ro, Sangdong-myeon, Gumi, Gyeongbuk 39171, Republic of Korea 5

Department of Materials Science and Engineering, Inha University, 100 Inharo, Nam-Gu,

Incheon 22212, Republic of Korea 7

Department of Advanced Materials Engineering, Chungbuk National University, 1 Chungdae-ro,

Seowon-gu, Cheongju, Chungbuk 28644, Republic of Korea

KEYWORDS: Molybdenum disulfide (MoS2), MoO3, radio frequency sputtering, transistors, intrinsic mobility

1 Environment ACS Paragon Plus


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ABSTRACT

Molybdenum disulfide with atomic-scale flatness has application potential in high speed and low power logic devices, owing to its scalability and intrinsic high-mobility. However, to realize viable technologies based on two-dimensional materials, techniques that enable their large-area growth with high quality and uniformity on wafer-scale is a pre-requisite. Here, we provide a route toward highly uniform growth of a wafer-scale, four-layered MoS2 film on a 2-inch substrate via a sequential process consisting of the deposition of a molybdenum trioxide precursor film by sputtering followed by post-sulfurization using a chemical vapor deposition process. Spatial spectroscopic analyses by Raman and PL mapping validated that the assynthesized MoS2 thin films exhibit high uniformity on a 2-inch sapphire substrate. The highly uniform MoS2 layers allow a successful integration of devices based on ~1200 MoS2 transistor arrays with a yield of 95% because of their extreme homogeneity on Si wafers. Moreover, a pulse electrical measurement technique enabled investigation of the inherent physical properties of the atomically thin MoS2 layers by minimizing the charge trapping effect. Such a facile synthesis method can be possibly applied to other 2D transition metal dichalcogenides, to ultimately realize the chip integration of device architectures with all 2D-layered building blocks.


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INTRODUCTION Layered two-dimensional (2D) atomic crystals such as semiconducting transition metal dichalcogenides , phosphorene, and black phosphorus have been explored extensively, owing to their unusual electronic and optical properties.1–8 Such layered materials have sparked a paradigm shift in the area of semiconductors. Particularly, molybdenum disulfide has been considered one of the fascinating semiconducting materials for next-generation nanoelectronics, owing to low power consumption,9,10 high effective mobility,11–13 excellent switching capability,14,15 and a tunable band gap.16,17 Most recently, the state-of-art MoS2 transistors with 1 nm gate lengths have shown the possibility of realizing transistors beyond the projected Si scaling limit of an approximately 5 nm gate length.18 In fact, the electrical characteristic of a transistor based on a MoS2 monolayer grown by chemical vapor deposition (CVD) suggested that the ballistic charge transport of MoS2 could exceed the performance of a Si channel, which meets the next requirement of the international technology roadmap for semiconductors.19 Despite the great potential of MoS2 as an extremely scaled semiconducting channel material, feasible implementation of the integrated circuit has been restricted owing to lack of large-area growth methods to guarantee high quality and uniformity. Recently, many efforts have been dedicated to the fabrication of large-area MoS2 thin films via diverse physical and chemical synthesis approaches. For instance, liquid exfoliation or the hydrothermal synthesis are cost-effective owing to solution-based processing.20,21 However, it is unlikely to achieve high crystal quality in MoS2 films fabricated by such methods. Alternatively, a metal organic chemical vapor deposition technique using gas-phase precursors such as Mo(CO)6, W(CO)6, and (C2H5)2S has been introduced and the synthesized MoS2 transistors exhibited homogeneous electrical properties with high mobilities.22,23. On the other hand, a 2D



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synthesis process using atomic layer deposition (ALD) has been developed.24–26 This could be a promising growth approach for 2D materials in terms of layer controllability and reproducibility, but the performance of devices based on ALD-grown films has been unsatisfactory in electronic applications such as transistor switching devices. Magnetron sputtering was reported to be able to synthesize p-type MoS2 atomic layers on a sapphire substrate with size less than 1 cm.27 Synthesis method for n-type MoS2 transistor, patterned by electron beam lithography, was also invented using a two-step process including reactive RF sputtering and then sulfurization.28 CVD techniques have been the most popular owing to less complex processing parameters and better crystal quality of the films grown on large scales.29,30 Synthesis of wafer-scale MoS2 using a gas phase sulfur precursor and predeposited Mo metal atoms was available even if mean mobility value of the transistor devices was slightly low of being ~0.07 cm2/Vs.31 2 inch wafer-scale MoS2 thin layers could be obtained using thermally evaporated MoO3 thin films as a starting material followed by a two-step thermal annealing process.32 Indeed, a reliable scalability and uniformity of transistor devices is prerequisite in terms of realizing a 2D integrated circuit. However, practical implementation of an integrated 2D circuit component using reproducible 2D synthesis has not been limited until now. In this work, we propose a simple and reliable technique for the large-area growth of MoS2 layered thin films on 2-inch wafers. Our approach involves a simple sequence of processes: Molybdenum trioxide (MoO3) is pre-deposited on a sapphire substrate via radio frequency (RF) sputtering followed by sulfurization via CVD. This growth technique could yield wafer-scale MoS2 thin films such that an array of approximately 1200 MoS2 transistors occupying 2-inch active area of a 4-inch silicon wafer could function well, with excellent electrical characteristics (a device yield of ~95%, average mobility of 0.8 ± 0.2 cm2/Vs, and log on/off ratio of 4.3 ± 0.7).


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The intrinsic mobility obtained from pulsed current measurements is 4.5 cm2/Vs, which also provided an insight of charge trapping phenomenon. Wafer-scale integration of the highly uniform transistor array device would be essential for 2D circuit platform consisting of diverse atomic-scale

components,

enabling

applications

beyond

complementary

metal-oxide-

semiconductors.

RESULTS AND DISCUSSION Figure 1a shows the optical image of the MoS2 field effect transistor (FET) array device (active area of 2 inch) integrated on a 4-inch SiO2/Si wafer. The MoS2 FET array devices with different channel lengths (10 to 50 µm) were fabricated on the wafer. A representative MoS2 FET device with 50 µm channel length and 100 µm width is shown in the enlarged image of Figure 1a. As illustrated in Figure 1b, the MoS2 FET array devices were fabricated by a conventional semiconductor process. First, a sapphire substrate was cleaned (step 1); then a ~3-nm-thick MoO3 precursor film was deposited on the pre-cleaned sapphire wafer by RF sputtering deposition (step 2). The MoO3 film was so flat (see Figure S1 in supporting information (SI)), which would enable atomically flat MoS2 2D film. Subsequently, the MoS2 layered film was obtained by CVD (step 3). More specifically, the pre-deposited MoO3 samples were placed in the center of the furnace, and sulfur powder was loaded on the flange heater near the furnace inlet. The temperatures of the furnace and flange heater were increased by ∼900 and ∼200 °C, respectively, under the flow of an Ar/H2 (85/15%) gas mixture. The MoO3 film was sulfurized with vapors sublimated from sulfur powder, resulting in the formation of a layered MoS2 films. The as-synthesized MoS2 film was transferred from the sapphire substrates onto SiO2/Si substrates using a conventional PMMA (Polymethyl methacrylate)-assisted transfer method (step



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4) and then patterned for active channel region of the transistor array devices via reactive ion etching (step 5). Au/Cr (50/3 nm) metallic electrodes were fabricated by a sequential lithography process, including photolithography, metal deposition, and a lift-off process (step 6). Finally, we achieved the MoS2 FET array devices integrated on SiO2/Si wafers. In particular, we selected a simple global back-gating transistor architecture to modulate the current flowing through the MoS2 channel. The crystalline structure of the vertical cross-section of the MoS2 film was characterized by transmission electron microscopy. The as-synthesized MoS2 multilayers on sapphire consisted of four layers (Figure 2a). The layers appeared atomically flat without any curvature of the layered structure. Figure 2b shows the X-ray photoelectron spectroscopy (XPS) spectrum of MoS2 with a doublet corresponding to Mo 3d3/2 (232.8 eV), Mo 3d5/2 (229.6 eV), and S 2s (226.9 eV) orbits. Additionally, a doublet for S 2p3/2 and S 2p1/2 was observed at 162.5 and 163.7 eV, respectively.33 Transmission electron microscopy with energy-dispersive X-ray spectroscopy (TEM-EDS) mapping of the as-synthesized MoS2 film revealed the existence of Mo and S elements constituting the MoS2 crystalline structure (Figure 2c). Meanwhile, Al and O elements from the single-crystalline Al2O3 (sapphire) substrate were also observed. To validate the uniformity of the MoS2 film over the entire sapphire substrate, we conducted a wafer-scale spectroscopic analysis via Raman and photoluminescence (PL) mapping. The unit pixel size for the Raman mapping analysis on the 2-inch wafer was 5 × 5 mm2. Laser spot area was 2 × 2 µm2. One random point within one pixel area was measured for Raman and PL mapping. Thus, a total of 76 spots were examined as shown in Figure 3a. Figure 3b shows a typical Raman spectrum of the MoS2 multi layers. The two distinctive peaks indicate the in-plane vibrational modes of the Mo and S atoms (E12g) and the out-of-plane vibrational mode of S atoms


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(A1g).34 The difference (∆) between the two peak positions, a strong indicator of the number of MoS2 layers, is approximately 24.9 cm-1. In general, this value indicates a MoS2 film with four layers. The corresponding Raman data obtained from the 2-inch sapphire wafer reveals the spatial distribution of the delta values. The Raman mapping data is strongly related to layer uniformity (Figure 3c). The delta values ranged from 24 to 24.9 cm-1. The low deviation of the delta values confirms highly uniform MoS2 layers. Figure 3d shows the PL peak (~1.8 eV) associated with indirect band gap of the multilayer MoS2. As shown in Figure 3e, PL mapping image was obtained from the emission peak of 1.8 eV for MoS2 transferred to the SiO2/Si substrate. The relevant PL emission peaks were tightly distributed around 1.8 eV on the entire wafer. We achieved a uniform PL data over the entire region of the sapphire wafer covered by the MoS2 nanofilm. These spectroscopic characterizations, including Raman and PL confirm that the as-synthesized MoS2 nanofilms are highly uniform (also See Figure S2 in SI). A field effect transistor (FET) device, the core building block of an electronic circuit, should be integrated with excellent electrical performance, high uniformity, and acceptable yield across a wafer. Figure 4a exhibits the transfer characteristics (IDS-VGS) of the 250 MoS2 transistor devices with the same gate length of 10 µm on a 2-inch wafer. As shown in the inset of Figure 4a, the drain current (IDS) was measured as a function of the drain bias (VDS) from −5 to 5 V to verify the contact property of the metal-semiconductor (Au/MoS2) junction; it reveals an Ohmic contact with a linear IDS-VDS relationship.35 Specifically, all the 250 tested devices showed a clear n-type semiconducting behavior with the current increase at a positive voltage. Interestingly, the deviations of the off-current levels were relatively wider than those of the on-current region. Such relatively large fluctuation in the off-current region might be due to the uncontrollable variables related to the physical properties of the MoS2 channel or the junction interface region.



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The other cumulative transfer curves with channel lengths from 20 to 50 µm are also shown in Figure S3, SI. Indeed, approximately 1200 MoS2 transistors could work well, showing excellent uniformity of device-to-device electrical performance on the 2-inch wafer-scale (device yield >~95 %). We also measured the output characteristics (IDS-VDS) in the range of gate voltages from −40 to 60 V (with a voltage step of 20 V) (Figure 4b). IDS increased linearly at the low drain voltage region, indicating a strong Ohmic contact between the MoS2 channel and the Au/Cr metal.35 The length-dependent electrical property is also shown in Figure S4, SI. Figure 4c–e display the statistical histograms of the essential electrical parameters such as the mobility, threshold voltage, and on/off ratio. As shown in Figure 4c, the transistor mobility is extracted using the following equation: =(

)( )

where, μ is the device mobility, is the drain current, is the gate voltage, is the channel length, is channel width, and is oxide capacitance per unit area between the channel and SiO2 back gate ( =

; is the dielectric constant of SiO2 = 3.9; is the thickness of SiO2

= 100 nm). The average mobility was calculated to be 0.8 ± 0.2 cm2/Vs. The threshold voltage and log on/off ratio were measured to be 18.0 ± 6.8 V and 4.3 ± 0.7, respectively. Figure 4f–h show the mapping data of 10 × 10 devices representing the spatial uniformity of the mobility, threshold voltage, and log on/off ratio. It would be necessary to carefully design and perform the fabrication process for minimizing the device variation. For instance, transfer-related process (fishing-out to reduce wrinkle, drying to minimize the macro pore between substrate and MoS2 film, and PMMA removal to minimize the residual on the MoS2 film) should be optimized to achieve good uniformity of FETs.


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Further, we explored the channel length dependence of the MoS2 transistor performance for the MoS2 transistors. As displayed in Figure 5a, the field effect mobilities of the 250 devices for each channel were plotted with standard error bars. In principle, the estimated field effect mobility (µFE) of the MoS2 transistors should be nearly constant regardless of the channel length.36,37 The mobility did not change with increasing channel length, meaning that our MoS2 transistor would operate well in diffusive charge transport regime.38 As the channel length becomes longer, the error bars of mobility values become smaller due to average-out effect of some variants such as grain size, boundary and so on. Alternatively, processing approaches for increase in grain size and grain boundary healing will lead to the improved device uniformity. To determine the contact resistance (Rc) between the metal contact and MoS2 channel, we utilized the conventional transfer length method. The total resistances are plotted as a function of the channel length from 10 to 50 µm at a gate voltage of 70 V as shown in Figure 5b. The intercept of the y-axis obtained from the extrapolated curve is 1.2 MΩ∙µm, which represents twice the

contact resistance (denoted as 2Rc) and thus, Rc should be 0.6 MΩ∙µm. Further, we extracted the effective Schottky barrier height between the MoS2 channel and metal electrode. Figure 5c shows the temperature-dependent transfer curves (IDS-VBG) at the variable temperature range of 313 to 388 K (in steps of 15 K) for the device with a channel length of 40 µm at ambient conditions. There are two distinct regions on the temperaturedependent transfer curves: the thermionic emission transport (temperature-dependent) and the thermally assisted tunneling transport (temperature-independent).39,40 Thus, the real Schottky barrier height should be determined near the flat-band configuration (the inset of Fig. 5d). The



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drain current through the Schottky junction can be expressed by the 2D thermionic emission, as follows: = ∗

!/

#$% &−

( +Φ* − ./ )* -

where, ∗ is the 2D equivalent Richardson constant, is the contact area,

is the temperature,

( is the electron charge, )* is the Boltzmann constant, Φ* is the Schottky barrier height, and - is the ideality factor. The Schottky barrier heights calculated using the 2D thermionic-emission equation are plotted with respect to a different gate voltage range of –40 to 40 V (Figure 5d). They decreased almost linearly with increasing gate voltage (–40 ~ 0 V). The Schottky barrier height saturates near the transition voltage (> 0 V), where the voltage is considered a flat-band voltage (no band bending). Thus, the actual Schottky barrier height of this device is estimated to be approximately 71.9 meV. Charge transport in atomically thin 2D material-based devices can be strongly hindered by charge traps in the gate oxide or 2D channel-oxide interfaces.41,42 Such a charge trapping phenomenon gives rise to device instability. Thus, it is imperative to investigate the intrinsic channel property by minimizing the extrinsic physical parameters such as the oxide charge trapping. In this context, pulsed current-voltage (I-V) measurement is a useful technique to investigate the intrinsic behavior of the MoS2 semiconductor.43 Figure 6a shows a schematic of the pulsed I-V measurement setup configuration, where the DC bias and AC pulse are simultaneously applied to the gate and drain region of the MoS2 transistors. The setup configuration for pulsed I-V measurement is shown in Figure S5a, SI. The drain current was monitored as function of time (ms) using a Keithley pulse module (4225 pulse measurement unit, PMU). Figure 6b shows the difference in the transfer curves between the conventional DC and pulsed I-V measurement (left panel), and also corresponding transient drain current as a function


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of time (right panel). In conventional DC measurements, the relative large hysteresis is clearly observed when sweeping the gate voltage from −40 to 70 V (black line). Such a hysteresis is primarily induced by the charge trapping between the MoS2 channel and gate oxide/interface, where the amount of the trapped charges can be simply estimated by the threshold voltage shift (ΔVth) described by the following equation, 0122 = × ∆45 /( where, 0122 is the amount of the effective trapped charge, and ∆45 is the threshold voltage shift, is the oxide capacitance, and ( is electric charge. Considering ΔVth of ~24 V in DC ID-VG curve, Neff is calculated to be ~5.2 × 1012 electrons/cm2 (black line). However, ΔVth was dramatically reduced to ~9 V for the pulsed I-V measurement (under a pulse with a rise time of 1 ms and pulse width of 10 ms) (orange line). The calculated amount of effective trapped charge is ~1.9 × 1012 electrons/cm2. Thus, the intrinsic property of the MoS2 channel could be studied by the pulse measurement system. Figure 6c shows the on-current changes in the MoS2 transistor as a function of the pulse rise time under a gate voltage of 40 V and drain voltage of 5 V. Overall, application of the shortest pulse to the transistor increased the current by ~45% and the hysteresis was also considerably reduced by ~66% (the inset of Figure 6C). By reducing the pulse rise time from 1 ms to 300 µs, the extrinsic scattering or trapping factors could be effectively excluded, resulting in a more intrinsic behavior of the charge carrier. The raw data of the pulsed I-V is shown in Figure S5b–c, SI. Meanwhile, a shorter pulse rise time of 100 µs caused the abnormal pulse current shape (see Figure S5d, SI). In principle, even if the pulse measurement setup (Keithley 4225 PMU) is capable of reducing the rise time down to 50 ns, the MoS2 transistor could not respond to pulse



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rise times shorter than 300 µs, owing to the high MoS2 channel impedance and high contact resistance. If the channel dimension is scaled further down, it would be possible to extract the charge carriers flowing exclusively through the channel, more quantitatively, by minimizing the charge traps. Figure 6d shows the field effect mobility as a function of the pulse rise time. Similarly, it is more beneficial to obtain the intrinsic mobility values using relatively short rise times; i.e., 300 µs. The estimated maximum intrinsic mobility is ~4.5 cm2/Vs. Thus, pulse measurements could provide more insights on the charge transport of the 2D layered materials.

CONCLUSION We successfully demonstrated the wafer-scale integration of the MoS2 FET array devices (active area of 2 inch) on a 4-inch Si wafer with high homogeneity via a simple, sequential twostep process combining the sputtering of MoO3 and sulfurization by CVD. Our simple and reliable 2D MoS2 growth technique provided an excellent statistical data of the transistor performance (device yield of ~95%, average mobility of 0.8 ± 0.2 cm2/Vs, and log on/off ratio of 4.3 ± 0.7). Moreover, through the novel pulsed current-voltage (I-V) electrical characterization, a more intrinsic charge transport behavior of the MoS2 transistor device could be studied by suppressing the charge trapping effects either the channel interfaces or gate oxide. Our simple 2D MoS2 nanofilm growth route could be also applied to other 2D materials, enabling the chip integration of novel 2D layered device architectures.

EXPERIMENTAL SECTION Sputtering deposition of MoO3. The MoO3 film was deposited on 2-inch sapphire substrates via magnetron sputtering (A-Tech System Co, Ltd, Flexlab System 100) using a 4-inch MoO3


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target (Applied Science Co.) at room temperature, without applying any heat during and/or after sputtering. The sputtering of MoO3 was carried out at an RF power of 200 W (0.53 W cm−2) under an Ar (99.9999%) flow rate of 60 sccm. The pressure of the sputtering chamber was initially reduced to about 2.0 × 10−6 Torr and maintained at 3.0 mTorr during sputtering. Electrical Characterization. The pulsed current-voltage (I-V) measurement was carried out on a semiconductor parameter analyzer (Keithley, 4200-SCS) at room temperature. The DC and pulse bias were simultaneously applied to the gate and drain side of the MoS2 transistor via a Keithley pulse module (4225-PMU) with an internal 50 Ω impedance matching capability. The device under test was loaded on a Summit Semi-automated Probe System with the capability of loading a 200 mm wafer.

Conflict of Interest: The authors declare no competing financial interest.

Supporting Information. Analysis data of MoO3 film; The 3D Raman and PL plots of assynthesized MoS2 multilayer film; Total transfer curves (IDS-VGS) with different channel lengths; The channel length dependences of transistor characteristics; Pulsed current-voltage measurement setup and the hysteresis loops obtained by changing the pulse rise time.

AUTHOR INFORMATION Corresponding Author *[email protected], [email protected], [email protected]

ACKNOWLEDGMENT 13 Environment ACS Paragon Plus


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This study was supported by the Fundamental Research Program (PNK5290) of the Korean Institute of Materials Science (KIMS). B. C. are grateful for the support from the Basic Science Research Program of the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (NRF-2017R1C1B1005076).


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Figure 1. (a) Optical image of 2D MoS2 field effect transistor (FET) array devices integrated on 4 inch SiO2/Si wafer (green square area). Picture of single MoS2 FET device with channel length of 50 µm and width of 100 µm is shown in final enlarged image of Figure 1a. (b) The sequence of fabrication process for MoS2 array devices.



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Figure 2. (a) High-resolution cross-sectional TEM image of as-synthesized MoS2 film on sapphire substrate. (b) X-ray photoelectron spectroscopy (XPS) spectrum of MoS2 film. Violet and orange lines are the Mo-related peak and S-related peaks, respectively. (c) Mapping of TEM energy-dispersive X-ray spectrometry (EDS) analysis for the as-synthesized MoS2 film.


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Figure 3. (a) As-synthesized MoS2 film on 2-inch single crystal sapphire (Al2O3) substrate. And, total of 76 spot area with 5 × 5 mm2 behind the substrate area divided for spectral analysis. (b,c) Raman spectrum of MoS2 multi layers and the corresponding raman spatial mapping on 76 spots of 2-inch sapphire wafer. (d,e) Photoluminescence analysis peaks and the corresponding PL spatial mapping data with 76 spots covered by 2-inch sapphire wafer.



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Figure 4. (a) Transfer curves (IDS-VGS) of a collection of approximately 250 MoS2 back-gated transistors with channel length of 10 um at drain voltage of 5 V. The inset shows the drain current-drain voltage (IDS-VDS). (b) Output curves at various gate voltages. Statistical histograms of electron mobilities (c), threshold voltages (d), and log on/off current ratios (e) measured from total of 250 transistors in the array. Spatial color mapping of 10 × 10 devices for mobilities (f), threshold voltages (g), and log on/off ratios (h), respectively.


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a

b 60

1.2

Rtotal (MΩ.µm)

Mobility (cm2/Vs)

1.4

1.0 0.8 0.6

0.2

10

20

30

40

-4

10

20

2Rc ~ 1.2 (MΩ.µm)

10

20

30

40

VGS=VFB

200

ΦB (eV)

150

-6

10

10-7

50

LG (µm)

d

Temp. : 173 - 413 K (step: 20 K)

10-5

Cr/ Au

MoS2

Cr/ Au

100 ~71.9 meV

50

-8

10

10-9 10

40

50

LG (µm)

c

@ VG= 70 V

0

0.4

IDS (A)

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LG = 10 µm

0

-10

-40

-20

0

20

40

60

-50 -40 -30 -20 -10 0 10 20 30 40 50

VBG (V)

VGS (V)

Figure 5. (a) Plot of the field effect mobilities on total of 250 MoS2 transistor devices as a function of channel length with standard error bars. (b) Plot of total resistance (Rtotal) as a function of channel length at gate voltage of 70 V. The intercept of y-axis denote twice of contact resistance (black arrow). (c) The temperature-variable transfer curves from 173 to 413 K with the step of 20 K. (d) Plot of extracted Schottky barrier heights with various gate voltages for MoS2 transistors. And, the figure of inset shows the energy band diagram at flat-band condition.



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Figure 6. (a) Schematic of block diagram for pulsed current-voltage (I-V) measurement systems (b) The hysteretic current-voltage (I-V) for DC (black line), pulse (orange line) and the corresponding transient current curve (right panel). (c) The plots of on-currents of MoS2 transistors for DC and different pulse rise times, respectively. The inset shows the changes of the amount of hysteresis. (d) Plots of the field effect mobilities for DC and pulsed measurement.


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ToC


Transistors - ACS Publications - American Chemical Society

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