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Tunable Mobility in Double-Gated MoTe Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites Hyunjin Ji, Min-Kyu Joo, Hojoon Yi, Homin Choi, Hamza Zad Gul, Mohan Kumar Ghimire, and Seong Chu Lim ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b05865 • Publication Date (Web): 08 Aug 2017 Downloaded from http://pubs.acs.org on August 9, 2017

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ACS Applied Materials & Interfaces

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites

Hyunjin Ji†, Min-Kyu Joo‡, Hojoon Yi†, ‡, Homin Choi†, ‡, Hamza Zad Gul†, ‡, Mohan Kumar Ghimire†, ‡, and Seong Chu Lim†, ‡,*

†

Department of Energy Science, Sungkyunkwan University (SKKU), Suwon 16419, Korea

‡

Center for Integrated Nanostructure Physics, Institute for Basic Science (IBS), Suwon

16419, Republic of Korea

*Corresponding author E-mail: [email protected]

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ABSTRACT There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that, for a strong back-gate bias, the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that, owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

KEYWORDS Molybdenum ditelluride, double-gated, mobility modulation, interface trap density, interfacial Coulomb scattering, carrier distribution


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INTRODUCTION

Low-dimensional semiconductor materials are a promising potential alternative to conventional complementary metal-oxide semiconductor (CMOS) technology, which is fast approaching its fundamental physical limits in small-scale devices.1, 2 Two-dimensional (2-D) semiconducting transition-metal dichalcogenides (s-TMDs), whose monolayer is consisted of single metal atomic layer at the center and two chalcogenide atomic layers on the both sides, have a bandgap between 1 and 2 eV.2-4 The increase in carrier scattering by surface atoms, which is inversely proportional to the channel thickness, is no longer problematic in s-TMDs because the surface is self-terminated. However, owing to the bottom-up approach used for TMD device fabrication, it is difficult to realize a clean interface between gate dielectrics and the channel because the contact area is open to contamination by adsorbates and impurities during fabrication, including solvents and polymer residues. In the case of Si devices, the gate oxide is grown directly from bulk Si in such a way that the Si/SiO2 interface is not exposed to contamination sources. In addition, a large surface area of TMDs and transfer process in the course of device integration raise a concern of enhanced scattering of carriers by charged impurities at the gate dielectrics. This implies that the benefit of a smooth TMD surface is nulled by the presence of exotic scattering substances at the gate interfaces. Several approaches can be used to address this problem in TMD FETs: adopting new dielectric materials containing fewer ionic impurities,5-8 using thicker channels, and dielectric engineering for screening the electric field of defect sites that causes carrier scattering.9, 10 For example, h-BN, a 2-D insulator with no dangling bonds on its surface, has a band gap of 6.0 eV and a dielectric constant between 3 and 3.9. An h-BN layer is inserted between SiO2 and TMD channels in order to reduce scattering by charged puddles. Carrier mobility as high as 30 ~ 50 cm2/Vs have thus been realized.11 In the passivated structure of TMDs using hBN, the further enhanced carrier mobility has been reported for MoS2, MoTe2 and WSe2.7, 12, 13

Another approach is to increase the TMD channel thickness. A thicker channel enhances the carrier mobility through the weakening of Coulomb scattering resulting from physical separation from the gate oxides.14-16 For instance, a study of thickness-dependent mobility reported maximum carrier mobility in the case of approximately ten MoS2 layers.14, 15, 17 The reduced gate electric field inside a thick channel can result in a wide spatial extent of the charge distribution, thereby weakening Coulomb scattering by traps in the gate dielectric.



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When a high-k material passivates a semiconducting channel, Coulomb scattering by ionic impurities can be screened substantially, leading to a mobility enhancement.9, 10 However, it is well known that a high-k dielectric contains many ionic impurities. These competing tendencies are both present in a double gated (DG) FET fabricated using a high-k dielectric. By controlling the position and population of the channel carriers via the gate bias, the precise role of interfacial traps that modulate local carrier mobility and density can be clarified.18, 19 In particular, this may provide a method for achieving carrier mobility close to those in bulk TMDs, in ultra-thin TMDs devices. In this study, we fabricated a DG MoTe2 FET and studied the enhancement of the carrier mobility by controlling both the top- and bottom-gate biases. The behavior of the gate-biasdependent carrier mobility was evaluated by low-frequency (LF) noise analysis. This revealed the role of the parameters contributing to the degradation of the mobility, the interface trap density NST and the interfacial Coulomb scattering parameter αSC. By controlling the DG bias, the carrier mobility was enhanced by a factor of 9.4 from 0.8 to 7.5 cm2/Vs. The enhancement of the mobility results from the screening of ionic impurities by the channel carriers. A significant reduction in αSC is observed for an accumulation carrier density Nacc ~ 1012 cm-2. In addition, the decrease in NST with VBG, which contributes to the increase in mobility, indicates a displacement of the carriers away from the gate-dielectric interface. For the first time, our results reveal the role of trap charges and reflect the modulation of the carrier distribution within the channel in a TMD DG FET. Unlike the use of dielectric engineering for the purpose of mobility enhancement, gaining a better understanding of carrier-scattering mechanisms in a channel using a DG FET opens new perspectives for innovative device structure, and for enhancing the performance of 2-D devices involving multiple or surrounding gates.

RESULTS AND DISCUSSION Device fabrication and material characterization The fabrication of a DG MoTe2 FET on an Si/SiO2 substrate accompanies the mechanical exfoliation of an MoTe2 flake for the channel, electron-beam lithography (EBL), metal deposition for the electrodes, and atomic-layer deposition (ALD) for the top gate. A Ti/Au (5/50 nm) bilayer metal was deposited to fabricate the source and drain electrodes. A 50-nmthick Al2O3 layer was applied by ALD for the top-gate dielectric, and its quality was examined using a capacitance-voltage measurement.20 The top-gate electrode was formed by 4 ACS Paragon Plus Environment

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metal deposition (Cr/Au=5/70 nm). The MoTe2 DG FET is outlined in Figure 1a. The optical image of the sample, before the fabrication of the top-gate electrode, is shown in the upperleft inset. Atomic-force microscopy (AFM) shows that the MoTe2 thickness is approximately 8 nm, which corresponds to 11 layers, as shown in the upper-right inset. The crystallinity of 2H-MoTe2 was estimated by measuring the full width at half maximum (FWHM) from the Raman spectrum shown in Figure 1b. The E12g peak at 235 cm-1, which originates from the in-plane vibrations of Te atoms, displays a FWHM of 4.6 cm-1. After depositing the Al2O3 layer, the peak position and FWHM in the Raman spectra of MoTe2 do not change, supporting the hypothesis that doping, defects, and strain effects are made negligible by the Al2O3 layer.21-23 Preliminary high-temperature annealing between 150 °C and 200 °C is usually recommended for TMD FETs, to improve metal-contact properties and the adhesion of the channel to the gate-dielectric layer.24-27 However, in this experiment, only electrical annealing was conducted for the MoTe2 DG FET, because the device had already undergone hightemperature annealing during the Al2O3 deposition at 200°C (Supporting Information S1 for I-V characteristic after ALD). To allow a flow of current that was sufficiently large for the Joule heating of MoTe2, both the top- and back-gate biases were controlled independently. Under these conditions, the device is in the “on” state with a moderate channel current. Thus, during electrical annealing, VTG was set to 0 V, VBG to 10 V and VDS to 0.1 V. Under the bias configuration, the initial channel current was around 0.66 µA. After the current annealing, IDS increased to 1.51µA (refer to Supporting Information S2).

DC analysis The static/LF noise properties of the MoTe2 DG FET were analyzed using the system configuration shown in Figure 1c. VTG was swept while registering the drain current IDS for different VBG values, as shown in Figure 2a. VBG was varied from -20 to +20 V in 10 V increments. All the measurements in Figure 2 were taken with VDS = 0.1 V. As expected, VTG controlled the channel current more effectively than VBG, because the equivalent oxide thickness (EOT) for the top gate dielectric (50 nm Al2O3 layer) is less than the back-gate dielectric thickness (300 nm SiO2 layer). The SiO2 EOT is 10.7 times greater than the Al2O3 thickness.20 Figures 2a-e display the DC features for the MoTe2 DG FET for a given VBG over a range of VTG, after current annealing. 5 ACS Paragon Plus Environment


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The transconductance (gm) maxima, shown in Figure 2b, lie within the range -20 V < VTG < -10 V, and increase with increasing VBG. Using the gm results in Figure 2b, the Y-function method (YFM) was employed to extract device parameters such as the low-field mobility µ0, the contact resistance RSD, and the flat-band voltage VFB, plotted in Figures. 2c-e. (Details of the YFM are provided in the Supporting Information, S3.) 28-30 The increase in VBG improves the field-effect mobility (µFE) and µ0, as shown in Figure 2c. There is a nearly linear increase in both µFE and µ0 with respect to VBG. We calculated µFE from the two-probe IDS-VTG curves, which are affected by RSD, whereas the µ0 values derived by the YFM are independent of RSD. To clarify the influence of RSD on µFE at various VBG values, we plot the increase rate of carrier mobility, defined as (µ0-µFE)×100/µFE in the inset of Figure 2c. Here, µ0 is almost twice µFE for VBG < 0, amounting to a 100% increase, compared with the slight increase in µFE, for VBG ≥ 0, of 20 to 60%. These results imply that the impact of the parameters on the degradation of the mobility weakens as VBG increases. In Figure 2d, the RSD values obtained by the YFM and the total resistance RTOT of the MoTe2 FET are plotted in the weak and strong accumulation regions. Both quantities show a simple exponential decrease with VBG, the opposite trend to that of the mobility in Figure 2c. The ratios of RSD and the channel resistance RCH to RTOT are plotted in the inset of Figure 2d. When VBG > 0, the ratios RSD/RTOT (R%SD) and RCH/RTOT (R%CH) begin to change noticeably. R%SD exceeds 80% for VBG < 0 and then decreases to approximately 50% at VBG = 20 V. The drop in R%SD signifies that a larger VBG contributes to a lowering of the contact resistance, resulting in the increase of carrier flow, instead of the consumption of VDS predominantly in the contact region. The increase in VBG in Figure 2e makes VFB shift toward negative voltages, indicating the earlier turning on of the device. In the inset of Figure 2e, the accumulated carrier density Nacc at VTG = 0 V, for each VBG, was obtained using the relation Nacc = COX (VTG - VFB)/q, where COX is the gate-dielectric capacitance per unit area and q is the elementary charge 1.6 × 10-19 C. In DC characterizations, we addressed the effects of gate control on the associated device parameters µ0, RSD, and VFB. These improvements arise not only from the modulation of the transport characteristics in the channel, which also depend on the top- and back-gate biases. However, some device parameters are not accessible from DC measurements at room temperature. Since TMD device performance is strongly susceptible to the presence of ionic 6 ACS Paragon Plus Environment

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impurities at the interface with the gate dielectrics, we studied the LF noise characteristics of the MoTe2 DG FET to investigate the correlation between mobility improvement in the device and the Coulomb interaction between the channel carriers and charged impurities residing in the top- and bottom-gate oxides.

LF noise modelling and analysis In the LF noise theory developed for Si MOSFETs, the presence of carrier fluctuations can be explained from two main perspectives31: (1) the scattering of carriers by impurities in bulk Si, which provides the foundation for the Hooge mobility fluctuation (HMF) model; and (2) the capture and release of carriers at interface trap sites in the gate oxide, which form the basis for the carrier number fluctuation (CNF) model. Given the exposure of the TMD channel to the environment, interfacial trap sites are expected to affect carrier transport more severely than impurities inherent in the channel. For this reason, previous LF noise studies on TMD FETs strongly supported the validity of the CNF model20, 32-35, expressed as

= =

(1)

where SIDS is the power spectral density (PSD) of the drain-current (IDS) noise, SVfb is the PSD of the flat-band voltage noise, q is the electric charge, kB is the Boltzmann constant, T is the temperature, NST (! ) the interface trap density for LF noise, f is the frequency, W is the channel width, and L is the channel length. In multilayer MoTe2 FETs, the gate interface with impurities and traps perturb the channel current, not only by capturing or releasing charge but also by scattering the carriers via the Coulomb interaction.20, 36 These border or interfacial heterogeneities, which are probed by characterizing 1/f noise, can be visualized as trap sites that are randomly distributed at the MoTe2-gate dielectric interface. They may also include weakly bonding chemical residues and various adsorbates, as shown in Figure 4b.37-39 When comparing TMD FETs with Si-MOSFETs, it is important not to underestimate the interfacial Coulomb scattering by charged impurities at the gate oxide. It is therefore necessary to introduce the carrier number fluctuation and the correlated mobility fluctuation (CNF+CMF) model which is expressed in a single equation, to account for the effects of both fluctuation mechanisms simultaneously. Such a model was applied to silicon-on-insulator (SOI) MOSFETs because of the strengthened influence of interface traps. The formula for the CNF+CMF model is very similar to that of the CNF model because of the common origin of 7 ACS Paragon Plus Environment


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the current fluctuations due to interface trap sites. Their difference lies in the additional Coulomb scattering term originating from electrostatic field of traps, the second term in the parentheses in Equation 2 below. The combined model is expressed as follows, where αSC is the interfacial Coulomb scattering parameter.

≈ 1 +

%& '(

(2)

The acquisition and analysis of LF noise spectra in an FET are illustrated schematically at the bottom of Figure 3a. First, the fluctuating IDS in the time domain (inset Ⓐ) was converted to SIDS in the frequency domain (inset Ⓑ). Then, the plot of SIDS (normalized by IDS2) vs. IDS (inset Ⓒ) was subsequently fitted to the LF-noise models.40 Finally, the associated LF noise parameters were extracted. The schematic at the top of Figure 3a depicts the interfacial carrier fluctuations in an FET, including ① carrier trapping, ② detrapping at the gatedielectric interface trap sites, and ③ Coulombic scattering of carriers by charged traps. All these effects contribute to the temporal and spectral variations of IDS in the CNF+CMF model for an FET. Figure 3b plots static IDS vs. VTG (solid lines) for VBG values varying from -20 to +20 V in 10 V increments. To characterize the LF noise properties, SIDS was extracted at specific current values marked with circles in Figure 3b. A selection of these currents were further investigated with VBG = 0 V to examine the dependence SIDS on f as a function of VTG, as shown in Figure 3c. SIDS is proportional to 1/f for all the top-gate voltages. This 1/f behavior is consistently reproduced in the current for different VBG values (Supporting Information S4). To understand the LF noise properties of our devices, normalized SIDS values () /+) )

were plotted as a function of IDS (Figure 3d) and fitted to the different noise models. We fixed VDS = 0.1 V, where the device exhibits ohmic behavior (Supporting Information S5). At f = 10 Hz, ) /+) is plotted as a function of IDS for different VBG values. Since IDS varies with

VTG at room temperature, the data points for a given VBG are plotted with the same color. Thus, each plot was generated for a fixed back-gate potential and for a varying top-gate potential, as in Figure 3b. If the considerable noise due to the contact resistance exists, the influence of it on noise ) /+) should be observable because the trend of contact noise is very different from that of channel noise as a function of a gate voltage32. For instance, in a plot of ) /+) vs. IDS, 8

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when the noise attributed to the channel area, ) /+) gradually decreases with an increase of IDS. In a contrast to the channel noise, ) /+) caused by the contact resistance gradually

grows with IDS and become comparable to channel noise. Therefore, if the contact noise is significant, then the overall ) /+) turns up in high current range. Such a turn-up of ) /+) is not observed in Figure 3d. The results lead us to conclude that the noise by the

contact resistance is negligible in our device. The LF noise characteristics of the MoTe2 DG FET in the low-current regime (IDS < 10-8 A), shown in Figure 3d, display a significant deviation from the simple CNF model. This discrepancy is explained by the background theory. In contrast, the CNF+CMF model with variable αSC shows good agreement with the LF noise data over the entire current range. The variable αSC is gate-dependent:41, 42 α ./0 1 = µ

2

(3)

5 &( 344

where µC0 is the coefficient for scattering effectiveness, and γ is the exponent on Nacc. Figure 3e shows the dependence of log(αSC) on log(Nacc) for various VBG values. As predicted by Equation 3, αSC is inversely proportional to Nacc owing to charge screening.43 The slope of the log-log plot in Figure 3e yields the exponent γ in Equation 3. In the plot of

αSC as a function of Nacc for the MoTe2 device, interfacial Coulomb scattering by charged traps displays a stronger dependence on VTG than VBG for the MoTe2 DG FET. Figure 3e compares interfacial Coulomb scattering for the three different devices, as functions of carrier density. The circle symbols denote the MoTe2 DG FET used in this study, the green band denotes the MoTe2 single-gated (SG) FET,20 and the yellow-green line represents a conventional Si-MOSFET.31 It is important to note the steeper slope γ (ranging from -1.9 to 2.2) for the MoTe2 DG FET than for both the MoTe2 SG FETs (-1.64 ≤ γ ≤-1.18) and the Si MOSFETs (γ = -0.5). Because αSC is determined by the carrier concentration, in order to see the strength of Coulomb scattering in each device, we compared αSC at a given carrier concentration where the devices operate. For instance, for an inversion carrier density Ninv ≈ 1012 cm-2 for Si-MOSFETs, we normally obtains αSC ≈ 1~4 × 104 Vs/C.44, 45 With regard to TMD FETs with Nacc = 1012 cm-2, αSC ≈ 105 Vs/C was reported for MoTe2 SG FETs on Si/SiO2 substrate20 and αSC ≈ 106 Vs/C was observed in the present work for MoTe2 DG FET. Thus, Coulomb scattering is almost ten times stronger in a TMD than in a conventional



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Si FET. A further ten-fold increase in Coulomb scattering occurs when TMD is implanted into a DG FET. As the carrier concentration increases significantly beyond 1012 cm-2, long-range scattering is weakened, as implied by Equation 3, owing to charge screening. This behavior is well reproduced in Figure 3e. However, the long-range scattering parameter is clearly segregated at low carrier concentrations among the Si, single-gated, and double-gated TMD devices. The

αSC value for the MoTe2 DG FETs is comparable to that for the Si FETs only when Nacc approaches 1013 cm-2. Values of αSC for all the devices are comparable for carrier densities of order 1013 cm-2, where the electric field produced by ionic impurities is likely to decay significantly in the channel because of screening. Stronger Coulomb scattering is counterintuitive because passivating the channel with high-k dielectrics contributes to enhanced carrier mobility.9 To explain the greater susceptibility of a double-gated MoTe2 FET to Coulomb scattering than a single-gated one, it is necessary to further analyze another parameter, the trap-site density NST. A large αSC in our device may be partially attributed to large NST. A further reason for considering NST is that the top- and bottom-gate dielectrics both contain charged impurities. In contrast to the relatively weak dependence of the interface trap density (Dit) on VBG, which is apparent in the transfer curves plotted in the inset of Figure 3f, the NST values deduced from the LF noise, a semilogarithmic plot of Figure 3f, decrease rapidly from ~1014 to ~1013 eV-1cm-2 as VBG increases from -20 to 0 V. It then decreases further with a different slope over VBG > 0, as shown in Figure 3f. Such a high value for NST in our device is likely to have resulted from a higher density of interface traps from the Al2O3 top-gate dielectric, rather than from the SiO2 layer. Not surprisingly, a stronger 1/f noise (by one to three orders of magnitude) and higher NST (by one to two orders of magnitude) have been reported in high-k gate dielectrics such as Al2O3, compared with SiO2 in Si-MOSFETs.31 In the case of nanoscale materials such as TMDs or nanowires, devices with a high-k gate dielectric exhibit NST values between 1013 and 1014 eV-1cm-2, while devices with SiO2 shows NST between 1010 and 1011 eV-1cm-2.46-49 We can therefore reasonably argue that strong interfacial Coulomb scattering and the high interface trap density observed in this study result from the top-side high-k dielectric Al2O3. A universal mobility curve displays the dominance of Coulomb scattering at room temperature in TMD FETs on a SiO2 substrate.14, 20, 36, 50 To understand the interplay between

αSC and NST in determining the Coulomb-scattering-limited carrier mobility µC, we calculated 10 ACS Paragon Plus Environment

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µC = (αSC ×NST)-1 from the LF-noise modelling. To obtain µC, the αSC was extracted at the highest value of Nacc for each VBG value in Figure 3e. Figure 4a compares µC and µFE, plotted as functions of VBG, for the MoTe2 DG FET. The trends shown by µC and µFE in response to VBG are similar. The strong resemblance between µC for LF noise and µFE for DC supports the hypothesis that Coulomb scattering by interfacial border traps dominates carrier transport in the MoTe2 DG FET.51 In this respect, the interest in Figure 3f lies in the change in NST with VBG. In a DG FET, the variation in NST should depend on the type of dielectric material used for making the device, rather than on VBG. The variation in all the device parameters reflects the behavior of carrier transport in the channel. In the present case, they are controlled by both the top- and bottomgate biases. Because physically NST cannot be changed in the gate oxides by using the gate bias, Figure 3f implies that NST does not simply represent the number of trap sites in the dielectrics, but rather the number of trap sites that actively capture carriers. One plausible scenario is the spatial shifting of the ensemble of carriers by the gate bias, resulting in a decrease in the influence of the trap sites. If this scenario is correct, NST should depend on the gate bias or on the distribution of carriers shown schematically in Figure 4(b). The capture of carriers by the trap sites occurred by resonant tunneling, because the trapping/detrapping of carriers in the CNF noise model is the superposition of generation-recombination events that occur at the interface. Consequently, the gate-induced drift and broadening of the ensemble, reflected in the probability Pcar of finding carriers(Figure 4b), varies the number of active trap sites NST that capture and release channel carriers, instead of electrostatic interactions. Pcar is normalized by dividing the number density of local charge to the total charge. Nacc is of the order of 1012 cm-2 at the extraction of NST. At such a carrier concentration, the Coulomb field produced by the trap charges is significantly screened out. Thus, the variation in NST results from the shift in Pcar, rather than from Coulomb interaction. The orange and blue solid lines in Figure 4b indicate the gate-bias-driven repositioning of the carrier distribution. Pcar correlates with the charge concentration in the channel. Since it is not possible to measure the local carrier concentration precisely, Pcar serves simply as a conceptual framework describing the charge redistribution depending on VBG in the channel . The top gate in our device is much thinner and has a greater dielectric constant. Because of the field from the top gate is stronger than that from the bottom gate, it is expected that, for positive VTG, carriers should exist near the top-gate dielectric and that their distribution curve 11 ACS Paragon Plus Environment


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is asymmetric, as shown in Figure 4b. Considering that the gate field in the Al2O3 layer is stronger than in the SiO2, an asymmetric Pcar is expected to form very near the Al2O3 interface when ① VBG

Tunable Mobility in Double-Gated MoTe2 Field ... - ACS Publications

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