Vertical Electrolyte-Gated Transistors Based on Printed Single-Walled

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Vertical Electrolyte-Gated Transistors Based on Printed Single-Walled Carbon Nanotubes Marcel Rother, Adelaide Kruse, Maximilian Brohmann, Maik Matthiesen, Sebastian Grieger, Thomas M. Higgins, and Jana Zaumseil ACS Appl. Nano Mater., Just Accepted Manuscript • DOI: 10.1021/acsanm.8b00756 • Publication Date (Web): 28 Jun 2018 Downloaded from http://pubs.acs.org on June 29, 2018

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ACS Applied Nano Materials

Vertical Electrolyte-Gated Transistors Based on Printed Single-Walled Carbon Nanotubes

Marcel Rother1, Adelaide Kruse1,2, Maximilian Brohmann1, Maik Matthiesen1, Sebastian Grieger1, Thomas M. Higgins1, and Jana Zaumseil1,3*

1

Universität Heidelberg, Institute for Physical Chemistry, D-69120 Heidelberg, Germany

2

Ohio University, Department of Chemistry and Biochemistry, Athens, Ohio 45701, USA

3

Universität Heidelberg, Centre for Advanced Materials, D-69120 Heidelberg, Germany

KEYWORDS. Single-walled carbon nanotubes, polymer-wrapping, aerosol-jet printing, electrolyte-gated transistors, printed electronics, vertical transistors

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ABSTRACT For all-printed circuits, the critical device dimensions, in particular the channel length in lateral field-effect transistors (FETs), are limited by the printing resolution and alignment accuracy. In contrast, the channel length in vertical electrolyte-gated transistors (VEGTs) is mainly defined by the film thickness and can be easily scaled down to less than 100 nm to achieve high current densities. For practical VEGTs, the printed semiconductor must be highly porous to enable efficient electrolyte-gating by ion penetration. Here, we use aerosol-jet (AJ) printed layers of polymer-sorted (6,5) single-walled carbon nanotubes as the semiconducting layer with film thicknesses from less than 50 nm to several hundred nanometers that were sandwiched between evaporated (gold) or printed (silver nanoparticle) metal electrodes and gated by an ionic liquid-based iongel. Vertical charge transport in the obtained threedimensional nanotube networks is confirmed via conductive AFM measurements. The nanotube network VEGTs exhibit transfer characteristics with good on/off ratios and high onconductances. The effective gating of the semiconducting nanotubes throughout the entire active area of several hundred µm² is corroborated by in-situ Raman spectroscopy. The overall transistor performance scales with film thickness and electrode overlap and is comparable to photolithographically structured lateral electrolyte-gated transistors with 2 µm short channels. VEGTs could thus be a viable replacement of printed lateral FETs that require too much space for the desired drive currents.


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INTRODUCTION Solution-processable semiconductors for field-effect transistors (FETs) cover a wide range of materials from small molecules,1-3 colloidal nanoparticles,4-6 metal oxides,7-8 polymers,9-10 to carbon nanotubes11-13 and monolayered transition metal dichalcogenides.14 Many of them have been shown to be also printable, e.g., by gravure,15-18 inkjet,19-22 or aerosol-jet printing,2328

and thus can be patterned without additional processing steps. However, most printable

semiconductors show rather low charge carrier mobilities and thus require short channel lengths and/or large channel widths to reach the drive currents required for many applications. Large channel widths increase the footprint of the device and are thus a limiting factor for electronic devices that require high integration density and resolution, such as displays or sensor backplanes.29-30 Short channel lengths are inherently challenging because of the limited alignment accuracy and resolution of printing processes, especially for flexible and even more for stretchable substrates.31 One possible solution to overcome the fundamental limitations of lateral device architectures is to change the direction of current flow from parallel to perpendicular to the substrate. In these so-called vertical FETs (VFETs), the resolution limitation is no longer defined by the lateral dimensions of the device but by the thickness of the semiconducting layer, which is controllable on a much more precise level, even on the nanometer scale. A vertical structure simultaneously decouples the alignment accuracy from the critical device dimension, i.e., the channel length L. Many VFETs use a source electrode that is embedded in the semiconductor layer and sandwiched between the drain and dielectric/gate electrode.32 In this geometry the source electrode has to be very thin, structured, or consist of nanowires, to allow the electric field of the gate electrode to penetrate and thereby control charge accumulation and conductivity.33-36 Others have used a triode-like structure, i.e., a gate electrode placed within the semiconductor and between source and drain, which unfortunately results in rather high leakage currents.37-38 3 ACS Paragon Plus Environment


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Recently, a rather different concept was introduced by Baby et al. A mesoporous metal oxide semiconductor layer was sandwiched between a source and drain electrode and electrolytegated via an iongel and side-gate,39 thus creating a vertical electrolyte-gated transistor (VEGT). The drift and accumulation of mobile ions in response to an applied gate field and thus charge accumulation and transport in a permeable semiconductor is a known concept for electrolytegated or electrochemical transistors, although usually utilized with device architectures that exhibit lateral charge transport between the source and drain electrode over a channel length of several micrometers.40-42 The vertical charge transport within a porous semiconductor between stacked electrodes with distances of tens to hundreds of nanometers can lead to very high current densities if efficient quasi three-dimensional doping can be achieved.39 This approach is in principle compatible with fully-printed devices. However, the metal oxide transistors demonstrated by Baby et al. required sub-micron electrode widths and hightemperature sintering (> 500 °C) of the printed precursor to create a porous semiconducting layer for effective ion penetration and doping. These limitations could be overcome by replacing the oxide semiconductor with a directly printable and inherently porous semiconductor layer such as a thick but open network of semiconducting single-walled carbon nanotubes (s-SWNTs). Networks of highly purified s-SWNTs already exhibit the desired properties of high carrier mobilities and high on/off current ratios in conventional FETs.11, 18, 43 They are easily printable even as very thick films (> 100 nm) via aerosol-jet (AJ) and inkjet printing.26, 44-45 The high semiconducting purity (>99.9 %) of SWNTs that is necessary for high on/off current ratios in short channel devices can be achieved via sorting techniques such as gel-chromatography or selective SWNT dispersion with conjugated polymers in organic solvents.43, 46-47 The latter method is scalable to rather large quantities using shear-force mixing instead of sonication.48


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Here, we employ thick aerosol-jet printed (6,5) SWNT films as the semiconducting layer between structured source/drain gold electrodes that were electrolyte-gated with an iongel and side-gate to study the vertical charge transport through the nanotube film, the influence of the lateral dimensions of the electrodes and printed area, and the overall film thickness. We corroborate by Raman spectroscopy that the electrolyte ions of the iongel are able to fully penetrate through the porous SWNT film even for electrode widths of more than 100 µm and thus efficiently gate the entire semiconducting layer. While the best devices show nearly no hysteresis and high on/off-ratios, the most critical factor is the purity of the nanotube dispersions especially regarding the absence of any residual metallic nanotubes. We further demonstrate that this approach can be readily extended to fully printed devices with source, drain and gate electrodes that were aerosol-jet printed with silver nanoparticle ink.

RESULTS AND DISCUSSION The device architecture (see Figure 1a,b) and dimensions (for detailed dimensions see Figure S1a, Supporting Information) of the vertical electrolyte-gated transistors (VEGTs) were chosen such that all components could also be easily deposited and patterned by printing as shown later. The bottom (source) and top (drain) electrode widths (Ws and Wd, respectively) were typically 100 or 200 µm, and the alignment of shadow masks was performed by hand. Thus, the dimensions were compatible with the alignment limits for roll-to-roll printing processes of around 20 µm.31 However, to initially investigate the device properties independently from the electrode printing process and to ensure more precise device dimensions and comparability to lateral short channel FETs, evaporated and partially photolithographically structured gold electrodes were first chosen as a model system. Polymer5 ACS Paragon Plus Environment


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sorted, monochiral (6,5) semiconducting single-walled carbon nanotubes (s-SWNTs) in toluene were obtained from CoMoCAT™ raw material by shear-force mixing followed by centrifugation as previously described in detail.48 In contrast to other purification methods, the resulting nanotube dispersions showed significantly longer (>1 μm) and less defective SWNTs and could be prepared in large volumes of up to 500 mL per batch with concentrations of a few mg L-1. A centrifugation step at a very high relative centrifugal force (284 600 g) was employed to minimize metallic nanotube residues as this is critical for the vertical channel devices fabricated here. The employed (6,5) SWNT dispersions did not show any residual metallic SWNTs (m-SWNTs) in absorption or Raman spectra (see Figure S2a,b, Supporting Information). However, both methods are limited and cannot detect very small ( 600 nm) nanotube films. We conclude, that the SWNT films exhibits at least a certain degree of three-dimensionality that allows for vertical charge transport through the film to occur, although limited by nanotube-nanotube junctions as single tubes bridging the whole film thickness are apparently not the main path of charge transport.


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Figure 3: Conductive AFM images of thin (150 nm, top) and thick (650 nm, bottom) printed (6,5) SWNT films on gold electrodes: (a) height and (b) corresponding normalized contact current that were measured simultaneously.

Achieving high current densities in VEGTs while maintaining fairly large and printingcompatible device dimensions requires efficient electrolyte-gating of the entire SWNT film. Previous work with a similar device architecture but mesoporous SnO2 as the semiconductor, showed a penetration depth of the ionic liquid of only 0.3 µm thus limiting the maximum electrode width and overall absolute current.39 To test the penetration depth of ions into the VEGTs we used in situ Raman spectroscopy. Carbon nanotubes are an ideal system to spectroscopically investigate gating of the whole channel area as their Raman modes (e.g., Gmode, radial breathing mode (RBM) and 2D-mode) are significantly and reversibly reduced in 11 ACS Paragon Plus Environment


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intensity by doping and thus enable in situ charge carrier density mapping.55-57 Recording the G-mode intensity over the whole active area of the device without any applied voltage gives the distribution of the nanotubes below and next to the top electrode (see Figure 4a). The Raman signal is much larger on top of the bottom electrode (acting as a mirror) and attenuated below the top electrode. However, due to the use of very thin (20 nm) gold electrodes that are still conducting but semi-transparent, the collected signal is large enough to enable reliable peak fitting in the relevant areas for both the doped and undoped state. Only at the edges of the film, where the SWNT layer becomes very thin, the signal-to-noise ratio was too low for reliable fitting results in the doped regime (see Figure 4c). The G-mode intensity of the nanotube film was mapped with applied gate bias while the source and drain electrodes were both grounded. As the measurements were performed in air (for transfer characteristics see Figure S3b, Supporting Information), the undoped state was achieved at a positive gate bias (no electron doping was observed) and hole doping occurred at negative gate bias. The reduction and recovery of the G-mode Raman signal took less than ten seconds, as determined by continuous single spot measurements in the middle of the sample (see Figure S4, Supporting Information). To ensure full ion movement and equilibration in thick films Raman mapping was performed at a positive (negative) gate bias of +2 V (-2 V) for the undoped (doped) state after a two minutes hold time. The resulting map of the ratio of the G-mode peak areas in the doped vs. undoped state indicates a very uniform intensity drop to less than 15 % of the original value even about 100 μm away from the electrode edge (see Figure 4b). The same observations as shown here for an electrode width of 200 µm were reproduced for an electrode width of 100 µm and for different thicknesses of SWNT films between 50 nm and 600 nm (see Figure S5, Supporting Information). We can conclude that the whole SWNT film is electrolyte-gated efficiently and fairly uniformly through ion movement and creation of electric double layers around the nanotubes independent of the 12 ACS Paragon Plus Environment

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thickness of the device and even at long distances from the electrode edge. The residual wrapping polymer poly[(9,9-dioctylfluorenyl-2,7-diyl)-alt-co-(6,6’-(2,2’-bipyridine))] PFOBPy of the nanotube dispersion may be helpful to create a matrix between the nanotubes for the electrolyte ions to move through the network while being non-conducting itself. No additional filler material and its subsequent removal58 to achieve larger porosity for ion penetration was necessary in this case.

Figure 4: (a) Raman map of G-mode peak area for the whole device. Note the lower but still sufficient signal below the top electrode and increased signal on top of the bottom electrode. (b) Map of the G-mode peak area ratio in the doped and undoped state. (c) Representative spectra in doped and undoped state at different positions of the device: Next to top electrode and above bottom electrode (A), in the active channel area (B) and at the edge of the (6,5) SWNT film (C).



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As shown above, the electrochemical nanotube doping is uniform and independent of film thickness. However, the resulting on-conductances and current densities should depend directly on the total SWNT film thickness (i.e., the channel length) and thus also the number of tubetube junctions in vertical direction. Figure 5 shows the transfer characteristics and current densities as a function of nanotube film thickness from 51 nm to 609 nm. As expected the current densities decrease almost linearly with increasing film thickness up to about 200 nm before leveling off for thicker SWNT films, probably due to parasitic currents in lateral direction. Very thick films (> 300 nm) also start to show significant current hysteresis. Depending on processing conditions electron trapping by residual water can occur considering that the AJ printing is performed in air.59 When the SWNT layer is very thick, water might not be completely removed by annealing. Thinner SWNT films are also preferable to reduce material cost. However, films with a layer thickness of less than 50 nm often showed sourcedrain shorts which is attributed to penetration of the porous SWNT film by the evaporated metal. We did not observe any source-drain shorts for SWNT film thicknesses of more than 50 nm. For best performance and minimum material consumption, the SWNT layers should thus exhibit a thickness of 60 to 200 nm. In addition to varying the thickness of the active layer we also studied different lateral channel dimensions to understand the impact of lateral parasitic currents. Two different widths for the top and bottom electrodes resulting in overlap areas of 0.01 mm² or 0.04 mm² were employed. Both devices showed similar current densities for large film thicknesses (> 300 nm) but deviated for thinner films (see Figure 5b). This indicates that in addition to the vertical, area-dependent currents there are also lateral stray currents at the circumference of the active area. For further investigation of the role of these lateral currents, we kept the top (drain) electrode widths Wd constant at 47 or 140 µm while varying the bottom electrode (source) width Ws from 50 to 500 µm and thus not only the overall area but also the circumference of 14 ACS Paragon Plus Environment

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the active device. The current-voltage characteristics of the resulting VEGTs (see Figure 5c) showed a decrease of nominal current densities with both, larger top (Wd) and larger bottom (Ws) electrodes (see Figure 5d).

Figure 5: Dependence of transport parameters on the device dimensions: (a) Transfer characteristics of VEGTs with different (6,5) SWNT film thickness for a constant active area (A) of 0.04 mm² and (b) corresponding thickness-dependent current densities at different source-drain biases and for different source-drain overlap areas. (c) Transfer characteristics for VEGTs with different widths of the bottom source electrodes and constant width of the top electrode (Wd = 140 µm) and film thickness (50 nm). (d) Corresponding current densities vs. bottom (source) electrode width (Ws) for two different top electrode widths (47 µm and 140 µm) and source-drain bias (-1 V and -100 mV). 15 ACS Paragon Plus Environment


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The vertical device architecture inherently supports two different pathways for lateral currents, one depending on the bottom electrode width Ws and one depending on the top electrode width Wd (see schematic depiction in Figure S6a-c, Supporting Information). Due to the profile of the top electrode and the SWNT film (see Figure S6d-e, Supporting Information), especially the current at the edge of the top electrode contributes significantly to the onconductance of the device. Linear extrapolation of the data points shows that at a theoretical bottom electrode width of Ws = 0 µm a significant current could still be observed, i.e., the contribution by lateral currents. The same analysis can be carried out for the edge of the bottom electrode by extrapolating the data to Wd = 0 µm (see Figure S7a-b, Supporting Information). These currents are consistent with short-channel lateral FETs around the edge of the electrodes and account for 10 % (for small electrode overlap of 47 x 50 µm²) to up to 49 % (for large electrode overlap of 142 x 500 µm²) of the total current. As the circumference is larger with respect to the device area, devices with narrower electrodes exhibit a larger current density. In addition, the off-currents increased with overlap area, which could be attributed to residual metallic nanotubes not detectable by Raman measurements. The larger the electrode overlap, the more likely it is that one or few metallic SWNTs bridge the channel and thus contribute to the off-current (note, their impact on the on-current in dense networks is negligible). The best device performance (on-current per device area) could hence be achieved by exploiting these lateral currents in addition to the vertical currents, i.e., reducing the electrode overlap area via very thin bottom electrodes and rather broad top electrodes. In addition to the actual length of the electrode edges, the overall area where nanotubes were deposited might also influence the lateral transport in these VEGTs. We fabricated transistors with constant electrode dimensions (Ws = Wd = 200 µm) and printed squares of (6,5) nanotube films with edge lengths of 200 to 800 µm to test this possibility. Although these devices showed 16 ACS Paragon Plus Environment

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an increased off-current, probably due to higher m-SWNT content, the extraction of oncurrents from these devices was still possible. The on-current values varied in a range of 0.15 to 0.35 mA at a source-drain bias of -10 mV but there was no correlation with the printed nanotube area (see Figure S8, Supporting Information). Clearly, lateral transport is limited to the first few micrometers next to the electrode edges and excess semiconductor coverage does not have a positive or negative impact on the current density. For the sake of material conservation, the nanotube film area should thus be as small as possible but exceed the actual electrode overlap as much as necessary to compensate for the limited alignment accuracy. Ultimately, the vertical device architecture should reduce the required space for a given drive current compared to typical lateral geometries, e.g., with interdigitated electrodes. Here we compare a VEGT (thickness 51 nm, SWNT film volume approx. 8000 µm³) to conventional electrolyte-gated SWNT transistors with a channel width of 10 mm and channel lengths of 2 or 5 µm and a printed SWNT network of 5 to 10 nm thickness (total SWNT film volume approx. 4500 to 9000 µm³). As shown in Figure 6a, the device performances for both device architectures are fairly similar and exhibit steep subthreshold swings of less than 200 mV/dec. While the vertical geometry shows a factor of two higher on-conductance, it also exhibits increased gate leakage. This gate leakage can be largely attributed to capacitive charging and the ionic conductance between source/drain and gate electrode. We used a very large common gate electrode for all devices on one substrate (Agate = 19 mm²) to ensure a sufficiently large counter electrode area for gating the whole three-dimensional SWNT network. However, this electrode area could be adjusted and reduced as necessary. For the thin (6,5) SWNT film of the lateral devices, a much smaller gate electrode (Agate = 2.4 mm²) was used. Despite the higher absolute currents in the VEGT, the total active channel area was only 0.04 mm² (for exact printing only in the overlap region) or 0.16 mm² (for printing with a clearly sufficient margin of 100 µm on all sides for alignment) in comparison with 0.9 mm² for the lateral transistor with 17 ACS Paragon Plus Environment


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interdigitated electrodes (see Figure 6b). While the footprint of the VEGT is smaller by a factor of 5 to 20 than the lithographically structured lateral counterpart, the volume of the SWNT film and thus required amount of (6,5) SWNTs are comparable for optimized film thicknesses. Importantly, unlike the short-channel lateral FETs, the vertical geometry is fully compatible with printing processes and needs neither precise alignment nor patterning processes for critical lateral dimensions of less than 10 µm. A fully-printed lateral transistor would require even more space as the electrode width as well as the channel length would have to be larger. Assuming an electrode width of 50 µm and a channel length of 20 µm the active area would already amount to 1.2 mm² even without increasing the channel width to compensate for the longer channel length to reach the same on-currents.

Figure 6: (a) Comparison of transfer characteristics of electrolyte-gated transistors with lateral channel and interdigitated electrodes (channel length L = 2 µm and L = 5 µm, channel width W = 10 mm, SWNT layer thickness 5-10 nm) and a vertical channel (Wd = Ws = 200 µm, 18 ACS Paragon Plus Environment

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SWNT layer thickness 51 nm) (b) To scale drawings of active device areas to enable size comparison.

As a proof of concept, we further realized the same device architecture with two different materials for solution-processed instead of the previously used evaporated gold electrodes: airbrush-sprayed mixed SWNTs (see Figure S9, Supporting Information) and aerosol-jet printed silver nanoparticles. Due to the limited sheet conductance of the sprayed SWNT films and poor contacts between the two networks,54 we focus here on the VEGTs with printed silver electrodes. Silver nanoparticles were AJ printed from a commercially available ink and the device structure was optimized for short lead lengths (≤ 1 mm). The electrodes were printed as several passes of a single line resulting in a width of 100 to 200 µm and a thickness of 70 to 80 nm. As the printing parameters were not optimized, high drying edges of around 1 µm appeared as a result of the coffee ring effect, however, these did not influence the device performance negatively. After each Ag ink printing step, the substrates were annealed overnight in air at 130 °C to achieve optimal conductance of the electrodes. The (6,5) SWNTs were deposited on the bottom electrode as described before with a thickness of 150 to 200 nm, followed by printing of the top silver electrode. Shorts between the silver electrodes were avoided by a rather large SWNT printing area of 400 x 400 µm². Figure 7a shows an optical micrograph of such an all-aerosol-jet printed device before deposition of the iongel. Here, we spin-coated the iongel, but printing of iongels has been demonstrated before.60 The transfer curves (Figure 7b) of these VEGTs reveal some residual metallic SWNTs but the off-currents stay reasonably low (less than 2 µA at Vds = -10 mV), thus leading to an on/off-ratio of up to 2∙103 at low source-drain bias. In the ambipolar regime, extremely high on-current densities of up to 570 A cm-2 at Vds = -1 V and Vg = -2 V are reached. 19 ACS Paragon Plus Environment


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In addition to rather large lateral currents at the high drying edges of the bottom electrode, we additionally attribute the higher on-currents (compared to the previously used evaporated gold electrodes) to the superior wetting properties of the liquid silver ink. When printed onto the rough and thick SWNT layer the silver ink can more easily form a closed film (including the edges of the nanotube network) than the evaporated gold and thus form better contacts with the nanotubes. The thin evaporated top gold layer is also prone to discontinuities due to the rough layer underneath. This is not an issue for the printed Ag nanoparticles. An on-off switching cycle (Figure 7c) again shows that the VEGTs turn-on within seconds, but subsequent de-doping takes rather long due to the slow ion movement at low gate voltages and thus small effective electric fields. The demonstrated VEGTs with silver nanoparticle ink serve as an example for employing the vertical structure in all-printed devices. While achieving relatively high current densities and reasonable on/off-ratios, the performance could be further improved by optimizing the printing process or switching to other, e.g., gold nanoparticles based, inks to further reduce sheet and contact resistance.61

Figure 7: (a) Optical micrograph of VEGT with aerosol-jet printed Ag nanoparticle electrodes and (6,5) SWNTs (b) Transfer characteristics for this VEGT at different source-drain voltages.


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(c) Switching behavior for voltage steps from initially Vg = 0 V to the on-state at Vg = -2 V and then the off-state at Vg = 0.5 V.

CONCLUSION We have demonstrated a vertical electrolyte-gated transistor structure featuring aerosol-jet printed dense semiconducting carbon nanotube films that exhibits device performances similar to lateral FETs with short (i.e., 2 to 5 µm) channels, but without the limitations of printing resolution or alignment accuracy. The network of polymer-sorted (6,5) SWNTs sandwiched between source and drain (i.e., bottom and top) electrodes as the semiconductor was confirmed to be partially three-dimensional, porous and fully electrolyte-gated by conductive AFM and Raman measurements. Varying the thickness and lateral dimensions of the VEGTs revealed the presence of additional lateral current pathways that contribute to the device performance. The presented device geometry and dimensions are fully compatible with conventional printing techniques for all material layers as demonstrated by a VEGT with printed silver nanoparticle electrodes.

EXPERIMENTAL SECTION Preparation of s-SWNT ink. The (6,5) SWNT dispersion and ink were prepared as described previously.26, 48 Briefly, 0.38 g L-1 CoMoCAT™ raw material (Chasm Advanced Materials, SG65i) and 0.5 g L-1 of the wrapping polymer poly[(9,9-dioctylfluorenyl-2,7-diyl)alt-co-(6,6’-(2,2’-bipyridine))] (PFO-BPy, American Dye Source, MW = 34 kg mol-1) were mixed in toluene with a shear force mixer (Silverson L2/Air, 10 230 rpm) for 72 hours at 20 °C. Undispersed material was removed by centrifugation at 60 000 g (Beckman Coulter Avanti J 26XP ultracentrifuge) for 45 min. An additional centrifugation step for 60 min at 284 600 g 21 ACS Paragon Plus Environment


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(Beckman Coulter Optima XP ultracentrifuge with a swing-bucket rotor) was included to further purify the material and remove as many metallic SWNTs as possible. Vacuum filtration through a polytetrafluorethylene (PTFE) filter followed by washing of the SWNT filter cakes with tetrahydrofuran (THF) removed excess polymer. The filter cake was redispersed in pure toluene by bath sonication immediately prior to aerosol-jet printing. The final ink was adjusted to a (6,5) SWNT concentration of 3 to 4 mg L-1 (based on absorption measurements) and a terpineol concentration of 5 vol% for reliable printing properties. Aerosol-jet Printing of (6,5) SWNTs. An initial volume of 1 mL (6,5) SWNT ink was used for printing the semiconducting layer with an Aerosol Jet 200 Printer (Optomec Inc.). Ink temperature, sonication strength, and stage temperature were set to 20 °C, (530 ± 20) mA, and 100 °C, respectively. Dense and thick films were achieved with a 200 µm inner diameter ceramic nozzle by printing orthogonal layers of lines with a pitch of 25 µm at a carrier gas flow rate of 14-15 sccm and a sheath gas flow rate of 30 sccm. After deposition, the substrates were carefully rinsed with THF and isopropanol to remove residual polymer and terpineol and blowdried with nitrogen. Aerosol-jet Printing of Ag electrodes. Silver nanoparticle ink (EXPT Prelect TPS 50, #14-KM137, Clariant) was used as received in the AJ printer with a sonication strength of (550 ± 10) mA at 30 °C bath temperature. The carrier and sheath gas flow rates were adjusted to 40 sccm and 50 sccm, respectively. Electrodes were printed as single lines with 2 passes at 5 mm s-1 stage speed. Annealing was performed on a hotplate at 130 °C overnight in air. FET fabrication. Bottom electrodes were deposited via electron-beam or thermal evaporation of chromium (2 nm) and gold (30 nm), or via AJ printing of silver nanoparticle ink on AF32eco Thin Glass (SCHOTT AG). Patterning of the gold electrodes was achieved either via standard double-layer resist photolithography and post-evaporation lift-off in N-methyl-2pyrrolidone or via stainless steel shadow masks. AJ printing of Ag ink resulted in directly 22 ACS Paragon Plus Environment

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patterned contacts. The (6,5) SWNT layer was aerosol-jet printed on top of these electrodes covering a sufficiently large area to avoid shorts between top and bottom electrodes. Top electrodes were deposited either through shadow masks by thermal evaporation of 20 nm gold or by AJ printing of Ag nanoparticle ink. The devices were annealed in dry nitrogen at 300 °C for 60 min (200 °C for 120 min for printed Ag electrodes) followed by spin-coating (2000 rpm, 30 s) of a solution of 1-ethyl-3-methyl-imidazolium-tris(pentafluoroethyl)-trifluoro-phosphate ([EMIM][FAP]) and poly(vinylidene fluoride-co-hexafluoropropylene) (P(VDF-HFP), Sigma Aldrich, MW ~400 kg mol-1) in acetone (4:1:14 by mass) and annealing for at least 60 min at 80 °C to form the iongel. Characterization. A Bruker Dimension Icon atomic force microscope (AFM) was used for topography measurements in tapping or ScanAsyst® mode and for conductive AFM measurements in PeakForce TUNA® mode at a sample bias of 1 V. Film thicknesses were determined with a Bruker DektatXT stylus profiler. Current-voltage measurements were performed with an Agilent 4156C semiconductor parameter analyzer in dry nitrogen. Absorbance spectra were collected with a Cary 6000i absorption spectrometer (Varian Inc.) and Raman spectra with a Renishaw inVia Reflex confocal Raman microscope (532 nm and 633 nm excitation laser), respectively. The Raman microscope was also used to acquire spectral maps (streamline mode, 50x long-working distance objective, 1.3 to 2 µm step size) of the whole active device area in the doped (Vg = -2 V) and undoped (Vg = 2 V) state by applying a bias to the gate electrode while source and drain were both grounded.



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ASSOCIATED CONTENT Supporting Information. Device dimensions, SWNT characterization (Raman and absorbance spectra), additional electrical characterization, time-dependent Raman quenching, Raman mapping of devices with different film thickness, evaluation of lateral currents, influence of printing area on device performance, VEGTs with spray-deposited TUBALL™ SWNT electrodes. PDF available online free of charge.

AUTHOR INFORMATION Corresponding Author *[email protected]

ACKNOWLEDGEMENT A.K. thanks the DAAD-RISE Germany program. T.M.H. received funding from the European Union’s Horizon 2020 research and innovation program under the Marie Skłodowska-Curie grant agreement No. 707644 (2D-EG-FET). J.Z. thanks the Struktur- and Innovationsfonds Baden-Württemberg for large equipment funding.


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TABLE OF CONTENTS FIGURE


Vertical Electrolyte-Gated Transistors Based on Printed Single-Walled

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