pubs.acs.org/NanoLett
Vertical InAs Nanowire Wrap Gate Transistors with ft > 7 GHz and fmax > 20 GHz M. Egard,*,† S. Johansson,† A.-C. Johansson,‡ K.-M. Persson,§ A. W. Dey,§ B. M. Borg,† C. Thelander,†,‡ L.-E. Wernersson,§ and E. Lind†,‡ †
Solid State Physics, Lund University, Box 118, 221 00 Lund, Sweden, ‡ Qumat Technologies AB, 222 24 Lund, Sweden, and § Electrical and Information Technology, Lund University, Box 118, 221 00 Lund, Sweden ABSTRACT In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, ft, extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, fmax, is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires. KEYWORDS Nanowire, MOSFET, InAs, high-frequency characterization, vertical geometry
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t is well established that continued scaling of the gate length of field-effect devices severely deteriorates the electrostatic control of the conducting channel. This has led to the development of devices such as FINFETs, Trigate transistors,1 and ultimately gate-all-around devices (GAA).2 Recently, we have reported on vertically grown and processed InAs nanowire (NW) MOSFETs3 (metal-oxidesemiconductor field-effect transistors), with a symmetrical GAA geometry. We now report on high-frequency NW MOSFETs that are fabricated from vertically standing nanowires on a semiinsulating substrate. To contact the devices, we have developed a fabrication technique that makes it possible to implement wrap around contacts at all three terminals of the NW transistor. Other techniques of performing RF or DC measurements on GAA nanowires/nanotubes may be found in the literature.2,4-9 The position of the MOSFETs are defined by a lithography step prior to the epitaxial growth of the InAs nanowires. This makes it viable to integrate high-frequency circuits consisting of the device reported in this paper. The vertical fabrication techniques also offers interesting features, such as the ability to scale the gate length without the use of lithography,10 the possibility of integrating III/V channel materials on Si,11 and the option to integrate highly lattice mismatched heterostructures, to boost the performance of the device.12 In this paper, we report on the fabrication of 100 nm gate length, vertical InAs nanowire MOSFETs. The performance of the devices is evaluated by standard S-parameter mea-
surements, which enables us to deduce the current gain and maximum power gain of the device. A small signal equivalent model of the NW MOSFET is also extracted from the measurements. Fabrication. To form arrays of nanowires, Au seed particles are first defined on a semi-insulating InP〈111〉B substrate, by electron beam lithography (EBL), evaporation of Au, and lift-off. Nanowires are grown by metal organic vapor phase epitaxy (MOVPE) at 420 °C, using trimethylindium (TMIn), arsine (AsH3), phosphine (PH3), and tetraethyltin (TESn) precursors. To facilitate nanowire nucleation, a 50-100 nm undoped InP nanowire is grown prior to the InAs nanowire growth. The doping level is set by the TESn flow to give a constant n-type (Sn) doping throughout the InAs nanowires. After nanowire growth, a source metal layer is deposited by sputtering of Al and W. The metal thickness on the side facets of the NWs is estimated to be one-third of the thickness on the planar surfaces. Source pads are formed by ultraviolet (UV) lithography and dry etching of W in a reactive ion etching (RIE) system using a SF6 and Ar gas mixture. This is followed by wet etching of Al as well as the thin InAs layer that was nucleated on the InP surface during growth of the NWs. The source metal is etched back to wrap around only the lower part (100-300 nm) of the nanowires. This is done by spinning an organic resist and dry etching it in oxygen plasma to the desired thickness. This is followed by RIE of W, in a SF6 and Ar gas mixture, using the resist as an etch mask. The Al film that protects the nanowires from being damaged by the plasma is sequentially removed from the nanowires by wet etching. Figure 1a shows a SEM image of a NW array with the bottom source contact.
* To whom correspondence should be addressed. E-mail: mikael.egard@ ftf.lth.se. Received for review: 09/21/2009 Published on Web: 02/04/2010 © 2010 American Chemical Society
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DOI: 10.1021/nl903125m | Nano Lett. 2010, 10, 809–812
FIGURE 2. Output characteristics for different wrap-gate voltages.
FIGURE 1. (a) Nanowire array with the bottom source ohmic contact, consisting of Al and W, wrapping around the NWs. (b) Schematic cross-section of the device, showing the thickness of the different layers and illustrating the device input capacitances. The gate length is about 100 nm. (c) Optical image of a completed device. The enlarged portion of the picture shows what is defined as the transistor cell.
FIGURE 3. Transfer characteristics, showing the DC drive current and the DC extrinsic transconductance.
acts as the drain, the intermediate metal layer that wraps around the wire is the gate, and the metal contact that wraps around the bottom part of the wire is denoted as the source. The output characteristics of the realized vertical InAs nanowire MOSFET, in common source configuration, is shown in Figure 2, and the transfer characteristics is shown in Figure 3. The measurements are performed by on-wafer probing. From Figure 2 it is evident that the device is of n-type and operates in depletion mode, with a reasonably high drive current. Figure 3 shows that the peak extrinsic transconductance, after normalizing to the total NW circumference, is 0.15 S/mm. We attribute the lower value of the normalized transconductance, as compared to our previous work,3 mainly to the 3 times lower value of the permittivity of Al2O3, as compared to HfO2. It is also possible that the density of trap states at the oxide semiconductor interface is altered by the Al2O3, which could explain the poor subthreshold characteristics. A second effect that needs to be considered is that too high a doping level of the channel could lead to hole accumulation at the surface of the NW, before the wire is fully depleted from electrons. For our 50 nm wire diameter device, this would correspond to a channel doping of about 3.5 × 1018 cm-3.13 It is also possible that the gate is not operating properly on a few nanowires in the transistor cell. High-Frequency Characterization. S-parameter measurements were made on a coplanar ground-signal-ground 50 Ω pad structure with a pitch of 100 µm, as illustrated in Figure 1c. The measurements were performed from 60 MHz to 20 GHz using an Agilent E8361A network analyzer and
An 8.8 nm-thick Al2O3 film is deposited as gate dielectric by atomic layer deposition (ALD) at 250 °C, using trimethylaluminum and H2O as precursors (80 cycles). On top of the gate dielectric, an organic dielectric is used as insulating spacer between the source and gate metals. Source via openings are made by UV lithography and the dielectric is etched back to about 350 nm, using oxygen plasma. Processing of the wrap-all-around Al/W gate contact is similar to that of the bottom source contact. The resulting gate length for this sample is about 100 nm. A 350 nm organic dielectric with source and gate via openings is used as an insulating spacer between the gate and drain metal. The spacer also acts as an etch mask, when removing the gate dielectric from the top segment of the nanowires and in via openings, by using wet etching. The contact surfaces are then exposed to diluted NH4Sx and a thick top metal layer is deposited by sputtering of Ti and Au. Finally, the drain, gate, and source pads are formed by UV lithography and wet etching. Figure 1b shows an illustration of the cross-section of the complete nanowire MOSFET, and Figure 1c shows an optical image of the standard 50 Ω pad layout. DC Characterization. The device considered in the following sections consists of about 70 nanowires with a diameter of 50 nm, as determined by SEM inspection. The illustration in Figure 1b shows that the upper metal contact © 2010 American Chemical Society
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DOI: 10.1021/nl903125m | Nano Lett. 2010, 10, 809-–812
TABLE 1. Simulated and Measured Nanowire Capacitances [fF] simulated Cgg, i 6.4
Cgs, mm 18
Cgd, mm 10
Cgs, mw 3.5
Cgd, mw 3.5
Cgg 41.4
measured Cgs 25
Cgg 42
dependent output conductance.14,15 This will be further investigated. An equivalent small signal model representing the nanowire MOSFET is presented in Figure 4b. It was extracted from the measured S-parameter data using an analytical approach, similar to the one reported in.16 h21, calculated from the extracted model, is represented by the dashed trace in Figure 4a, to show the agreement between the model and the measurement. Neglecting the conductive current path through Rgs and Rgd, makes it possible to derive an analytical expression for ft (1),17 where Cgg ) Cgs + Cgd, which include both the intrinsic and parasitic contributions
FIGURE 4. (a) Unilateral power gain, U, and current gain, h21. The dashed line represents the calculated current gain of the model presented in Figure 4b. (b) Small-signal equivalent circuit deduced from measured S-parameters. The currents ids and igs, which are indicated in the drawing of the circuit, are used to define the current gain as h21 ) ids/igs.
Cgg 1 ) (1 + (Rs + Rd)gds) + (Rs + Rd)Cgd 2πft gm
the port power was -27 dBm. DC bias was supplied through a bias tee internal to the vector network analyzer. A twoport LRRM (load-reflect-reflect-match) calibration was performed using a Cascade Microtech 101-1908 impedance standard substrate. The device response was deduced from the measured data by de-embedding using on-chip open pad structures, which may be modeled as a π network consisting of three capacitors. The size of the capacitors are measured to be 16 fF between drain and source, 14 fF between gate and source, and 0.6 fF between gate and drain. Off-chip calibration, combined with pad-de-embedding is known to work well for the frequencies considered in this paper. The device is defined as a transistor cell (indicated in Figure 1c) consisting of the source and drain metal above the nanowires, as well as the gate metal that extends to the gate via. Measurements of the current gain h21 ) ids/igs and the unilateral power gain U, are presented in Figure 4a. U is defined as the maximum power gain of a transistor to which a reactive network has been added in order to set the feedback to zero, which would make the transistor stable at all times. A low frequency current gain of more than 30 dB is obtained together with a unity current gain cutoff frequency (ft) of 5.6 GHz, and a maximum oscillation frequency (fmax) above 20 GHz. The highest ft measured among nominally identical devices on the same chip is 7.4 GHz. To the author’s knowledge, these RF measurement results are the first reported for vertically processed nanowire transistors. h21 shows nearly ideal behavior with a slope of 20 dB/decade. The nonideal behavior of U is most likely due to impact ionization or interband tunneling, which causes the output of the device to have an inductive behavior with a frequency © 2010 American Chemical Society
Cgd 17
(1)
Here, it is seen that ft is to a large extent limited by Cgs and Cgd, which for the devices presented in this paper is limited by the parasitic capacitance between the gate and drain, and between the gate and source. Table 1 lists the size of the different contributions, where the intrinsic gate capacitance Cgg,i has been calculated using a self-consistent Poisson Schro¨dinger solver. The parasitic capacitances, which may be divided into two parts, the metal-wire capacitance (Cgs,mw and Cgd,mw) and the metal-metal capacitance (Cgs,mm and Cgd,mm), have been estimated using analytical expressions and the 3D finite element solver COMSOL. The geometry of the different capacitive contributions are illustrated in Figure 1b. The measured gate-source and gatedrain capacitances are also included in Table 1. Good agreement between the measured and modeled data is obtained. In the present implementation, the gate-source and gatedrain overlap is 196 and 110 µm2, respectively, while the area covered by wires is only 12.5 µm2. The metal-metal parasitic may be decreased by having less excess pad area surrounding the wires. The metal-wire capacitance may be decreased by making the wire pattern denser, as a short wire spacing will cause the electric field, originating from the gate metal, to be screened by the conductive wires. Hence, ft is in the present design mainly limited by the resolution of the optical lithography process used, when defining the pad layout. Another factor that needs to be considered when designing vertical transistor is the gate-source and gate-drain separation. Increasing these distances would decrease the corresponding parasitic capacitances, and hence increase ft, but it would also increase Rs and Rd, which would decrease f t. 811
DOI: 10.1021/nl903125m | Nano Lett. 2010, 10, 809-–812
(SSF), by the Knut and Alice Wallenberg Foundation, by the Swedish Research Council (VR), by VINNOVA, and by the EU-project NODE 015783. REFERENCES AND NOTES (1)
(2) (3) (4)
FIGURE 5. Distribution of measured ft among 22 nominally identical devices, on the same chip.
(5) (6)
To show the spread among nominally identical devices fabricated on the same chip, ft were measured for a total of 22 devices. The result is shown in Figure 5. Conclusion. In this letter, we reported on a fabrication process that allows for the implementation of vertical InAs nanowire MOSFETs. The devices fabricated with this technique are high-frequency compatible. This, together with the possibility to define the position of the nanowire transistors by lithography, makes it viable to implement high-frequency circuits using the technique. The device were evaluated by measuring the S-parameter response. The result is a ft of 7.4 GHz and a fmax higher than 20 GHz. We also conclude that the device performance is limited by the parasitic source, gate, and drain capacitances. Decreasing the pad area, which in the current implementation is limited by the resolution of the optical lithography process used, will increase both ft and fmax.
(7)
(8) (9) (10)
(11)
(12) (13)
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Acknowledgment. The authors thank colleagues within the Department of Electrical and Information Technology as well as within the department of Solid State Physics at Lund University for stimulating discussions. This work was supported by the Swedish Foundation for Strategic Research
© 2010 American Chemical Society
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