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Vertical Organic Field-Effect Transistors for Integrated Optoelectronic Applications Hyeonggeun Yu, Zhipeng Dong, Jing Guo, Doyoung Kim, and Franky So ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.6b00182 • Publication Date (Web): 11 Apr 2016 Downloaded from http://pubs.acs.org on April 12, 2016

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ACS Applied Materials & Interfaces

Vertical Organic Field-Effect Transistors for Integrated Optoelectronic Applications Hyeonggeun Yu, Zhipeng Dong1, Jing Guo1, Doyoung Kim2, and Franky So*

Dr. H. Yu and Prof. F. So*, Department of Materials Science and Engineering, North Carolina State University, Raleigh, NC 27606, USA E-mail: [email protected] Z. Dong1 and Prof. J. Guo1, Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611, USA Prof. D. Kim2, Department of Materials Science and Engineering, University of Florida, Gainesville, FL 32611, USA; Current address: School of Materials Science and Engineering, Oklahoma State University, Tulsa, OK 74106, USA

ABSTRACT Direct integration of a vertical organic field-effect transistor (VOFET) and an optoelectronic device offers a single stacked, low power optoelectronic VOFET with high aperture ratios. However, a functional optoelectronic VOFET could not be realized because of the difficulty in fabricating transparent source and gate electrodes. Here, we report a VOFET with on/off ratio up to 105 as well as output current saturation by fabricating a transparent gate capacitor consisting of a perforated indium tin-oxide (ITO) source electrode, HfO2 gate dielectric, and ITO gate electrode. Effects of the pore size and the pore depth within the porous ITO electrodes on the on/off characteristic of a VOFET are systematically explained in this work. By combining a phosphorescent organic light-emitting diode with an optimized VOFET structure, a vertical organic light-emitting transistor with luminance on/off ratio of 104 can be fabricated.

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KEYWORDS Vertical field-effect transistor, organic light-emitting transistor, Schottky diode, on/off ratio, current saturation

INTRODUCTION Vertical field-effect transistor (VFET) is a class of field-effect transistors where the gate electrode, gate dielectric, source electrode, channel, and drain electrode are stacked vertically. Compared to conventional metal-oxide-semiconductor FETs (MOSFETs), VFETs feature high output currents at low operation voltages due to the extremely short channel lengths in nanometer scale. While the performance of organic field effect transistors is inferior compared to that of the inorganic counterpart, organic channel VFETs (VOFETs) are promising due to the short channel lengths, low cost, easy fabrication, and potential use for flexible device applications1-14. In VOFETs, fabrication of a porous source electrode is critical because charge injection from the source electrode to the channel layer is controlled by the gate via the porous electrode region. Various techniques have been employed to fabricate a porous source electrode for VOFETs and this includes deposition of an ultra-thin metal film1, 3-4, a mesh electrode patterned by lithographic process5-6, or graphene-organic heterojunctions for flexible VOFET applications7-14. Another great advantage of VOFETs is that the device can readily be integrated with a lightemitting device or a photodetector to realize integrated optoelectronic VOFETs. These optoelectronic devices require transparent electrodes either on the top side or at the bottom side for light sensing or light emission in or out of the devices. For example, to integrate with


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an organic light emitting diode to realize a vertical organic light-emitting transistor (VOLET) with a bottom opaque source/gate, the top drain electrode must be transparent. Since ITO cannot be used as a top electrode in an organic light-emitting diode (OLED), a semitransparent ultra-thin metal film with a refractive index-matching layer is usually used in the top emitting device15-16, thus limiting the transmittance and hence the device efficiency. In order to circumvent this issue, a top gate, bottom-emitting device structure was demonstrated on glass substrate with an ultra-thin Al film as the source electrode and a thermally evaporated LiF layer as the gate dielectric4. However, the gate leakage current was very high because LiF is not a good gate dielectric material. To address this issue and demonstrate a versatile platform for optoelectronic applications, here we report VOFETs with indium-tin oxide (ITO) gate and source electrodes. Figure 1a shows the structure of the VOFET in this work having the following structure: ITO gate electrode/HfO2 gate dielectric/porous ITO source electrode/C60 channel layer/Al drain electrode. As observed in Figure 1b, the transmittance of porous ITO/HfO2/ITO/glass is over 80 % in visible spectrum (10% of absorption from the soda-lime glass substrate and 10% of absorption from the ITO/HfO2/ITO gate capacitor. Since ITO is transparent and commonly used for a bottom electrode in many optoelectronic devices, these VOFET can readily be integrated with many optoelectronic devices such as organic light-emitting diodes (OLEDs) or photodetectors to realize optoelectronic VOFETs.

RESULTS AND DISCUSSIONS To demonstrate a VOFET, fabrication of a porous source electrode is essential because charge injection from the source electrode to the channel layer is modulated by gating the porous source electrode through the gate electrode. Control of porosity is important because



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the equilibrium potential distribution of the channel layer inside the porous region is expected to change with the pore size, and hence the porosity can significantly affect the current modulation of a VOFET. This point will be explained further in the next section. Previously reported VOFETs showed a random pore size and irregular pore distribution within the source electrode, resulting in transistors with low on/off ratios1, 5. To address these issues, we make use of a self-assembly of Langmuir-Blodgett nano-spheres as a shadow mask to produce a close-packed nano-pore array on top of an ITO film as observed in the scanningelectron microscope (SEM) image as shown in Figure. 1c. The pore size and the pore density can be controlled either by regulating the oxygen plasma etching conditions (Figure. S2) or choosing a different size of nano-spheres (Figure. S3). In addition to the requirement of porosity, the source electrode in VOFETs need to form a high Schottky barrier to ensure a low off current in the device. Here, C60 is chosen as an nchannel material because of a high electron mobility and a high energy level offset between the lowest unoccupied molecular orbital (LUMO) level of C60 and the Fermi level of ITO17. Figure. 1d-1i explains schematically the current modulation mechanism of a VOFET in this work. Under zero gate bias and a constant reverse source-drain bias, the large Schottky barrier at the porous ITO/C60 interface suppresses electron injection from the porous ITO electrode to the C60 channel layer as described in the Figure. 1d-1f. On the other hand, under a positive gate bias with the same source-drain bias, electron accumulation at the HfO2 dielectric/C60 interface decreases the potential energy of the C60 layer as described in Figures 1g and 1h. This induces a strong band bending in the C60 layer near the porous ITO region, and the Schottky barrier width in the vicinity of the HfO2/C60 interface becomes significantly narrower, facilitating electron injection from the porous ITO electrode to the C60 layer (Figure 1i).


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Figure. 2a illustrates the transfer characteristic of a representative VOFET at VDS = 3 V with the average pore size of 150 nm. The off current at VGS = 0 V is 1.5 × 10-3 mA/cm2, which is similar as the reverse current measured from the porous ITO/C60/Al Schottky diode (Figure. S4). On the other hand, the on current (black line) at VGS = 10 V reaches 25 mA/cm2 resulting in an on/off ratio of 1.6 × 104, while the gate leakage current (green line) stays almost 3 orders of magnitude lower than the on current. The hysteresis observed in the cyclic transfer curve is probably due to the existence of hydroxyl charge traps on HfO2 surface generated during the colloidal lithography process which has been observed in other HfO2 films18-20. The cyclic transfer curve does not shift after consecutive sweeps as shown in the Figure. 2a, indicating that charge trapping-detrapping is fully reversible. It should also be noted that increase in the source-drain voltage of VOFETs would increase the off current as well as the on current, resulting in a similar on/off ratio as function of a source-drain voltage2, 27. In order to form a large Schottky barrier between a porous ITO film and a C60 layer, the porous ITO film was ultra-violet ozone (UVO)-treated to increase its work-function21. As shown in Figure. 2a, the off-current of the device without UVO treatment (blue line) is increased by 3 orders of magnitude due to the formation of a smaller Schottky barrier at the ITO/C60 interface, resulting in a low on/off ratio. These results indicate that Schottky barrier formation at the source/channel interface is very important to the VOFET device performance. Figure. 2b shows the output characteristic of a VOFET in Figure. 2a. In previous works, output current saturation was not usually observed in VOFETs due to the short vertical channel lengths1, 22, which is a problem in realizing a functional VOFET driver. In this work, 1 µm-thick C60 channel layer was used and this thickness leads to the saturated output currents due to the space charge effect in the C60 channel layer. Since the operation of VOFETs is due to band bending of the C60 at HfO2/C60 interface, the



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pore size should affect the equilibrium potential distribution of C60 within the porous region and hence the charge injection at the ITO/C60 Schottky junction. To verify the device operation mechanism, we investigated the effect of pore size on the transfer characteristic of the VOFETs. Figure. 3a-3c demonstrates the SEM images of a porous ITO electrode with different pore size controlled by oxygen plasma treatment. To eliminate the effect of pore density, the pore center-to-pore center distance was fixed at 1.1 µm. Figure. 3d shows the oncurrent density (JDS at VGS = 10 V and VDS = 6 V, black), the off-current density (JDS at VGS = 0 V and VDS = 6 V, white), and on/off ratio (blue) as a function of the pore size. As observed, the average off-current is gradually decreased as the pore size is increased. This is due to the fact that the off-current is due to the reverse current at the porous ITO/C60 Schottky junction and hence is proportional to the non-porous area of the ITO source electrode. The average oncurrent density, on the other hand, increases gradually as the pore size is increased from 40 nm to 150 nm and these results can be explained as follows. First, the total effective area of the lateral ITO/C60 interface where charge injection occurs is increased as the pore size gets bigger. Second, band bending of C60 becomes larger at the lateral ITO/C60 interface as the pore size is increased. To verify the pore size effect, device simulation was carried out by numerically solving the three-dimensional (3D) Poisson equation self-consistently with the current continuity equation23. Finite element method24 was used to discretize the 3D Poisson equation for the porous source electrode contact. The current term in the current continuity equation is expressed by the drift-diffusion equation, which is discretized using the Scharfetter-Gummel method25. The metal-semiconductor Schottky barrier height imposes the Dirichlet boundary condition in the Poisson equation. The tunneling current through the Schottky barrier can be computed from the Laudauer-Buttiker formula and is described in the current continuity equation as an equivalent generation term26. Figure. 3e shows the simulated conduction band profile of C60 at the bottom of a pore along the X direction


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marked in the device structure (VGS = 10 V and VDS = 6 V). The lateral ITO/C60 Schottky junction is located at X position = 0 nm and the Fermi level of ITO is at EC = 0 eV. As shown in the Figure 3e, the Schottky barrier width becomes gradually narrower due to an increased band bending of C60 as the pore size is increased from 40 nm to 575 nm. We interpret that the increase of the average on-current density in Figure. 3d is due to the decrease in the Schottky barrier width. It should be noted, however, that large pore size increases the series resistance of the porous ITO network and hence reduces the on-current density under a fixed VDS as observed in case of the pore size of 575 nm. Therefore, there is a trade-off of the pore size due to an increase of band bending and an increase of sheet resistance of the porous ITO network. To further investigate the pore size effect, we vary the pore depth by varying the porous ITO electrode thickness. Figure. 3f illustrates the on current density (JDS at VGS = 10 V and VDS = 6 V, black), the off-current density (JDS at VGS = 0 V and VDS = 6 V, white), and the on/off ratio (blue) as a function of a pore depth. As observed, the off-current is increased as the pore depth is increased due to the larger lateral ITO/C60 interface area, supporting that the offcurrent is proportional to the non-porous ITO area. On the other hand, the on-current is gradually decreased as the pore depth is increased. Based on our device simulation in Figure. 3g the conduction band profile of C60 at the center of a pore along the Z direction marked in the device structure (VGS = 10 V and VDS = 6 V), formation of a potential barrier is observed along the Z direction as the pore depth is increased. This is due to the fact that the potential energy of C60 is raised by the surrounding ITO as the pore depth is increased. The Schottky barrier width at the lateral ITO/C60 interface, on the other hand, does not change as the pore depth is varied as observed in the inset of Figure. 3g. Therefore, we conclude that the observed decrease in the on-current density in Figure. 3f is not due to a decrease in charge injection at the lateral Schottky interface but due to the effect of the potential barrier



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formation along the Z direction in the channel layer. Direct integration of a VOFET with an optoelectronic device offers many advantages over conventional optoelectronic devices with separate driving transistors such as inherently low power consumption, single stack device fabrication, and high pixel aperture ratios. Based on the optimized VOFET structure, we demonstrated a vertical organic light-emitting transistor (VOLET). Figure. 4a illustrates the device structure of a VOLET where a phosphorescent OLED is inserted between the C60 channel and the Al drain electrode of a VOFET. Figure. 4b shows the transfer curve of a representative VOLET. Under a constant VDS of 13 V and no gate bias, electron injection from the ITO source electrode is negligible while holes are injected from the Al drain electrode, resulting in negligible luminance (red line). At a positive gate bias over 1 V, on the other hand, the luminance increases to 170 cd/m2 due to the increased electron injection from the ITO source electrode recombining with the holes injected from the Al drain electrode, resulting in a high luminance on/off ratio of 104 at VGS = 6 V. Further enhancement of the luminance would be available by decreasing the C60 thickness, where 1 μm was used in this work to avoid any possible short path formed during the porous ITO fabrication. The inset in Figure. 4a shows the light emission image of a pixel area with and without applying a gate bias under VDS = 13 V. It is noted that an output current saturation is not observed in the Figure. 4c because a small hole blocking barrier at TcTa/Bphen interface causes hole leakage currents with increased source-drain voltage27. In addition to the light-emitting transistor, we demonstrated that a novel vertical nearinfrared (NIR) phototransistors could be fabricated using the VOFET27 architecture with measured detectivity of 1.2 × 1013 Jones. Compared to the lateral type NIR phototransistors28, 29

, the vertical NIR phototransistor yielded significantly faster response due to the photo-

gating gain mechanism.


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CONCLUSION We have demonstrated VOFETs with output current saturation with a current on/off ratio up to 105 by fabricating a perforated ITO source electrode. The pore dimensions of the ITO source electrode determine the potential distribution of C60 within the porous ITO regions and hence significantly affect the on/off ratio of the transistor. By combining a phosphorescent OLED with optimized VOFET, a vertical light-emitting transistor with luminance on/off ratio of 104 can be fabricated. Due to the usage of ITO electrode, which has been a common bottom electrode in many optoelectronic devices, for transparent gate capacitor, the VOFET will become a universal device platform to develop various optoelectronic sensors or memory units in the future.



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Figure 1. Schematic diagram and operation mechanism of the VOFETs. a) Structure of the vertical

organic

field-effect

transistor

(VOFET).

b)

Transmittance

of

porous

ITO/HfO2/ITO/glass capacitor. Inset is the photograph of the capacitor fabricated on 1 inch by 1 inch glass substrate. c) Scanning electron microscope (SEM) image of the porous ITO source electrode with average pore size of 575 nm. d), e), and f) Off state band diagram of the VOFET under zero gate bias and a positive drain bias with the source grounded; g), h), and i) On state band diagram under a positive gate bias and a positive drain bias. Charge injection


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occurs through narrower Schottky barrier width at porous ITO/C60 interface.



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Figure 2. a) Transfer and b) output characteristic of a representative VOFET with average pore size of 150 nm.


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Figure 3. Effect of pore dimensions on VOFET performance. Scanning electron microscope images of a porous ITO source electrode with the pore size controlled by a) 0 min, b) 1 min, and c) 2 min of oxygen plasma treatment. Each scale bar: 1 µm d) On current density (black), off current density (white), and average on/off ratio (blue) as a function of a pore size. e) Simulated conduction band profile of a C60 layer along the X direction at the porous ITO/C60 interface with different pore size. f) On current density (black), off current density (white), and average on/off ratio (blue) as a function of a pore depth. The pore size is fixed at 575 nm. g) Simulated conduction band profile of a C60 layer along the Z direction with different pore



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depth. Inset is the simulated conduction band profile of a C60 layer along X direction.

Figure 4. a) Device structure of VOLET as well as photographs with and without a gate bias, b) transfer, and c) output characteristic of a representative vertical organic light-emitting transistor.


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Acknowledgements We acknowledge the financial support from Nanoholdings LLC.


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Vertical Organic Field-Effect Transistors for ... - ACS Publications

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