Vertical-Tunnel Field-Effect Transistor Based on a SiliconâMoS2

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Vertical-Tunnel Field-Effect Transistor based on Silicon-MoS2 3D-2D Heterostructure Gwang Hyuk Shin, Bondae Koo, Hamin Park, Youngjun Woo, Jae Eun Lee, and Sung-Yool Choi ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b11396 • Publication Date (Web): 25 Oct 2018 Downloaded from http://pubs.acs.org on October 27, 2018

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ACS Applied Materials & Interfaces

Vertical-Tunnel Field-Effect Transistor based on SiliconMoS2 3D-2D Heterostructure

Gwang Hyuk Shin1, Bondae Koo1,2, Hamin Park1, Youngjun Woo1, Jae Eun Lee1 and Sung-Yool Choi1 *

1

School of Electrical Engineering, Graphene/2D Materials Research Center, KAIST,

Daehak-ro, Yuseong-gu, Daejeon, 34141, Republic of Korea Email: [email protected] 2

System LSI, Samsung Electronics,

Samsung-ro, Giheung-gu, Yongin-Si, Gyeonggi-do, 17113, Republic of Korea

1

ACS Paragon Plus Environment

ACS Applied Materials & Interfaces 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ABSTRACT

We present a tunneling field-effect transistor based on a vertical heterostructure of highly p-doped silicon and n-type MoS2. The resulting p-n heterojunction shows a staggered band alignment in which the quantum mechanical band-to-band tunneling probability is enhanced. The device functions in both tunneling transistor and conventional transistor modes, depending on whether the p-n junction is forward or reverse biased, and exhibits a minimum subthreshold swing of 15 mV/decade, an average of 77 mV/dec for four decades of the drain current, high on/off current ratio of approximately 107 at a drain voltage of 1 V, and fully suppressed ambipolar behavior. Furthermore, low-temperature electrical measurements demonstrated that both trap-assisted and band-to-band tunneling contribute to the drain current. The presence of traps was attributed to defects within the interfacial oxide between the silicon and MoS2.

KEYWORDS: tunneling transistor, heterostructure, MoS2, silicon, steep-slope device 2


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INTRODUCTION The success of the Information Age is due in large part to the rapid development of silicon electronics and the aggressive shrinking of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs). However, state-of-the-art CMOS technology faces several challenges, including high power consumption, the short-channel effect, and rising heat problems.1 These fundamental problems can be overcome by reducing the supply voltage and off-state leakage current, which will decrease the energy consumption and lower the operating temperature.2 Even though novel device structures, such as fin-FETs, have addressed some of these issues through good electrostatics in multi-gate devices3, 4, the challenges in metal-oxide-semiconductor field-effect transistors (MOSFETs) still remain because of the fundamental thermionic limitation of the subthreshold swing, which is 60 mV/decade at room temperature. One way to reduce the supply voltage and off-state leakage current without degrading the performance is to improve the switching steepness by lowering the subthreshold swing. To date, various novel devices, including impact-ionization MOS devices5, nanoelectromechanical FETs6, negative capacitance FETs7, and tunneling FETs8-10, have been proposed to provide steep-slope characteristics. Among these, tunneling FET is one of the most promising candidates for ultra-low power switching devices. Tunneling FETs exhibit an approximately 100-fold power reduction over conventional CMOS transistors, which significantly reduces the energy consumption.2 This is because the injection mechanism in tunneling FETs utilizes quantum-mechanical band-to-band tunneling, which is inter-band tunneling from the valence to conduction bands, rather than the thermionic emission process employed in conventional FETs. However, typical tunneling 3



FETs are somewhat limited due to their relatively low on-state current and ambipolar behavior. Although, while these issues can be partially relieved by modulating the doping profile in p-i-n homojunction tunneling FETs, other adverse effects remain, such as the Urbach tail, which creates trap sites within the bandgap, and random dopant fluctuation problems, which degrade the off-state current and subthreshold swing.11, 12 Some semiconductor heterostructures utilizing staggered or broken band alignments provide sharper band profiles than those from doping modulation alone. Consequently, they can enhance the on-state current as well as the steepness of the subthreshold slope in tunneling FETs. 11, 13-15 In addition, a smaller bandgap in the source improves the on-state current while a larger bandgap in the drain suppresses the ambipolar behavior. Such heterostructures have been proposed to boost the performance of tunneling FETs using SiGe10, III-V semiconductors11,

13, 14

, and Ge-MoS2.15 Recently, the emergence of two-

dimensional (2D) materials has attracted much attention for hetero-stacked vertical tunneling devices due to their unique physical properties. Although several hetero-stacked 2D/2D semiconductor devices have been reported, such as vertical transistors or diodes16-22, Sarkar et al. and Xiao et al. presented the subthermionic tunneling FET based on a Ge-MoS2 heterostructure15 and SnSe2-WSe2 heterostructure22 at room temperature, respectively. In the present study, for the first time we investigated a subthermionic vertical-tunneling field-effect transistor based on a highly p-doped silicon and tri-layer n-type MoS2, which was mechanically exfoliated to confirm the intrinsic characteristics. A p-n heterojunction diode was modulated by the high-k gate dielectric of Al2O3. The heterostructure of highly p-doped silicon as the source and MoS2 as the channel offers several advantages. First, the device fabrication process is not only compatible with well-established conventional silicon 4


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technology fabrication processes, but is also relatively simple compared to 1D nanowire structure based transistors.8, 11 Second, the on-state current can be increased because the band-to-band tunneling occurs at the surface of the vertically overlapped heterojunction rather than along a line in the typical laterally overlapped junction.15 Third, the electric field between the source and channel is significantly enhanced by the ultra-sharp doping profile. Fourth, the heterostructure produces a tunneling barrier that has a small width and height, which can increase the band-to-band tunneling (BTBT) efficiency. Fifth, Si can form more stable interfaces than Ge because it has lower interface state density (Dit) as well as higher thermal stability.23 Because of these advantages, we can achieve a steep-slope verticaltunneling field-effect transistor. In the reverse bias condition, the transistor exhibits a minimum subthreshold swing of 15 mV/decade with an on/off current ratio of approximately 107. In addition, the transistor not only shows an on-state current of approximately 2 µA (0.1 µA/µm) at VDS = 1 V, which is comparable to other tunneling FETs but also successfully suppresses the ambipolar behavior. By way of temperature dependent I-V measurements, we found that the tunneling current consisted of trap-assisted tunneling (TAT) and BTBT at low electric fields, while the BTBT current became dominant at high electric fields. RESULTS AND DISCUSSION Figure 1a illustrates the device structure. The device fabrication process is as follows. First, 70 µm × 70 µm square patterns were etched on a wafer using a photolithography process. The wafer consisted of a 90-nm-thick layer of silicon dioxide on a highly p-doped (≈ 1019 cm3

) silicon substrate, and the etching was performed by dipping the sample in buffered oxide

etcher (BOE) for 120 s to expose the silicon surface. Next, we implemented an Au mediated exfoliation method to obtain large area thin MoS2 flakes (see Figure S1 in the Supporting 5



Information).24 The prepared MoS2 flakes were transferred onto the patterned silicon surface via a dry transfer method with alignment system (see Figure S2 in the Supporting Information).17-19, 25 In order to prevent re-oxidation of the silicon in air, we immediately transferred the MoS2 flakes on the silicon surface as soon as the silicon dioxide was etched. The source that contacts the silicon and the drain that contacts the MoS2 were simultaneously metallized with 50-nm Ni, which facilitated Ohmic contact with both the silicon26 and MoS2.27

High k dielectric 8-nm Al2O3 was deposited by atomic layer deposition (ALD)

using thermal ALD equipment at the condition of 150 °C and 80 cycles. In general, it is difficult to deposit a thin high k dielectric on the 2D material due to the absence of dangling bonds; therefore, we pre-deposited a 1.5-nm Al thin blanket layer using a thermal evaporator and enabled the thin film to oxidize in air so as to function as a seed layer before initiating the ALD process.28 Finally, the gate electrode was patterned and deposited with the 50-nm Ni using the photolithography and thermal evaporation system, followed by a liftoff process. Figure 1b shows an optical microscope image of the p-n vertical heterojunction diode with highly p-doped silicon and MoS2 before gate stack fabrication. With the combination of highly developed doping technique in 3D silicon and n-type characteristics of MoS2, the vertical stack of n-type MoS2 and p-type silicon can create an extremely sharp doping profile15 (the doping concentration is abruptly changed to 4 orders of magnitude and the doping type is transited from p-type to n-type within a few nanometers. The doping concentration of our p-type silicon is approximately 1019 cm-3, whereas that of n-type MoS2 is approximately 1015 cm-3 in the literature29) without several doping processes, which cause dopant diffusion problems, due to the naturally n-type semiconductor characteristics of MoS2 hence the electric field at the interface is significantly enhanced due to absence of diffusion

6


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of dopant atoms.15 The relatively high electric field at the junction compared to the typical pi-n junction can lead to large BTBT currents due to the increased band bending. Two-dimensional semiconductors like MoS2 have good gate controllability due to their ultra-thin layered structure, but the bandgap is affected by the quantum confinement effect depending on the number of layers. In the case of MoS2, even if a monolayer has excellent electrostatics, the BTBT efficiency may be degraded by the large bandgap of approximately 1.8 eV. Thus, we employed tri-layer MoS2 for the heterojunction of our tunneling FET, which has good gate controllability and an appropriate bandgap of 1.2 eV.30 However, the tunneling transmission probability may be lowered by the quantum effects and phonon-assisted tunneling effects in indirect bandgap semiconductors.2 Figure 1c shows a cross section of a transmission electron microscope (TEM) image of the device in which the vertically stacked silicon crystal material, thin native oxide layer, three layers of MoS2, 8-nm Al2O3 gate dielectric, and Ni gate metal can be clearly seen in energy dispersive X-ray analysis (Figure S3, supporting information). The tunneling barrier width or distance is determined by the MoS2 thickness and the native oxide, which is a few nanometers in length.15 This native oxide thickness results in additional tunneling barrier width; therefore, it has a significant effect on the magnitude of the tunneling transmission probability in the silicon/native oxide/MoS2 structure. In addition, the gate bias applied in the vertical heterojunction can modulate the charge of the MoS2 as well as the silicon. Thus, a positive gate voltage could deplete the p-type silicon surface creating a depletion layer as an additional tunneling barrier width.31 The tunneling transmission probability can be exponentially lowered as the native oxide thickness and the depletion layer increase in accordance with the Wentzel–Kramer– Brillouin (WKB) approximation.31 Therefore, this native oxide layer should be minimized or removed so as to increase the tunneling probability. 7



Figure 1d illustrates a schematic band alignment diagram of the silicon and MoS2 heterojunction. The energy band alignment was investigated by X-ray photoelectron spectroscopy (XPS) using an Al Kα (1486.7 eV) X-ray source (see Figure S4 in the supporting information). The values of the valence band maximum (VBM) energy of the silicon and MoS2 were measured from the valence band spectrum of the respective materials and the values of the bandgap used in the literature.30, 32 The results of the XPS analysis showed the type II staggered band structure had a conduction band offset of 0.76 eV and valence band offset of 0.84 eV. The resulting vertical heterostructure was found to have a tunneling barrier with a small height of 0.35 eV between the valence band in the silicon and the conduction band in MoS2. The tunneling transmission probability (TWKB) in tunneling FET can be calculated by WKB approximation.2 √∗

≈ exp ( ћ(

)

) (1)

where λ, Eg, m*, q, ћ, and ∆Φ are the screening tunneling length, bandgap, effective mass, elementary charge, Planck constant, and energetic difference between the conduction band in the source and the valence band in the channel. In order to obtain a large tunneling current, the λ, Eg, and m* should be lowered. Especially, the screening length could be affected by several factors including the device geometry, doping profiles, and gate capacitance.2 In our device, the 3D/2D vertical p-n junction geometry allows to build a short tunneling width or distance with a few nanometers in length and the sharp doping profile between p-type silicon and n-type MoS2 forms a small barrier height; hence, λ was lowered and the BTBT efficiency was increased. Furthermore, the thickness of MoS2 can significantly affect TWKB because Eg

8


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and λ are changed by the number of layers in MoS2. λ can be represented by the following equation.22 λ=

!" #!" #$%

%$, (2)

where εch, εox, tch, and tox are the permittivity and thickness of the channel and the oxide dielectrics, respectively. To improve TWKB, we should use a thin MoS2 channel with a small bandgap. Hence, the tri-layer MoS2 can be of optimum thickness because it has not only thin 1.95-nm layers but also a bandgap of 1.2 eV, which is smaller than the monolayer MoS2 bandgap of 1.8 eV. Electrical measurements were carried out at room temperature in vacuum and dark conditions. Figure 2a depicts the IDS-VGS transfer characteristics of a device under reverse bias conditions, in which the drain voltage was varied from VD = 0.2 V to 2 V while the source was grounded. The gate leakage current of the same device was smaller than the drain current. To represent the transfer curve in the log plot, the drain current was taken to the absolute value because of the off-state noise current in the negative gate voltage ( 0); hence, BTBT occurred from the valence band of the silicon to the conduction band of the MoS2. The amount of electrons through the BTBT is determined by the energetic difference (∆Φ) between the valence band maximum (VBM) of the silicon and the conduction band minimum (CBM) of the MoS2. Therefore, the tunneling current Ids can be represented with following equation.

&'( ∝ *1 +,( (- ) − ,' (- )/0- (3) Where the ,( (- ) and the ,' (- ) is the Fermi-Dirac distribution function at energy E. On the other hand, the negative VG shifted the energy band of the MoS2 higher; hence, BTBT was suppressed, as shown in Figure 3c. In conventional FET mode, while the positive VG pulled the energy band down and allowed the diffusion of carriers from the source to the drain in forward bias conditions (VDS < 0), the negative VG pulled the energy band up and created a Schottky barrier to block the thermal diffusion. 11



To demonstrate the transport mechanism of our tunneling FET, temperature dependent electrical measurements were carried out. Figure 4a exhibits the IDS-VGS transfer characteristics at VDS = 1 V at different temperatures from 173 K to 293 K. The leakage current in the off-state (VG < -1.5 V) originated from the carrier recombination processes, including Shockley-Read-Hall recombination and direct recombination. In the vicinity of the onset gate bias (-1.5 V < VG < -1 V), IDS exhibits an obvious temperature dependence, which may indicate trap-assisted tunneling (TAT).11,40,41 On the other hand, in the on-state (VG > 1 V), a weak temperature dependence was present, which indicates that BTBT was the dominant transport mechanism at high VG. Figure 4b shows Arrhenius plots at different gate biases. The activation energy at each gate bias was measured to be 49 meV to 1 meV, which corresponded to VG = -1 V to 1 V. Based on these results, it is clear that there were traps in the channel. We speculate that the traps arose from defects within the interfacial oxide between the silicon and MoS2, but further studies are needed for an accurate analysis. The trap states should be reduced because the Fermi level pinning effect caused by these chargeable states can degrade the SS in the tunneling FET.42 In Figure 4c, a weak temperature dependence can be seen in the minimum and averaged SS, which signifies a tunneling based transport mechanism. The minimum SS was measured from 16 to 23 mV/decade and the averaged SS over approximately 4 decades was confirmed from 77 to 82 mV/decade. The value of the averaged SS can be determined from: 2345 =

67 689: > ;89:

(4)

where VT, IT, Vmin, and Imin are the threshold voltage, drain current at VT, voltage at Imin, and minimum drain current. The threshold voltage was determined using the constant current method at 10-9 A. 12


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Furthermore, to confirm the evidence of BTBT, the experimental values were evaluated using Kane’s model43, 44, which is defined as C/

?@@ = A- -B

exp(

/F

E

) (5)

where Eg is the bandgap, E is the electric field at the tunneling junction, and A and B are the tunneling model parameters, which consist of the effective mass and tunneling width, as shown in Figure 4d. The tunneling generate rate, GBTBT, can be rewritten in terms of VGS from the Fowler–Nordheim tunneling equation for BTBT in the silicon assuming a triangular potential barrier.43 C/

&GH = AI -B

JKH exp(

/F

E

G6LM

) (6)

where D is the parameter between the electric field at the tunneling junction and VGS, which is a function of the drain voltage, oxide thickness, channel length, and doping concentration. If we define the normalized drain current (IDS/VGS2) and take the natural log of the above equation, the following equation can be obtained.43 Log

QRM

F 6LM

= Log

SG F

T/F

−

/F

G6LM

(7)

The measured transfer characteristics of our device are plotted as log(IDS/VGS2) with respect to 1/VGS, and we confirmed a straight line with the intercept of 9.2 showing AD2 and the slope of 4.4 showing B/D for constant Eg. A straight line is well fitted to the measured data and thus, the experimental results are consistent with the theory. CONCLUSIONS In this paper, we demonstrated a tunneling FET based on a silicon and MoS2 vertical heterostructure with a minimum SS of 15 mV/decade and on/off current ratio of approximately 107. Our tunneling FET could be compatible with conventional silicon 13



fabrication technology, and hence can be applied to large-area wafer scale applications of high density integrated circuits, assuming the synthesis technology of 2D materials is further developed. In addition, the operating mechanisms can be understood through the temperature dependent transfer characteristics, which signify the evidence of BTBT and TAT, depending on the gate bias. Based on the fabrication and characterization results of the tunneling FET, it will be useful in future ultra-low-power electronics applications. METHODS The device fabrication process is fully stated in the results and discussion section above. Electrical measurements were conducted using a semiconductor parameter analyzer (4200 SCS, Keithley Instruments) and probe station (MS-TECH). All measurements were performed in vacuum and dark conditions. Temperature dependence tests were performed using the same instruments, and low-temperature ambient conditions were realized by liquid nitrogen. Cross-sectional TEM images were obtained using a transmission electron microscope at 300 keV (Titan3 G2 60-300, FEI Company). ASSOCIATED CONTENT The Supporting Information Supporting Information is available online or from the author. Exfoliation method; transfer method; TEM images; XPS data; explanation for instrument noise current; I-V curve for MOSFET mode; comparison table; optical microscope images of the device; measurement scheme; SS vs. IDS plot; temperature dependent IDS-VDS in the tunneling FET; temperature dependent IDS-VGS in the MoS2 MOSFET. ACKNOWLEDGEMENT 14


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This research was supported by grants from the Creative Materials Discovery Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT, and Future Planning (NRF-2016M3D1A1900035), and the Global Frontier Research Center for Advanced Soft Electronics (Gran No. 2011-0031640). Conflicts of interest. The authors declare no competing financial interest.

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Vertical-Tunnel Field-Effect Transistor Based on a SiliconâMoS2

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Vertical-Tunnel Field-Effect Transistor Based on a SiliconâMoS2