Vertically Integrated Nanowire-Based Unified Memory - Nano Letters

Aug 31, 2016 - Department of Memory Business, Samsung Electronics, San 16 Banwol-Dong, Hwasung City, Gyeonggi-Do 18448, Republic of Korea. § Departme...
0 downloads 19 Views 3MB Size
Download PDF
Letter pubs.acs.org/NanoLett

Vertically Integrated Nanowire-Based Unified Memory Byung-Hyun Lee,†,‡ Dae-Chul Ahn,† Min-Ho Kang,§ Seung-Bae Jeon,† and Yang-Kyu Choi*,† †

School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea ‡ Department of Memory Business, Samsung Electronics, San 16 Banwol-Dong, Hwasung City, Gyeonggi-Do 18448, Republic of Korea § Department of Nano-Process, National Nanofab Center (NNFC), 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea S Supporting Information *

ABSTRACT: A vertically integrated nanowire-based device for multifunctional unified memory that combine dynamic random access memory (DRAM) and flash memory in a single transistor is demonstrated for the first time. The device utilizes a gate-all-around (GAA) structure that completely surrounds the nanowire; the structure is built on a bulk silicon wafer. A vertically integrated unified memory (VIUM) device composed of five-story channels was fabricated via the one-route all-dry etching process (ORADEP) with reliable reproducibility, stiction-free stability, and high uniformity. In each DRAM and flash memory operation, the five-story VIUM showed a remarkably enhanced sensing current drivability compared with one-story unified memory (UM) characteristics. In addition to each independent memory mode, the switching endurance of the VIUM was evaluated in the unified mode, which alternatively activates two memory modes, resulting in an even higher sensing memory window than that of the UM. In addition to our previous work on a logic transistor joining high performance with good scalability, this work describes a novel memory hierarchy design with high functionality for system-on-chip (SoC) architectures, demonstrating the practicality and versatility of the vertically integrated nanowire configuration for use in various applications. KEYWORDS: Vertically integrated nanowire, zRAM, 1T-DRAM, NAND flash memory, unified memory, one-route all-dry etching process an advantage for DRAM can be a disadvantage for flash memory, and vice versa. Thus, the memory market has been unwillingly bisected. For example, charge trap flash (CTF) memory has the benefit of nonvolatility; however, its slow speed and poor reliability are problematic. In contrast, even though DRAM has the strengths of high speed and robust reliability against iterative operations, the inherent characteristic of volatile memory, which inevitably demands a periodic refresh operation, thus increasing power consumption, has not yet been resolved. For an embedded system that is aimed at achieving system-on-chip (SoC) technology, DRAM is manly utilized for data processing that requires a rapid memory function, whereas nonvolatile flash memory is used for highcapacity storage with long-term retention times of more than 10 years. However, the monolithic integration of the two memory devices with a logic transistor is actually impossible due to the fabrication of a capacitor in DRAM and the formation of a charge trap layer in flash memory; the two

W

ith the remarkable growth of information and communication technology (ICT), many different electronic devices have been developed. Among them, memory devices are core components for data storage. In the era of smart electronics, the explosive increase in digital data requires a memory technologies with high speed, good scalability, and low-power operation for effective data-driven computation. In particular, due to the demands of state-of-the-art information technologies that are suitable for big data storage or the Internet of Things (IoT), the necessity for these technologies is highlighted. Over the past four decades, dynamic random access memory (DRAM) and flash memory have been technology drivers in the domains of speed, power, and capacity via their aggressive miniaturization based on silicon technology.1 Although numerous emerging memory devices have been proposed,2,3 the two previously mentioned memory devices still share a dominant portion of the market as costdriven products. Furthermore, they will indisputably remain mainstream for the next two decades with the aid of mature and well-established silicon technologies.4 However, DRAM and flash memory suffer from an inherent conflict that originates from the unique operation mechanism of each device. That is, © XXXX American Chemical Society

Received: July 7, 2016 Revised: August 9, 2016

A

DOI: 10.1021/acs.nanolett.6b02824 Nano Lett. XXXX, XXX, XXX−XXX

Letter

Nano Letters

DRAM). In this case, the body of the transistor itself serves as a built-in capacitor. In addition to the reduction of the cell size, which is a consequence of the absence of the cell capacitor, one of the greatest advantages of zRAM is that, unlike conventional DRAM, no sense amplifier for the identification of the data state is needed. The removal of the sense amplifier itself can be beneficial to prolonging DRAM scaling because the sense amplifier occupies an area of approximately 15% of the total chip size, 30% of the total power consumption for read and write operations, and 25% of the speed delay. Furthermore, this feature provides an additional wide option for a versatile periphery circuit architecture to enhance the performance and packaging density. In this respect, a notable increase in the data sensing margin (ION/IOFF), i.e., the memory window, is very important for the stable memory function of DRAM without the sense amplifier. Unfortunately, aggressive scaling of SiNWs, which is good for the suppression of IOFF but detrimental to ION, is precluded by the decreased ION. Such a condition cannot be exceptional in flash memory. In addition to NAND flash memory, which is suitable for bulk storage because of its high packing density and low energy consumption,24 NOR flash memory is attractive from the point of view that it can share the backbone architecture of DRAM in the fabrication of URAM. However, the extremely scaled SiNW channel cannot provide an ION that is sufficient for the wide sensing margin and could result in erroneous data, i.e., “readout failure”, as well as a degradation of the speed.25 This failure would be aggravated by the further scaling of the unit transistor to achieve a highdensity cell. For circumventing the reduced ION, the previously mentioned vertical integration of multiple GAA SiNWs is desirable. Therefore, taking all of the factors into consideration, the combination of the strengths of the two types of memories with the aid of the vertically integrated multistacked GAA SiNW structure is an attractive approach for extremely scaled memory with high performance and multifaceted functions. In this study, a vertically integrated channel-based unified memory (VIUM) combining DRAM and flash memory is demonstrated for the first time on an 8 in. bulk-silicon wafer. A transistor body serves as the intrinsic capacitor for the DRAM function, and an oxide−nitride−oxide (O/N/O) gate dielectric is used for the flash memory function. The fabricated VIUM exhibited DRAM and flash memory functions without critical interference. The device is fused at the transistor level, not at the system level; thus, a monolithic integration encompassing the strengths of DRAM and flash memory was allowed. A noticeably enhanced data sensing current without the sacrifice of scalability was observed. Therefore, the technology provides potential routes to prolong the scaling of memory and to produce hybrid memory devices. The vertical stacking of SiNWs, which is the most important process in the entire fabrication, is achieved via a one-route all-dry etching process (ORADEP). Compared with the results of previous works,26−28 the optimized ORADEP permitted the stable creation of the vertically integrated multistacked SiNWs without stiction failure, demonstrating its high controllability, high reproducibility, and simplicity. An image of a VIUM with a five-story structure was clearly obtained via high-resolution transmission electron microscopy (TEM) and energy-dispersive spectrometry (EDS). Compared with results from one-story unified memory (UM), the five-story VIUM exhibited a remarkable increase in sensing current for both the zRAM and the flash memory operations, i.e., the current corresponds to the number of stacked SiNWs. This feature increases the window of circuit

technologies are incompatible with each other. Thus, chip-tochip bonding at the package level has been proposed as an alternative.5 Unfortunately, such hybrids chip are bulky and therefore not appropriate for mobile devices. Furthermore, the interference that arises from the interconnection wires between the chips is a concern. Notably, the fraction of the packagerelated delay stemming from the interference is greater than 50% of the total delay of the electronic signals. Such a delay would be aggravated in more-complicated systems and eventually be a severe obstacle to obtaining the integrity necessary for embedded system-level integration. Moreover, the cost is high because the two chips are bonded together. Recently, the cost for a back-end process that includes dicing, wiring, and packaging a fabricated chip has led to an increase in the total chip price compared with that for a front-end process involving the micro−nanofabrication of the chip on a wafer. In addition, the total power consumption of a number of functional blocks embedded for SoC configuration is problematic. In this regard, unified RAM (URAM), which is a hybrid device not at the package level but at the transistor level, could be an attractive approach to integrating the functions of flash memory and DRAM in a single transistor.6 URAM is based on complementary metal-oxide-semiconductor (CMOS) technology. The merits of URAM are summarized in the Supporting Information. Because the continuous miniaturization of semiconductor devices has directly reduced the fabrication cost and improved productivity and performance, it has also been a barometer for the advancement of DRAM and flash memory technologies. Effectively suppressing the severe short-channel effects (SCEs) of a unit transistor is therefore crucial in such memory devices.7,8 As an approach to inhibit SCEs, the implementation of a three-dimensional (3-D) gated structure in lieu of a conventional two-dimensional (2-D) gated structure has been a driving force to prolong Moore’s law,9−11 demonstrating the feasibility of a sub-10 nm scale transistor.12 Among various 3-D structures, the silicon nanowire (SiNW) gate-all-around (GAA) transistor has been recognized as the end of the structural roadmap with respect to the suppression of SCEs13,14 and as an attractive platform for versatile applications in various fields of micronanotechnology.15−19 The smaller diameter of the SiNW results in a lowered off-state current (IOFF). However, the extreme scaling of SiNWs inevitably gives rise to a reduction of the on-state current (ION); therefore, a compromise exists between the controllability of IOFF and the drivability of ION. ION and IOFF correspond to the drain current (ID) in the “on” state and “off” state, respectively. In this regard, the vertical integration of multiple GAA SiNWs is a very desirable configuration that provides good scalability, effectively suppresses the SCEs, reduces energy consumption, and recuperates the ION sacrificed by the extremely scaled SiNWs.20,21 In accordance with these attributes, the use of such a configuration, i.e., vertically integrated multistacked GAA SiNWs, may be the optimal choice with which to overcome the scaling limits of DRAM and flash memory. In terms of the scaling of DRAM and flash memory, the manufacturers of DRAM have recently encountered immense challenges for continuous miniaturization with the advent of sub-20 nm DRAM technology.22 In particular, the cell capacitor for data storage has become the bottleneck for further scaling of DRAM. Accordingly, reconsidering a zero-capacitor DRAM (zRAM) that consists of only one transistor (1T) is a timely approach;23 zRAM is also known as one-transistor DRAM (1TB

DOI: 10.1021/acs.nanolett.6b02824 Nano Lett. XXXX, XXX, XXX−XXX

Letter

Nano Letters

Figure 1. Details of the VIUM, including the operation principle and voltage domain. (a) A schematic of the URAM that combines DRAM and flash memory and the five-story SiNW VIUM for high performance. The strengths of DRAM with high speed and flash memory with nonvolatility are unified in a single-transistor-based URAM. The floating SiNW body serves as storage node 1 (SN1) for the zRAM, whereas the floating nitride gate serves as storage node 2 (SN2) for the flash memory. In addition, “W/L” and “B/L” denote the word line to access the target cell and the bit line to transfer the data, respectively. The five-story VIUM enhances the strengths of the URAM by achieving high performance without sacrificing scalability. (b) The operation principle of the VIUM. Its operation relies on impact ionization facilitated by a lateral (drain-to-source) electric field for the zRAM and FN tunneling via a vertical (gate-to-body) electric field for the flash memory. Thus, the holes that accumulate in the floating SiNW body and the electrons trapped in the nitride layer change the VT and the ID (ION) of a fresh device. That is, the trapped electrons in the nitride give rise to an increase in VT and consequent reduction of ID, which corresponds to a data state of “0” in the flash memory. In contrast, the accumulated holes in the SiNW lead to an increase in ID accompanied by a reduction of VT, resulting in a data state of “1” in the zRAM. The blue mark inside the SiNW indicates the outbreak of the impact ionization. (c) The voltage domain for the multifunctional memory operation. The main voltage for each memory function in the VIUM is as follows: the 1st quadrant is the programming of the flash memory and the zRAM; however, the magnitude of the voltage is quite different for each memory (i.e., the voltage does not overlap). The second quadrant is for the erasing of the zRAM, and the fourth quadrant is for the erasing of the flash memory. Hence, two memory functions are realized in one transistor without disturbance due to overlap of the operation voltages.

and a floating gate, i.e., a nitride layer inside the O/N/O gate dielectric, for the flash memory. Thus, a dual function can be achieved in a single transistor without the construction of additional storage, enabling good scalability with a high packing density. With regard to the writing and erasing of data, unlike conventional DRAM with a mechanism of charging and discharging the cell capacitor, the operation of zRAM is based on impact ionization triggered by hot electron injection.23 The excess holes generated by iterative impact ionizations accumulate in the floating SiNW body and give rise to parasitic bipolar junction transistor (BJT) behavior that consists of n+ for the emitter, p for the base, and n+ for the collector, where each node in turn corresponds to the source, body, and drain.29 Notably, the base is floating in the parasitic BJT, whereas it is biased in a conventional BJT. Because of the action enabled by the parasitic BJT, an abrupt increase in ID occurs, along with a very steep subthreshold slope (SS), reducing the threshold voltage (VT) of the VIUM. As a consequence, the VIUM exhibits a remarkably increased ID at a particular reading voltage compared to the initial condition (Figure 1b), which indicates a data value of “1” by the writing operation in the zRAM mode of the VIUM. The erasing of the data value of “1” is attained by removing the accumulated holes with the aid of a drain junction current enabled by VD and thus simultaneously permitting the writing of a data value of “0”. In contrast, the program−erase (P/E) of the flash memory in the VIUM is based on Fowler−Nordheim (FN) tunneling.30 The data states of the flash memory operation are identified by the

designs for versatile applications and enables the aggressive scaling of the footprint area in chip architecture because of the removal of the sense amplifier. In addition, the VIUM showed reliable cyclic endurance for both zRAM and flash memory operations. Considering the very tall configuration of the silicon−oxide−nitride−oxide−silicon (SONOS)-based GAA SiNWs, which are stacked up to five levels, this result demonstrated the stability of the full process, including the ORADEP. Here, the five-story VIUM with an O/N/O gate dielectric can serve as a high-performance logic transistor due to the multistacked SiNWs, which are operable with up to five channels. Thus, this work could influence the design of memory blocks for versatile SoC architectures and ultimately enable the integration of multifunctional devices. Details regarding the VIUM, including its structural and operational features, are depicted in Figure 1. Taking the “unified’” in unified memory literally, the device combines different memory functions into a unit cell that consists of only one transistor,6 thereby serving as a complementary memory that harnesses DRAM with high speed and flash memory with nonvolatility. Here, as previously mentioned, the zRAM without a cell capacitor replaces the function of conventional DRAM. Moreover, the VIUM can be operated with up to five channels in parallel and can therefore achieve high performance without sacrificing scalability, which is different from the onestory UM (Figure 1a). Figure 1b shows a schematic and the basic operation principle of the VIUM. As a storage node (SN) to sustain data, the VIUM utilizes a floating body for the zRAM C

DOI: 10.1021/acs.nanolett.6b02824 Nano Lett. XXXX, XXX, XXX−XXX

Letter

Nano Letters trapping and the detrapping of FN-tunneled charges into the nitride layer sandwiched between the tunneling oxide and the barrier oxide,31 where such an O/N/O stack serves as the gate dielectric of the VIUM. When a positive bias for programming (VPGM) is applied to the gate electrode in the case of the nchannel FET, the electrons are injected into the nitride layer via the FN tunneling mechanism, thus resulting in an increase in VT, as shown in Figure 1b. Similar to the case of the zRAM operation, this action gives rise to an increase of in VT and a reduction of ID at the reading voltage compared to the state of preprogramming, which indicates a data state of “0” (Figure 1b). In addition, the erasing of a data state of “0” and the programming of a data state of “1” are feasible at the same time via the detrapping of charges from the nitride layer by applying a negative gate bias (VG), i.e., the voltage for the erasing operation (VERS). The bias domain of each operation is described in Figure 1c. In conclusion, no interference occurs between the bias condition for zRAM and the flash memory in the VIUM. Specifically, the zRAM operation requires a comparatively higher VD to trigger the impact ionization in the domain of an ordinary VG below 2 V, whereas the flash memory operation demands a substantially greater VG and a particular VD, commonly 50 mV or 1 V, as presented in Figure 1c. In addition, a difference exists in the quantitative value for each operation voltage, and the zRAM operation is mainly based on the lateral electric field (drain to source) generated by VD, whereas the flash memory operation strongly depends on the vertical electric field (gate to body) modulated by VG. Considering the operation voltage, this quantitative and qualitative distinction supports independent and stable operation without severe interference during the actuation of each memory mode in the VIUM. Consequently, this nonoverlap of the voltage domains is very desirable for selecting the intended memory operation from the VIUM because it enables the selection of a memory mode that can be customized to the needs of the end-user. The bias domain for the real multifunction of the VIUM is included in the Supporting Information. The fabrication process of the VIUM is very similar to that reported in our previous works except for the formation of the gate dielectric. Instead of a thermally grown gate oxide, an O/ N/O gate dielectric, which is composed of a thermally grown tunneling oxide, a nitride charge-trapping layer deposited by low-pressure chemical vapor deposition (LPCVD), and a barrier oxide deposited by LPCVD, was used for the flash memory and the zRAM. The details of the overall fabrication process, including the optimum conditions of the ORADEP, which is the most elaborate step of the process, have been reported in our previous works.20,21 In addition, the Supporting Information in this work provides brief descriptions of the entire fabrication process. Figure 2a shows a schematic of the VIUM. The roles of the interlayer dielectric (ILD) oxide, which is referred to as the shallow trench isolation (STI) oxide elsewhere, are (1) to isolate the fabricated transistors from one another in the same plane and (2) to block any unwanted leakage current paths through the bulk silicon below the bottom of the SiNW channel. The images of the fabricated VIUM obtained with scanning electron microscopy (SEM) and TEM, along the direction indicated in the schematic, are shown in panels b and c of Figure 2, respectively. The clear separation of each uniform SiNW surrounded by the poly-Si gate proves that the GAA structure is complete, demonstrating the stability and reproducibility of the ORADEP without stiction failure.

Figure 2. Schematic and SEM and TEM images of the VIUM. (a) A schematic of the VIUM fabricated on the bulk-Si substrate, where “S”, “D”, and “G” denote the source, drain, and gate, respectively. (b) An SEM image along the a−a′ direction (parallel to the SiNW length) in Figure 2a. The complete separation of uniform SiNWs without stiction failure was achieved with the aid of the optimized ORADEP. (c) A cross-sectional TEM image along the b−b′ direction (parallel to the gate length) ofFigure 2a. Poly-Si serves as the gate surrounding five SiNWs that demonstrate the complete GAA SiNW configuration. The upper inset of Figure 2c shows a magnified view of one of the SiNW channels. The lower inset shows an inverted TEM image of the SiNW channel and its EDS mapping image. Each layer of the SONOS configuration is clearly identified via this inset image.

The upper inset image in Figure 2c shows a close-up view of a single SiNW among the five SiNWs. The O/N/O stack consists of a thermally grown SiO2 layer, which completely wraps the rhombus-shaped SiNW, Si3N4 enclosing the SiO2, and tetraethyl orthosilicate (TEOS) as the outer layer. Each layer is clearly identified by EDS mapping and by the TEM image with inverted color. The vertically integrated five-story GAA SiNW-based fieldeffect transistor (FET) with an O/N/O gate dielectric exhibits a remarkable improvement in ION compared to results from the one-story GAA SiNW-based FET, as expected (Supporting Information). Additionally, the vertically integrated five-story GAA SiNW-based FET with an O/N/O gate dielectric was utilized for the zRAM. Figure 3 shows the zRAM characteristics of the VIUM. The basic operation of the zRAM in the VIUM is presented in Figure 3a. It relies on a single transistor latch (STL) stemming from impact ionization and consequently actuates parasitic BJT. As mentioned previously, the iteration of the hot electron-induced impact ionization activates the N−P− N-type parasitic BJT in the floating SiNW body. Because the parasitic BJT serves as another driving source in addition to the inherent metal-oxide semiconductor field-effect transistor (MOSFET), the zRAM in the VIUM can maintain an “on” state with a high ION despite a reduction in VG, i.e., the “off” state of the MOSFET. This phenomenon signifies the STL behavior,32 which serves as the impetus for the operation of the zRAM. Although the device exhibits normal I−V characteristics at low VD, i.e., below 1 V, it exhibits an extremely steep slope of less than 10 mV/dec, accompanied by bistable hysteresis at high VD, which sufficiently triggers the STL behavior. During D

DOI: 10.1021/acs.nanolett.6b02824 Nano Lett. XXXX, XXX, XXX−XXX

Letter

Nano Letters

Figure 3. ZRAM operation of the VIUM. (a) The double-sweep ID−VG characteristic with various VD showing the basic operation of the zRAM in the VIUM. LG, WNW, and HNW denote the gate length, nanowire width, and nanowire height, respectively. TO/N/O means the thickness of the O/N/ O gate dieletrics; the subscripts represent, from left to right, the thickness of the tunneling (control) oxide, the nitride charge-trapping layer, and the barrier (blocking) oxide. An abrupt switching characteristic is achieved beyond the critical VD, which is the triggering voltage of the impact ionization and enables the parasitic BJT faction (refer to the Supporting Information for bias magnitude conditions and pulse duration for the zRAM operation). (b) A comparison of the double-sweep ID−VG characteristics of the one-story UM and of the five-story VIUM, where open and closed circles represent the reverse and forward sweeps, respectively. The triangle symbol indicates a slope of 60 mV/dec, which is known as a limiting value of the SS in relation to conventional MOSFET operation. This limitation is surpassed by virtue of the impact ionization in the zRAM operation mode, resulting in a steep SS below 10 mV/dec (c) A transient measurement based on the BJT method of each memory device with the periodic P/ E operation as a function of applied pulse time, where tRead means the time for a reading operation. Compared with that of the one-story UM, an enhanced ISENSE in the five-story VIUM is verified, where ISENSE denotes the negative source current (−IS) in practice. (d) The variation of ISENSE as a function of the pulse time. During the periodic readout operations, the memory states of the five-story VIUM are sustained without serious degradation of the ISENSE. The five-story VIUM shows a noticeably improved ISENSE compared with that of the one-story UM. (e) Multireading operations under the periodic hold state, where tHold denotes the interval between reading operations, i.e., a retention time of the programmed data. The dual state is repeated via the BJT-method-based readout operation. The arrow indicates the programing point, which indicates the data state of “1” (left) and the data state of “0” (right). (f) A comparison of the postcycle endurance characteristics. The five-story VIUM maintains a higher ISENSE than the one-story UM, even after iterative P/R/E/R operations, where “P”, “R”, and “E” denote the operations for the programming, reading, and erasing of the data, respectively.

becomes increasingly important for continuous memory scaling as the cell size is reduced. Additionally, the opportunity to make use of the area normally occupied by the sense amplifier is very attractive for versatile circuit architectures, demonstrating the necessity of the VIUM. Stable readout operations are accomplished in one- and five-story zRAM via the BJT mode, as previously mentioned (Figure 3d), which is desirable for power saving and rapid operation because of the decreased periodic refreshing. Moreover, multiple readout operations showing robust hold retention are achieved in the VIUM without loss of the programmed data (Figure 3e), where a hold time (tHold) of 500 ms corresponds to a static retention time of the programmed data in conventional DRAM. This approach is useful for determining the optimum cycle of the readout operation based on the BJT method; the device can thereby efficiently manipulate power consumption. In addition, the VIUM showed a reliable zRAM switching endurance (Figure 3f). For the zRAM operations, including the basic P/E operation and the postcycle endurance, the VIUM retained the increased sensing current window without any malfunctions.

the forward and reverse bias sweeps, a hysteresis loop in the zRAM operation results from a positive feedback mechanism that is due to the operation of the parasitic BJT. The bias magnitude and pulse duration for the zRAM operation are summarized in the Supporting Information. Figure 3b shows the hysteresis transfer characteristics of the one- and five-story zRAM. As expected, ION increases as the number of vertically stacked channels increases. However, no notable degradation of the critical parameters, such as the SS and IOFF, is observed during the operation of the zRAM. The periodic P/E operation of the zRAM is presented in Figure 3c, where the BJT method was applied.33 The BJT method is preferred for stable data retention, which warrants a wide window for the sensing current (ISENSE) and is beneficial for nondestructive read operations.33 ISENSE corresponds to ID for sensing the data state and represents the negative source current (−IS). Notably, ISENSE of the VIUM is remarkably improved compared to that of the UM. Considering that the read current of a cell array transistor in conventional DRAM has recently reached values less than 10 μA, a high VIUM current is capable of identifying the data state without a sense amplifier. This advantage E

DOI: 10.1021/acs.nanolett.6b02824 Nano Lett. XXXX, XXX, XXX−XXX

Letter

Nano Letters

Figure 4. Flash memory operation of the VIUM. (a) The ID−VG characteristics of the flash memory with one- and five-story SiNW configurations, where the physical parameters of the device are equal to those of the device in Figure 3a. The VT shift by the P/E operation is identified. A memory window (VT difference) above 4 V is achieved without degradation of the SS. The voltage polarity is positive for the data programming and (2) negative for the data erasing. “Fresh” denotes the initial pristine state of the device before the P/E operation. (b) The P/E transient characteristics with various voltages and pulse times. The left figure represents the one-story UM, and the right figure shows the results for the five-story VIUM. Despite the five-story SiNW configuration, the VIUM exhibited a stable transition with an acceptable memory window corresponding to the applied voltage. (c) A comparison of ISENSE after the readout operation of each data state including the fresh state, where arrows indicate the programming points of “0” and “1”. VG,Read and VD,Read represent the readout voltage of VG and the readout voltage of VD, respectively. Similarly, tPGM and tERS denote the times for programming and erasing, respectively. Compared with results from the one-story UM, ISENSE was increased in the five-story VIUM for the fresh state and the data state of “1”. (d) A comparison of the data retention time for the one-story UM and the five-story VIUM. (e) A comparison of the postcycle endurance characteristics of the one-story UM and the five-story VIUM. The five-story VIUM maintained an ISENSE that was higher than that of the one-story UM, showing robust nonvolatility and reliable P/E endurance. Here, the bias conditions and times for each operation are equal to those in Figure 4c.

The flash memory operation is another function of the VIUM and is described in Figure 4. Figure 4a shows the I−V characteristics of the P/E operation of the flash memory. The FN-tunneled electrons are trapped in the nitride layer when a positive bias is applied to the gate electrode for programming. Such trapped electrons shift the I−V curve to the right, i.e., VT is positively shifted compared with results from the fresh state. This VT difference is commonly called the “memory window” of flash memory. As a result, each memory device, i.e., the onestory UM and the five-story VIUM, shows a lower current at a particular reading voltage (e.g., a VG of 2 V) compared to that of the preprogramming state. This difference in current, i.e., the sensing current window, is critical for maintaining the accuracy of a data state, and the fast readout operation should be guaranteed regardless of the scaling down of the memory device. As shown in Figure 1a, the five-story SiNW VIUM exhibit a sensing current window that is larger than that of the UM with a one-story SiNW, which corresponds to an FET with a larger number of channels (see the Supporting Information). In the case of the post-erasing operation, the higher current of the VIUM was sustained without substantial degradation compared to results from the fresh state. Figure 4b shows the variation in the memory window with various voltages for the

P/E operation as a function of the pulse time. Consequently, the VIUM exhibits stable flash memory operation with an acceptable memory window under various conditions despite a device configuration with a tall height and numerous SiNWs. The ISENSE of each memory is compared in Figure 4c. Regardless of the time, the nonvolatile VIUM exhibited a higher ISENSE than the UM in all states, including the fresh state. Furthermore, the suitability of the VIUM for high ISENSE-based nonvolatile memory is verified by Figure 4d. The VIUM shows robust endurance in Figure 4e, sustaining a higher ISENSE than the one-story UM even after 105 periodic P/E cycles. The previously mentioned memory functions of the VIUM, i.e., the zRAM in Figure 3 and the flash memory in Figure 4, were independently demonstrated in each memory mode. Although the two memory functions are realized in a single transistor, mutual disturbance between the zRAM and flash memory can be a concern. During the iterative zRAM operations, some energetic electrons enabled by the parasitic BJT action can be captured in the nitride of the O/N/O. However, this issue has already been resolved in our previous work and is no longer a concern.34 However, checking for any disturbance of the zRAM after iterative flash P/E operations is important. As shown in Figure 5, to verify the postcycle F

DOI: 10.1021/acs.nanolett.6b02824 Nano Lett. XXXX, XXX, XXX−XXX

Nano Letters

■

Letter

ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.6b02824. Additional details on the fabrication process, a comparison of the drain current-gate voltage, operation conditions of the zRAM in the VIUM, variation of the memory window for the flash memory operation in the VIUM as a function of the retention time and the number of P−E cycles, domains of the operation voltage for the zRAM and the flash memory in the VIUM, merits of the transistor-level unification based on the VIUM, and discussion on further scaling of the VIUM. Figures showing schematics of the ORADEP and for the brief description of the fabrication process, a comparison of the ID−VG characteristics of the O/N/O gate dielectricbased one-story and five-story SiNW channel FETs, bias conditions and pulse wave duration for the evaluation of the BJT method based zRAM operation, data retention and switching endurance of the flash memory in the VIUM, operation voltage domains for the zRAM mode and the flash memory mode in the VIUM, merits of the transistor-level unification based on the VIUM, a schematic of the PR trimming process to reduce the prepatterned PR size and the resulting SEM image, and a schematic of the SADP process and the consequent real images using SEM and TEM. A table showing process conditions for the ORADEP to reduce the SiNW width. (PDF)

Figure 5. Postcycle endurance characteristics under the mutual disturbance condition. Under this condition, sequential operations in the zRAM mode are immediately performed after iterative P/E operations in flash-memory mode. In addition to each independent memory operation, the VIUM also operates under the mutual disturbance condition, ensuring that the unified memory is functioning well, even at the single-transistor level.

endurance of the VIUM, iterative P/E operations of the flash memory were carried out and, immediately after, the zRAM was operated for the same number of cycles. In addition to the independent operation mode of the zRAM and the flash memory, as shown in Figures 3 and 4 and in the Supporting Information, the VIUM showed an acceptable P/E endurance, even in the unified mode shown in Figure 5. Although the sensing memory window was somewhat reduced in the unified mode, compared to results from the independent mode, the VIUM with five channels still retains a higher sensing memory window than the independent mode of the UM with a single channel, supporting the practicality of the VIUM. This result reflects the high integrity of the unified memory performance and the fabrication process in relation to the development of multifunctional memory. In summary, vertically integrated unified memory based on a five-story GAA SiNW FET (which is abbreviated as VIUM) was demonstrated on a bulk-Si substrate for the first time. The VIUM combined high-speed DRAM and nonvolatile flash memory. The ORADEP optimized in our previous work enabled the fabrication of the five-story VIUM with high reproducibility, as supported by high-resolution TEM and SEM analyses. In each memory function, the fabricated VIUM exhibited a noticeably enhanced ISENSE compared with that from a one-story UM with the same design. This achievement was entirely retained without substantial degradation, even after iterative operations, to verify the switching endurance, demonstrating robust reliability. The complete fabrication of the VIUM was entirely compatible with the CMOS process with high reliability and high completeness. In addition to our previous work,20,21 which demonstrated the capability of encompassing SCE suppression, high performance, and good scalability in an FET for a logic circuit, the demonstration of the VIUM can affect the architecture of a memory block embedded in a system-level chip from the viewpoint of the scaling of the chip size and power efficiency. Furthermore, this result is meaningful in that it is the real unification at the transistor level of two representative memories that have dominated the memory market. Thus, the VIUM can serve as a blueprint for the ultimate scaling of multifunctional memory toward the end of the roadmap, and more practically, it would serve as a core player in an innovative ICT product that leads a “smart life”.

■

AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. Author Contributions

B.-H.L. and D.-C.A. equally contributed to this work Notes

The authors declare no competing financial interest.

■

ACKNOWLEDGMENTS This work was supported by the Center for Integrated Smart Sensors funded by the Ministry of Science, ICT and Future Planning as Global Frontier Project (grant no. CISS-20110031848). This research was partially supported by the Pioneer Research Center Program through the National Research Foundation of Korea funded by the Ministry of Science, ICT and Future Planning (grant no. 2012-0009600). This work was partially supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (No. B0126-16-1023, Development on Semi-conductor based Smart Antenna for future mobile communications).

■

REFERENCES

(1) Baldi, L.; Bez, R.; Sandhu, G. Solid-State Electron. 2014, 102, 2− 11. (2) Wang, L.; Yang, C.; Wen, J.; Gai, S. J. Nanomater. 2014, 2014, 1− 10. (3) Makarov, A.; Sverdlov, V.; Selberherr, S. Microelectron. Reliab. 2012, 52, 628−634. (4) Neisser, M.; Wum, S. Adv. Techn. 2015, 4, 235−240. G

DOI: 10.1021/acs.nanolett.6b02824 Nano Lett. XXXX, XXX, XXX−XXX

Letter

Nano Letters (5) Takahashi, K.; Umemoto, M.; Tanaka, N.; Tanida, K.; Nemoto, Y.; Tomita, Y.; Tago, M.; Bonkohara, M. Microelectron. Reliab. 2003, 43, 1267−1279. (6) Han, J.-W.; Ryu, S.-W.; Kim, S.; Kim, C.-J.; Ahn, J.-H.; Choi, S.-J.; Kim, J. S.; Kim, K. H.; Lee, G. S.; Oh, J. S.; Song, M. H.; Park, Y. C.; Kim, J. W.; Choi, Y.-K. IEEE Electron Device Lett. 2008, 29, 632−634. (7) Muller, D. A.; Sorsch, T.; Moccio, S.; Baumann, F. H.; EvansLutterodt, K.; Timp, G. Nature 1999, 399, 758−761. (8) Meindl, J. D.; Chen, Q.; Davis, J. A. Science 2001, 293, 2044− 2049. Dai, Y.-H.; Xu, J.-B.; Xu, H.-F.; Zhao, Y.-Y.; Wang, J.-Y. Mater. Sci. Semicond. Process. 2015, 31, 229−234. (9) Colinge, J. -P. FinFETs and Other Multi-Gate Transistors; Springer; New York, 2008. (10) Ferain, I.; Colinge, C. A.; Colinge, J.-P. Nature 2011, 479, 310− 316. (11) Iwai, H. Microelectron. Eng. 2009, 86, 1520−1528. (12) Lee, H.; Yu, L.-E.; Ryu, S.-W.; Han, J.-W.; Jeon, K.; Jang, D.-Y.; Kim, K.-H.; Lee, J.; Kim, J.-H.; Jeon, S. C.; Lee, G. S.; Oh, J. S.; Park, Y. C.; Bae, W. H.; Lee, H. M.; Yang, J. M.; Yoo, J. J.; Kim, S. I.; Choi, Y.-K. VLSI Symp. Technol. Dig 2006, 58−59. (13) Iwai, H. Solid-State Electron. 2015, 112, 56−67. (14) Singh, N.; Agarwal, A.; Bera, L. K.; Liow, T. Y.; Yang, R.; Rustagi, S. C.; Tung, C. H.; Kumar, R.; Lo, G. Q.; Balasubramanian, N.; Kwong, D. − L. IEEE Electron Device Lett. 2006, 27, 383−386. (15) Barrelet, C. J.; Greytak, A. N.; Lieber, C. M. Nano Lett. 2004, 4, 1981−1985. (16) Hood, L.; Heath, J. R.; Phelps, M. E.; Lin, B. Science 2004, 306, 640−643. (17) Lieber, C. M. MRS Bull. 2003, 28, 486−491. (18) Kempa, T. J.; Day, R. W.; Kim, S.-K.; Park, H.-G.; Lieber, C. M. Energy Environ. Sci. 2013, 6, 719−733. (19) Lee, J.-H.; Zhang, A.; You, S. S.; Lieber, C. M. Nano Lett. 2016, 16, 1509−1513. (20) Lee, B.-H.; Kang, M.-H.; Ahn, D.-C.; Park, J.-Y.; Bang, T.; Jeon, S.-B.; Hur, J.; Lee, D.; Choi, Y.-K. Nano Lett. 2015, 15, 8056−8061. (21) Lee, B.-H.; Hur, J.; Kang, M.-H.; Bang, T.; Ahn, D.-C.; Lee, D.; Kim, K.-H.; Choi, Y.-K. Nano Lett. 2016, 16, 1840−1847. (22) Kim, K. Technol. Digest IEEE Electron Devices Meet. 2010, DOI: 10.1109/IEDM.2010.5703274. (23) Okhonin, S.; Nagoga, M.; Sallese, J. M.; Fazan, P. IEEE Electron Device Lett. 2002, 23, 85−87. (24) Lee, C.-H.; Hur, S.-H.; Shin, Y.-C.; Choi, J.-H.; Park, D.-G.; Kim, K. Appl. Phys. Lett. 2005, 86, 152908. (25) Hubert, A.; Nowak, E.; Tachi, K.; Maffini-Alvaro, V.; Vizioz, C.; Arvet, C.; Colonna, J.-P.; Hartmann, J.-M.; Loup, V.; Baud, L.; Pauliac, S.; Delaye, V.; Carabasse, C.; Molas, G.; Ghibaudo, G.; De Salvo, B.; Faynot, O.; Ernst, T. Technol. Digest IEEE Electron Devices Meet 2009, 1. (26) Fang, W. W.; Singh, N.; Bera, L. K.; Nguyen, H. S.; Rustagi, S. C.; Lo, G. Q.; Balasubramanian, N.; Kwong, D. − L. IEEE Electron Device Lett. 2007, 28, 211−213. (27) Sacchetto, D.; Ben-Jamaa, M. H.; DeMicheli, G. D.; Leblebici, Y. ESSDERC. Proceedings of the European 2009, 245−248. (28) Ng, R. M. Y.; Wang, T.; Liu, F.; Zuo, X.; He, J.; Chan, M. IEEE Electr. Device L. 2009, 30, 520−522. (29) Zhou, Z.; Fossum, J. G.; Lu, Z. IEEE Electron Device Lett. 2009, 30, 565−567. (30) Chang, T. C.; Yan, S. T.; Liu, P. T.; Chen, C. W.; Wu, H. H.; Sze, S. M. Appl. Phys. Lett. 2004, 85, 248−250. (31) Hofmann, F.; Specht, M.; Dorda, U.; Kommling, R.; Dreeskornfeld, L.; Kretz, J.; Stadele, M.; Rosner, W.; Risch, L. SolidState Electron. 2005, 49, 1799−1804. (32) Kuo, J. B.; Lin, S.-C. IEEE Solid-State and Integrated-Circuit Technlogy 2011, 891. (33) Han, J.-W.; Moon, D.-I.; Kim, D.-H.; Choi, Y.-K. IEEE Electron Device Lett. 2009, 30, 1108−1110. (34) Han, J.-W.; Kim, C.-J.; Choi, S.-J.; Kim, D.-H.; Moon, D.-I.; Choi, Y.-K. IEEE Electr. Device L. 2009, 30, 544−546.

H

DOI: 10.1021/acs.nanolett.6b02824 Nano Lett. XXXX, XXX, XXX−XXX