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Functional Inorganic Materials and Devices

Visible light-erasable oxide FET-based nonvolatile memory operated with deep trap interface Taeyoon Kim, Jung Wook Lim, Seong Hyun Lee, Jeho Na, Jiwoon Jeong, Kwang Hoon Jung, Gayoung Kim, and Sun Jin Yun ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b07749 • Publication Date (Web): 12 Jul 2018 Downloaded from http://pubs.acs.org on July 17, 2018

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ACS Applied Materials & Interfaces

Visible light-erasable oxide FET-based nonvolatile memory operated with deep trap interface Taeyoon Kim†, ‡, Jung Wook Lim†,‡,*, Seong Hyun Lee†, Jeho Na†, Jiwoon Jeong†, Kwang Hoon Jung†,‡, Gayoung Kim†, ‡, and Sun Jin Yun†,‡,* †

ICT Materials Research Group, Materials & Components Basic Research Division,

Electronics and Telecommunications Research Institute (ETRI), 218 Gajeong-ro, Yuseonggu, Daejeon 305-700, South Korea ‡

Department of Advanced Device Engineering, University of Science and Technology, 217

Gajeong-ro, Yuseong-gu, Daejeon 305-350, South Korea *Corresponding authors: J. W. Lim, [email protected]; S. J. Yun, [email protected] ABSTRACT. A new concept of a tunneling oxide-free non-volatile memory device with a deep trap interface floating gate is proposed. This device demonstrates a high on/off current ratio of 107 and a sizable memory window due to deep traps at the interface between the channel and gate dielectric layers. Interestingly, irradiation with 400 nm light can completely restore the program state to the initial one (performing an erasing process) attributed to the visible light-sensitive channel layer. Device reproducibility is enhanced by selectively passivating shallow traps at the interface using in-situ H2-plasma treatment. The passivated memory device shows a highly reproducible memory operation and on-state current during the retention baking test at 85 °C. One of the most significant advantages of this visible lighterasable oxide field-effect transistor-based non-volatile memory is its simple structure, which

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is free from deterioration due to the frequent tunneling processes, as compared to conventional non-volatile memory devices with tunneling oxides. KEYWORDS. non-volatile memory (NVM), oxide semiconductor, transistor, plasma treatment, visible light

INTRODUCTION With the rapid growth of the computer and mobile device markets, the demand for personal and network data storage devices is continuously increasing. The most representative Sibased flash memory is non-volatile memory (NVM), which is widely used in the storage device market because of its high integration density and reliability. However, conventional NVM using a tunneling oxide takes a longer time for the program/erase cycle operation than other memory devices with no tunneling oxides; moreover, the charge retention characteristic is likely to be degraded due to defects generated by the repetitive operations in the tunneling oxide.1 Furthermore, the generation of defects inevitably results in the reduction of device lifetime, which is a crucial disadvantage for the currently used multi-level memory applications. To solve this problem, it is necessary to develop an innovative nonvolatile memory without tunneling oxides. Recently, several kinds of nonvolatile memories such as resistive RAM and phase-change RAM have been studied to replace the Si-based flash memory; however, commercialization has been difficult due to their unstable durability, reproducibility, and ambiguous mechanism of memory operation.2,3 Meanwhile, oxide-based metal oxide semiconductor field-effect transistors (oxideMOSFETs) have been actively studied as non-volatile memory devices for applications including transparent and flexible devices, because of their high transmittance in the visible wavelength range and the low deposition temperature of oxides.4–9 Oxide-MOSFETs have a


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much lower off-state leakage current than Si-MOSFETs, allowing low-power memory operation. Conventional oxide-based non-volatile memory generally uses positive and negative gate voltage (VG) pulses to achieve the program and erase states, respectively.4,10 However, the n-type nature of most oxide semiconductors makes it difficult to conduct a sufficient amount of holes in the channel oxides, leading to high power consumption and long erase times; hence, in addition to voltage, the use of other input power sources (e.g., light) would be very useful.11-13 In non-volatile memory, the memory window, the difference between the programming and erasing voltages, should be set to secure a sufficient margin of read voltage (Vread) for stable device operation; wider memory windows can be achieved by producing more defect sites to trap more charges. However, shallow traps adversely affect device stability.14,15 Therefore, it is necessary to selectively exclude shallow trap sites to satisfy both a wide memory window and high device stability. In this work, a novel oxide FET-based non-volatile memory device without tunneling oxide is proposed, employing the deep trap interface (DI) as a simple floating gate. Some of the earlier works on non-volatile memories utilizing interface traps had still employed tunnel oxides.16,17 In the absence of a tunnel layer, reproducibility could not have been guaranteed because very defective films had been deposited to form interface trap sites.17 We selected TiO2 as the channel layer as it has high photo-sensitivity and a broad range of wavelengths (including visible light); moreover, it can be used as an input power source, making it highly scalable and adaptable to various future applications. We fabricated memory devices based on a MOSFET possessing a TiO2 channel, and evaluated critical parameters such as the on/off ratio and memory window. As it is essential to ensure the stable operation of injection, storage, and removal of charges in non-volatile memory devices, we carefully characterized the device operation and evaluated its reproducibility and stability


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using a retention bake test. We expect that our simple TiO2-based non-volatile memory device, which is completely erasable only by light irradiation and shows reproducible and stable operation, will greatly contribute to the future development of a wide range of electronic devices. RESULTS AND DISCUSSION Figure 1 shows schematic diagrams comparing the structure of the proposed tunneling oxidefree deep trap interface (TOFDI) TiO2 non-volatile memory device with conventional nonvolatile memory devices. The earlier non-volatile memory devices included a metal floatinggate, as shown in Figure 1(a).1 Figure 1(b) shows the Si-oxide-nitride-oxide-Si (SONOS)type non-volatile memory device, where a dielectric material such as silicon nitride replaces the metal floating-gate.18–20 In addition, various functional layers have been studied as charge trapping layer or blocking layer in SONOS structure.21,22 In the SONOS-type memory, the program/erase ability is superior to that of the conventional floating-gate memory. However, because of the presence of tunneling oxide, a concern arises that the device lifetime would be shortened due to the defects created by repetitive tunneling.1, 23 Therefore, the degree of memory integration is limited. Nanocrystal floating-gate memory devices have also been developed for simplifying the multi-stacked structure;5,12,24 however, they have drawbacks such as complex manufacturing processes of nanocrystals and insufficient reliability and operational stability.1 When the lateral dimension of the non-volatile memory device decreases below 20 nm in a floating-gate structure, floating-gate interference and parasitic capacitance become severe.25 To simplify the manufacturing process, Qian et al. reported an amorphous InGaZnO memory device employing metal nanoparticles embedded in the gate oxide to play the role of a floating gate.26 However, this memory device showed unstable operation and a high erasing voltage. Recently, a vertical 3D NAND NVM device was


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manufactured to address the integration limitation of the devices.27 However, it requires a complicated manufacturing process; moreover, only limited reduction in the thickness of the floating gate and tunneling oxide can be achieved. Therefore, we were motivated to design a simplified innovative structure that removes floating gates and tunneling oxides to solve the fundamental problems arising from highly integrated processes. Recently, Lee et al. demonstrated the operation of a memory device with no floating gate; however, limitations such as a low on/off ratio and instability at the required operation temperature, were observed.28 Our proposed TOFDI TiO2 non-volatile memory device design is shown in Figure 1(c). This structure employs TiO2 films as a channel material and has only a gate oxide. Unlike conventional non-volatile memory, it uses charge trap sites at the interface as a floating gate and requires no tunneling oxide. Al2O3 and TiO2 films were deposited in-situ by the plasmaenhanced atomic layer deposition (PEALD) method, and H2 plasma treatment was performed on the interface between Al2O3 and TiO2 (Figure S1) to selectively passivate shallow trap sites. Interestingly, we discovered a new restoration method that returns the program state to its initial state only with violet light (VL) irradiation without any additional voltage pulse (that has been used for erasing in conventional memory devices). Figure 2 (a) shows XRD data of TiO2 films deposited at 150 and 300 °C. The TiO2 films deposited at 150 °C were amorphous, while those deposited at 300 °C had the anatase structure. The peaks at 25.15° and 48.01° correspond to the (101) and (200) planes of the anatase phase of TiO2.29, 30 In general, the anatase phase has superior electrical properties to the rutile phase, which forms at temperatures above 300 °C.31 Therefore, we used a process temperature of 300 °C for fabricating the memory devices. Figure 2 (b) shows the XRD data of TiO2 deposited at 300 °C as a function of film thickness. The XRD peak intensity


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decreased considerably with decreasing film thickness from 30 to 10 nm. For oxide-based MOSFETs, which are advantageous for flexible and transparent applications, the thickness of the channel layer should be as low as possible while maintaining good crystallinity to ensure high-mobility devices. Hence, the 30 nm TiO2 films with good crystallinity were thought to be the most suitable for our devices. Figure 3 (a) shows the cross-sectional transmission electron microscopy (TEM) image of a TiO2 non-volatile memory device composed of highly uniform Al2O3 and TiO2 films deposited by PEALD. Figure 3 (b) shows an HR-TEM micrograph of the area of the TiO2 film denoted by the square in Figure 3 (a), where wellordered lattice planes were observed. The lattice spacing was approximately 0.35 nm, which corresponds to the interlayer distance of the (101) crystal plane of the anatase TiO2 phase.32 This result agreed well with the XRD data. In addition, the atomic force microscopy (AFM) image of a 30 nm TiO2 film on Al2O3 also showed crystalline TiO2 grains of the anatase phase in Figure S2. According to the AFM images (Figure S2 (c) and S2 (d)), the grain size of crystalline TiO2 is ranged from 50 nm to 200 nm. Figure 4 (a) shows a schematic diagram of the structure of the TiO2 non-volatile memory with an inverted staggered bottom-gate structure. Figure 4 (b) shows the n-type transfer characteristics of the TiO2 non-volatile memory when the drain voltage (VD) was set to 1.0 V. The on/off current ratio was as high as 1.7 × 107, much larger than the value of 103 obtained in a previous study using charge trap sites.28 The gate current (IG) is also plotted in Figure 4 (b). The threshold voltage (Vth) and the field-effect mobility (µFE) were calculated from ID vs VG and ID1/2 vs VG curves in Figure 4 (c) and Supporting Information. Figure 4 (d) shows output characteristics at VG = 1.0, 5.0, and 10.0 V. The channel conductance significantly increased with increasing VG, while the output curves showed clear pinch-off and saturation behaviors.


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For memory operations, our TiO2 non-volatile memory devices used a bias pulse for programming and VL irradiation for erasing, unlike other NVMs that use bias pulses for both functions. Figure 5 (a) shows a schematic illustration of the VL irradiation of the TiO2 nonvolatile memory. For programming, a positive bias pulse of 50 V was applied at the bottom gate. We measured the breakdown characteristic curve of 80 nm-thick Al2O3 (Figure S4(a)) and the gate current with the programming voltage of 50 V (Figure S4(b)). This result shows that gate current (IG) were 5-orders of magnitude lower than ID. Then, VL was used to irradiate the TiO2 channel to erase the state Unprogrammed device did not respond to VL irradiation at all. Figure 5 (b) shows the characteristic ID–VG curves in the program and erase states of the TiO2 non-volatile memory, where the difference between the transfer curves of the initial and program states represents the memory window (8.5 V in this case). Programming with a positive bias pulse is due to electrons held in trap sites at the interface. Subsequently, the device returned to the initial state, i.e., optical restoration was perfectly achieved using VL irradiation of the samples, as shown in Figure 5 (b). Unlike the previous literature10, we found that the transfer curves of this TiO2 memory device in the programmed state were not shifted toward the erase state at all by applying negative voltage. This indicates that trapped electrons cannot be detrapped by electric field. On the other hand, the programmed transfer curves completely shifted to recover the erase state by irradiating VL. From this observation, we learned that the trapped electrons could be neutralized by photogenerated holes rather than be detrapped by an electric field. For photo-restoration, the light of wavelength similar to the band gap energy, such as violet light, is the most effective and reproducible. Light with energy much greater than the band gap generated excessive carriers, which made it difficult to operate reliably It is important to ensure the stability and reproducibility of memory devices for practical applications. Crupi et al. described many deep and shallow trap states present at the interface


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between adjacent oxides.33 The shallow traps need to be selectively eliminated; they degrade the stability of memory operation as charges in such traps can be easily dissipated.34,35 In this study, we performed an in-situ H2-plasma treatment on the interface between Al2O3 and TiO2 during the PEALD process to selectively passivate shallow traps, while retaining the stable deep traps at the interface. A. Polyakov et al. reported that ex-situ H2 treatment selectively eliminated charges in shallow traps compared to deep ones.36-38 The electrical characteristics of the devices fabricated with various H2-plasma treatment times are presented in Figure 6, Table S1 and Figure S3. The hysteresis of the transfer curves between the forward and reverse scanning provide information about the amount of mobile trap charges. Figure S3 (a) and (b) show that the magnitude of hysteresis reduced considerably for H2-passivated samples compared to that of the untreated samples. The data in Table S1 indicates that a H2 plasma treatment time of 24 s was sufficient to passivate shallow trap sites. The transfer curves shown in Figure 5 (c) confirm that the plasma-treated device was effectively restored from the program state to the initial state after VL irradiation. This indicates that the optical restoration was not affected by H2 passivation. Although the memory window (magnitude of Vth shift) was reduced by H2 treatment, a sufficiently large memory window was obtained. The improved device stability due to the H2-plasma treatment is clearly demonstrated in Figure 5 (d), showing decay of the normalized ID over time for samples prepared with and without H2 treatment after unit light pulse. Reduced decay of ID (hence, fewer shallow traps) was observed for the passivated sample, indicating more stable operation. Considering the operation of the TiO2 non-volatile memory devices, we propose a mechanism of restoration by VL irradiation in the cases with and without H2 treatment (Figure 7 and S5, respectively). In Figure 7 (a), when a positive VG pulse (VG = 50 V, VD = 1


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V) was applied for programming the memory, shallow and deep trap sites at the interface between TiO2 and Al2O3 capture electrons in the channel (a-2). The trapped electrons recombine with holes photo-generated by the VL irradiation (a-3) to form neutral trap sites, and the initial state can be fully recovered (a-1). For the H2-treated sample, shallow traps are selectively passivated by hydrogen atoms in the initial state (b-1). Therefore, only deep traps can trap negative charges in the program state (b-2) and can be neutralized by the photogenerated holes during VL irradiation (b-3), as depicted in Figure 7 (b). In order to verify the stable operation of the TiO2 non-volatile memory, we alternately applied VG and VL pulses to the samples fabricated with and without plasma treatment, as shown in Figure 8 (a) and (b). In order to maintain the on/off current ratio of 106, VG pulses of 50 V (2 s) and 60 V (5 s) were applied to the samples with and without H2 passivation, respectively. For the sample without H2 passivation (Figure 8 (c)), a considerable attenuation of on- and off-current levels was repeatedly observed within each pulse, while the on/off current ratio was reproducible, even after ten pulses. The H2-passivated samples showed clear improvement in the on- and off-current levels in each pulse for repeated operation (Figure 8 (d)). These results demonstrate the effectiveness of the in-situ passivation process for ensuring stable retention characteristics of TOFDI TiO2 non-volatile memory devices. For the practical application of non-volatile memory devices, reproducible operation after exposure to harsh environmental conditions (e.g., high temperature) is critical. In a previous literature, considerable changes in the characteristics of the device due to various atmospheric species such as oxygen have been reported.39 On the contrary, TOFDI memory in this paper shows stable operation over a long period of time as shown in the program/erase cycle diagram of Figure 9. Figure 9 (a) shows typical transfer curves of the program and erase states, and the current levels observed at Vread. Figure 9 (b) and (c) shows the noticeable


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effect of the passivation treatment on the ID curves over time in the program and erase state. The current values of the samples with H2 treatment were nearly constant, indicating stable operation over the accumulated storage time of 6 × 105 s during the retention bake test at 85 °C. Therefore, we could conclude that there is negligible effect of environmental species on interface trap sites. Figure 9 (d) and (e) also show the effect of H2 passivation treatment on the reproducibility of Vth values in the program and erase states during the retention bake test at 85 °C. The devices were programmed by a VG pulse of 50 V for 2 s, and then erased by a light pulse for 3 s. In the sample fabricated without H2 treatment of Figure 9 (d), the Vth values showed highly fluctuating behavior due to the shallow trap sites causing unstable charging at high temperature. However, the Vth values of the H2-passivated sample were consistently maintained both in the program and erase states, producing a stable memory window; the memory windows of the H2-passivated sample at different temperatures of 85 °C and 25 °C were similar, as shown in Figure 9 (e). These encouraging results demonstrate that the passivation of shallow trap sites ensures stable and reproducible memory operation, even at high temperature. The drain current was measured as a function of the number of program/erase cycles, as shown in Figure S6. Reproducible level cycles were obtained, and the drain current values degraded by less than 10% over 100 cycles. Also, we carried out C-V measurement of the n++ Si/Al2O3/TiO2 MOS capacitors. The CV characteristic curves showed the clockwise hysteresis, which demonstrates that mobile charges are due to electron traps as reported in previous literature40,41. We roughly evaluated the number of mobile charges (Dit), which is a type of shallow traps, by integrating hysteresis curves. From comparison of Dit for the samples with and without plasma treatment, we confirmed that the Dit of the sample without H2 plasma treatment is 2.4 times larger than that with plasma treatment. The result indicates that shallow trap density was considerably decreased by H2 plasma treatment.


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TOFDI TiO2 memory device erasable by violet light has attractive advantages and also limitations to be overcome. In some applications that the device is integrated with optical devices, the optical signal can simultaneously operate the memory device. Moreover, in principle, it is more advantageous for high speed devices because the photo-switching is faster than the electric signal. On the other hand, in transparent device applications, external violet light may interfere the device operation. However, this limitation would be overcome by designing a proper device structure in further study. CONCLUSIONS We fabricated a novel tunneling oxide-free TiO2 NVM with Al2O3 gate dielectrics using a PEALD method. The MOSFET-based memory device uses the interface between the TiO2 channel and Al2O3 layers, which contain trap sites, as a floating gate. The on/off current ratio and Vth of the TiO2 MOSFET were 1.7 × 107 and −1.0 V in its initial state, respectively. The device was programmed by applying VG. One of the significant and novel characteristics of this device is that the program state can be erased (and the initial state completely recovered) using only VL irradiation. Such complete recovery is attributed to the highly photosensitive TiO2 channel layer. This optical restoration phenomenon could be explained as the recombination of trapped electrons with photo-generated holes, restoring the charged state to the initial neutral one. We also demonstrated that in-situ H2 plasma treatment at the interface between the Al2O3 and TiO2 could selectively passivate shallow traps, thus improving the stability and reproducibility of memory device operation. For successful commercialization of NVM operated by a bias voltage and a light pulse, attenuation of ID and the unstable operational voltage should be minimized. The H2 treatment was shown to improve device stability and reproducibility even at a high temperature of 85 °C. The demonstrated approach of developing a simple structured device with reliable memory operation is advantageous for


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highly integrated NVM devices, especially for flexible and transparent applications in the near future. In particular, since our proposed device has no tunneling oxide, performance degradation due to repeated operation will be much reduced. Moreover, this device would become more commercially attractive when it is expanded to multi-level memory devices requiring a very high degree of reproducibility and stability.

METHODS Fabrication of TiO2-based memory devices: For the fabrication of TiO2-MOSFETs, 80 nm Al2O3 gate dielectric and 30 nm TiO2 channel layers were sequentially deposited by PEALD on a low-resistivity (< 0.005 Ω·cm) n-type Si wafer, which also served as the back-gate electrode. Figure S1 shows the pulse sequence used to deposit the Al2O3 and TiO2 films, including in-situ H2 plasma treatment at the interface. The TiO2 channel areas were patterned by photolithography and reactive ion etching processes. The source and drain electrodes were defined by a lift-off process and Al electrodes were deposited by a thermal evaporation method. In the inverted staggered bottom-gate MOSFET structure, the top portion of the channel was exposed to the air environment during electrical characterizations. The TiO2 MOSFETs prepared to study the programming and erasing of the memory device had a channel length and width of 10 and 40 µm, respectively, while channels 15 µm in length and 40 µm in width were used for the reproducibility measurements. In order to verify the operational stability and reproducibility of the memory device at a high temperature, a retention bake test was carried out. The devices were stored at 85 °C and intermittently removed from the furnace for a short time to measure the transfer curve at 25 °C, after which the samples were returned to the furnace.


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Characterization techniques: XRD (D/MAX-2500, RIGAKU) measurements were performed in order to analyze the crystallinity of the TiO2 films. We also performed a series of surface analyses using AFM (XE-100, Park System), cross-sectional TEM, and highresolution TEM (HRTEM; JEOL 2100F, accelerating voltage of 200 kV) to investigate the surface morphology and microstructure of the films. The electrical characteristics of the fabricated TiO2 MOSFETs were measured using a parameter analyzer (Keithley 4200) in the dark and under VL irradiation at 25 °C. We used standard LEDs (center wavelength of 400 nm) as a light source for the VL with an incident power of 0.13 W/cm2. The gate bias condition was VG = 0 V during the erase by VL irradiation. ASSOCIATED CONTENT The Supporting Information is available free of charge on the ACS Publications website at DOI: Additional details concerning the ALD process, XRD, TEM and AFM characterizations, and electrical properties are provided. AUTHOR INFORMATION Corresponding Author * Corresponding authors: J. W. Lim, [email protected]; S. J. Yun, [email protected] Author Contributions T.K., J.W.L. and S.J.Y. conceived and designed the experiments. T.K., J.W.L., S.J.Y., J.N., and S.H.L. analyzed the data. T.K., G.H.J. and J.H.J. fabricated the devices and performed the measurements. All authors discussed the results and commented on the manuscript.

ACKNOWLEDGMENT


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This work was supported by the Institute for Information and Communications Technology Promotion (IITP) grant funded by the Korea government (MSIT) (Grant No. 2016-0-00576, Fundamental technologies of 2D materials and devices for the platform of new-functional smart devices).

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[21] Sugizaki, T.; Kobayashi, M.; Ishidao, M.; Minakata, H.; Yamaguchi, M.; Tamura, Y.; Sugiyama, Y.; Nakanishi, T.; Tanaka, H. In Novel multi-bit SONOS type flash memory using a high-k charge trapping layer, VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on, IEEE: 2003; pp 27-28. [22] Ji, H.; Wei, Y.; Zhang, X.; Jiang, R. Improvement of Charge Injection Using Ferroelectric Si: HfO2 As Blocking Layer in MONOS Charge Trapping Memory. IEEE Journal of the Electron Devices Society 2018, 6 (1), 121-125. [23] Hota, M. K.; Alshammari, F. H.; Salama, K. N.; Alshareef, H. N. Transparent Flash Memory Using Single Ta2O5 Layer for Both Charge-Trapping and Tunneling Dielectrics. ACS Appl. Mater. Interfaces. 2017, 9, 21856. [24] Jang, J.; Park, J. C.; Kong, D.; Kim, D. M.; Lee, J. -S.; Sohn, B. -H. Endurance Characteristics of Amorphous-InGaZnO Transparent Flash Memory with Gold Nanocrystal Storage Layer. IEEE Trans. Electron Devices 2011, 58, 3940. [25] Lee, J. -S. Recent Progress in Gold Nanoparticle-Based Non-Volatile Memory Devices. Gold Bull. 2010, 43, 189. [26] Qian, S. -B.; Wang, Y. -P.; Shao, Y.; Liu, W. -J.; Ding, S. -J. Plasma-Assisted Atomic Layer Deposition of High-Density Ni Nanoparticles for Amorphous In-Ga-Zn-O Thin Film Transistor Memory. Nanoscale Res. Lett. 2017, 12, 138. [27] Kim, H.; Ahn, S. -J.; Shin, Y. G.; Lee, K.; Jung, E. Evolution of NAND Flash Memory: From 2D to 3D as a Storage Market Leader. In Proc. Memory Workshop International IEEE 2017, 1.


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FIGURES

Figure 1. Schematic diagrams comparing the structure of conventional non-volatile memory devices with the proposed design. a) Conventional floating-gate non-volatile memory, b) silicon-oxide-nitride-oxide-semiconductor (SONOS) memory, and c) the tunneling oxide-free deep-trap interface (TOFDI) TiO2 non-volatile memory proposed in this study.


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Figure 2. a) XRD patterns of 30 nm TiO2 films deposited on SiO2-grown Si substrate as a function of deposition temperature. b) XRD patterns of the TiO2 films deposited at 300 °C as a function of film thickness.


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Figure 3. a) Cross-sectional TEM image and b) HR-TEM image of a representative TOFDI TiO2 non-volatile memory device structure.


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Figure 4. Characterization of the electrical properties of the TOFDI TiO2 non-volatile memory devices. a) Schematic illustration of the TiO2-MOSFET channel layer grown at 300 °C used for the electrical characterization. b) Transfer characteristics (L/W = 10/40 µm) of TiO2 MOSFETs. (c) ID vs. VG and (ID)1/2 vs. VG curves. d) Output curves of the TiO2 MOSFETs measured at different gate voltages.


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Figure 5. Operation of the TOFDI TiO2 memory device under light irradiation. a) Schematic diagram showing the experimental setup. b, c) Light-restoration characteristics (at VD = 1.0 V) of the program states b) without H2 treatment and c) with H2 treatment for 24 s. (d) Decay of ID over time for samples prepared with and without H2 treatment after unit light pulse (Vread = 3 V for H2 treatment 0 s; 2 V for H2 treatment 24 s).


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Figure 6. µFE, Vth, and ∆Vth of TOFDI TiO2 memory with respect to H2 plasma treatment time. The electrical characteristics of the fabricated TiO2 memory were measured in the dark.


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Figure 7. Conceptual schematics of the restoration procedure of the device a) without H2 treatment and b) with H2 treatment, depicting the (a-1, b-1) initial state, (a-2, b-2) saturated state, and (a-3, b-3) restoration by VL irradiation. The trap sites at the interface between the channel and gate dielectric capture electrons when the VG bias is applied, and are neutralized by holes generated by VL irradiation.


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Figure 8. Cyclic operation of the TOFDI TiO2 memory showing high responsivity and stability. a, b) Time trace of the application of pulsed gate bias (50 V and 60 V) and VL (green and blue lines, respectively). c, d) On/off drain current and switching behavior as functions of the applied gate voltage and VL shown in a) for devices with c) no H2 treatment


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(VG = 3 V, VD = 1 V, programming VG = 50 V for 2 s, and d) H2 treatment for 24 s (VG = 2 V, VD = 1 V, programming VG = 60 V for 5 s). The VL was switched on for 3 s. (L/W=15 µm / 40 µm)

Figure 9. Characterization of the transfer characteristics and the memory window of the TOFDI TiO2 memory devices. a) Typical transfer characteristics (ID vs. VG) of n-type MOSFETs in the program and erase states. b, c) Time evolution of the ID of the program and erased state for devices with no H2 treatment and H2 treatment for 24 s measured at 25 °C and 85 °C. d, e) Reproducibility measurements as a function of time for devices with c) no H2 treatment and d) H2 treatment for 24 s in the program (+50 V for 2 s) and erase (VL for 3 s) states at 25 °C and 85 °C.


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TABLE OF CONTENTS ENTRY


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Visible light-erasable oxide FET-based non ... - ACS Publications

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