ARTICLE pubs.acs.org/crystal
Defect-Free GaAs/AlGaAs Core Shell Nanowires on Si Substrates Jung-Hyun Kang,*,† Qiang Gao,† Hannah J. Joyce,‡ Hark Hoe Tan,† Chennupati Jagadish,† Yong Kim,§ Yanan Guo,|| Hongyi Xu,|| Jin Zou,|| Melodie A. Fickenscher,^ Leigh M. Smith,^ Howard E. Jackson,^ and Jan M. Yarrison-Rice# †
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Department of Electronic Materials Engineering, Research School of Physics and Engineering, The Australian National University, Canberra, Australian Capital Territory 0200, Australia ‡ Clarendon Laboratory, Department of Physics, University of Oxford, Parks Road, Oxford OX1 3PU, United Kingdom § Department of Physics, College of Natural Sciences, Dong-A University, Hadan 840, Sahagu, Busan 604-714, Korea Materials Engineering and Centre for Microscopy and Microanalysis, University of Queensland, St. Lucia, Queensland 4072, Australia ^ Department of Physics, University of Cincinnati, Cincinnati, Ohio 45221, United States # Department of Physics, Miami University, Oxford, Ohio 45056, United States ABSTRACT: We report straight and vertically aligned defect-free GaAs nanowires grown on Si(111) substrates by metal organic chemical vapor deposition. By deposition of thin GaAs buffer layers on Si substrates, these nanowires could be grown on the buffer layers with much less stringent conditions as otherwise imposed by epitaxy of III V compounds on Si. Also, crystal-defect-free GaAs nanowires were grown by using either a twotemperature growth mode consisting of a short initial nucleation step under higher temperature followed by subsequent growth under lower temperature or a rapid growth rate mode with high source flow rate. These two growth modes not only eliminated planar crystallographic defects but also significantly reduced tapering. Core shell GaAs AlGaAs nanowires grown by the twotemperature growth mode showed improved optical properties with strong photoluminescence and long carrier life times.
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ver the past several years, nanowires have come into the spotlight as nanocomponents of future integrated devices. Due to the superior electrical and optical properties of III V compound semiconductors, III V nanowires (NWs) such as gallium arsenide (GaAs), gallium phosphide (GaP), indium arsenide (InAs), and indium phosphide (InP), have been investigated intensively for application in nanoscale optoelectronic devices.1 3 It is therefore crucial to fabricate nanowires with good morphology, high-quality crystal structure, and controllable composition. Furthermore, III V compound semiconductor nanowires exhibit great potential for integration with the established Si microelectronics technology.4 Nevertheless, there are specific problems to be overcome when forming a heterostructure interface between two dissimilar materials from groups III V and IV5,6 such as lattice and thermal expansion mismatch, the formation of antiphase domain, and, in particular, the existence of a native oxide layer on the Si surface.5,7 9 As recently demonstrated, GaAs NWs can be epitaxially grown on Si(111) substrates using the vapor liquid solid (VLS) mechanism by coating Si with thin GaAs buffer layers.10 Through the optimization of a double buffer layer structure consisting of an initial layer grown with low V/III ratio at low temperature and the subsequent layer grown with high V/III ratio at high temperature, not only the specific difficulties of growing III V compound semiconductors on Si substrates could be eliminated, but also nanowire growth could be achieved over a broader growth parameter window. 10,11 For optoelectronic device r 2011 American Chemical Society
application, nanowires must have pure crystal structure without structural defects such as twin defects, phase polytypism, and stacking faults, which may give rise to deterioration of optical and carrier transport properties.12 In order to overcome these crystal defects, many improvements in the growth of nanowires have been made by controlling the growth conditions, such as temperature, V/III ratio, or precursor flow.3,13,14 In this paper, we investigate defect-free GaAs NWs grown on Si substrates by controlling the growth parameters. First, GaAs buffer layers were grown onto the surface of Si substrates and subsequently annealed prior to the growth of nanowires. Using two separate growth temperatures for the “nucleation” stage and the “growth” stage and simultaneously controlling precursor flow rates, we were able to substantially reduce unintentional radial growth to obtain uniform and untapered nanowires that are free of planar defects. The combination of buffer layers and optimized nanowire growth conditions greatly increased the yield of vertical GaAs NWs. In addition, for optical spectroscopy measurement, a radial heterostructure (core shell structure) was also grown with an AlGaAs shell and GaAs cap layers. This AlGaAs shell has a function to passivate the GaAs surface, reducing nonradiative surface-related recombination.10 Received: March 22, 2011 Revised: May 15, 2011 Published: May 17, 2011 3109
dx.doi.org/10.1021/cg2003657 | Cryst. Growth Des. 2011, 11, 3109–3114
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Figure 1. Schematics of three types of GaAs NWs: NW0 grown by normal procedures as a standard sample, NW1 grown by two-temperature growth mode, and NW2 grown by a rapid growth rate mode. The / indicates in-situ annealed double GaAs buffer layers, T(n) is nucleation temperature, T(g) is growth temperature, t(n) is nucleation time, t(g) is growth time, and R(g) is growth rate.
The GaAs NWs were grown on Si(111) substrates coated with GaAs buffer layers. Both GaAs layers and nanowires were grown by horizontal flow low-pressure metal organic vapor-phase epitaxy (MOVPE) at 100 mbar. Trimethylgallium (TMGa) and arsine (AsH3) were used as group III and V source materials, respectively. Si substrates were [111] oriented with 4 miscut toward the [112] direction. The basic treatment method of Si substrates follows the previous works: the substrates were treated with trichloroethylene (TCE), acetone, and methanol in a consecutive order, followed by HF etching and rinsing with DI water. The substrates were immediately transferred into the metal organic chemical vapor deposition (MOCVD) reactor, and preannealed under H2 atmosphere to remove remaining contaminants and then under AsH3 to create an As-rich surface. A GaAs double buffer layer was then grown and annealed according to the conditions reported in ref 10. These GaAs-coated Si substrates were taken out of the MOCVD reactor and then functionalized by immersion in poly(L-lysine) (PLL) solution for 1 min. This PLL treatment gives the surface a positive charge to attach the negatively charged colloidal Au nanoparticles. After rinsing in DI water, a droplet of Au colloidal solution containing Au particles of 50 nm diameter (4.5 1010 nanoparticles/mL) was applied, and then the substrates were subsequently rinsed with DI water. Finally the wafers were loaded into the reactor and annealed at 750 C under AsH3 ambient atmosphere before nanowire growth. Three different types of GaAs NWs were grown, and their schematics are shown in Figure 1. First, standard GaAs NWs were grown at 450 C for 30 min with a V/III ratio of 46.3 (TMGa = 1.157 10 5 mol/min and AsH3 = 5.357 10 4 mol/min) as a reference (NW0). The second type of GaAs NWs was grown by a two-temperature growth mode (NW1), where initially GaAs NWs were grown at a nucleation temperature, Tn, of 450 C for 1 min and then continued for 30 min while the growth temperature, Tg, was reduced to 375 C (cooling from 450 to 375 C took about 10 min). The V/III ratio was constantly maintained at 46.3. The last set of GaAs NWs was grown with a rapid growth rate method (NW2). The nanowires were grown at 450 C for 6 min with the TMGa flow rate increased by a factor of 5 while the V/III ratio was kept at 46.3 (TMGa = 5.785 10 5 mol/min and AsH3 = 2.679 10 3 mol/min; please note that
Figure 2. (a, b, c) SEM of NW0, NW1, and NW2, respectively. The samples were tilted 45 from their surface normal. Arrows indicate surface grooves of nanowires; all scale bars are 1 μm. (d, e, f) Highresolution SEM images, closed-up to the body of NW0, NW1, and NW2 with top-viewed images of single NWs (inset); the samples were tilted 10 from their surface normal. Scale bars represent 200 nm.
the growth time was reduced to have a comparable length as NW0). Due to the high nonradiative surface recombination rate of carriers on the GaAs surface,15 an AlGaAs shell was grown over the GaAs NWs for optical characterization. The AlGaAs shell growth was carried out at 650 C for 20 min with an Al vapor concentration of 26% and the same flows of TMGa and AsH3 as described earlier. Finally, in order to prevent oxidation of the AlGaAs shell from exposure to air, a thin GaAs cap layer was grown at 650 C for 5 min. All nanowires were characterized by field emission-scanning electron microscopy (FE-SEM), transmission electronic microscopy (TEM), energy-dispersive spectroscopy (EDS), microphotoluminescence (μ-PL), and time-resolved photoluminescence (TR-PL) measurements. FE-SEM images were obtained using Zeiss Ultraplus with an acceleration voltage of 3 kV. TEM and EDS were carried out using a FEI Tecnai F30 F20 equipped with 3110
dx.doi.org/10.1021/cg2003657 |Cryst. Growth Des. 2011, 11, 3109–3114
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Figure 4. Plot of NW diameter measured at distance from the top of nanowires and illustration of the change in diameter per unit of NW length (ΔD/ΔL) (inset). All three types of GaAs NWs were measured at each 0.5 μm point; all error bars represent average diameter with about 5 nm. Figure 3. TEM images with inset HRTEM images of (a) NW0, (b) NW1, and (c) NW2 and (d) cross-sectional TEM image showing clearly the zinc-blende (ZB) structure (bottom inset) with truncated triangular shape and schematic image (upper inset) of shape change. All scale bars in inset images are 5 nm.
an EDS system. For μ-PL and TR-PL measurements, the wires were mechanically dispersed on a silicon substrate and placed in a continuous flow helium cryostat at about 15 K. Circularly polarized 750 nm (1.65 eV), 200 fs pulses at a repetition rate of 76 MHz were used for excitation. The resulting micro-PL emission was collected through a 50/0.5 numerical aperture long working length microscope objective. The collected light was then dispersed using a 1200 grooves/mm grating on a 0.25 m Newport spectrometer and a thermoelectrically cooled CCD detector (2000 800 pixels). Figure 2 shows overall morphology and shape of three types of GaAs NWs grown on Si(111) substrates coated with a GaAs double buffer layer. All nanowires are vertically aligned with a 4 tilt from the substrate normal due to the 4 miscut of the Si substrates. This indicates that the GaAs NWs bear an epitaxial relationship to the Si substrates. The buffer layer can be clearly seen in these SEM images with a flat top surface but terrace-like structure.10 In Figure 2a, the reference GaAs NWs (NW0) have a straight and vertical morphology. The nanowires, however, show serrated sidewalls (surface grooves; indicated by arrows) and substantial tapering,10 which are undesirable for device applications. Figure 2d, a high-resolution SEM image to the body of the nanowires and top-view image (inset), shows the surface grooves and rotated body segments more clearly (indicated by an arrow) due to the side faceting behavior.10,16 On the other hand, GaAs NWs grown by the two-temperature mode (NW1) in Figure 2b show much improved morphology with little tapering and smooth sidewalls. However, some nanowires have nonvertical growth directions or form whiskers on the tip possibly due to the temperature change (from 450 to 375 C) during nanowire growth or low growth temperature.17 It should be noted that without the nucleation step at 450 C, all nanowires grown (on GaAs) at 375 C were kinked.13 In Figure 2c, GaAs NWs with a
high growth rate (NW2) uniformly exhibit straight and vertical orientation. A few of nanowires show surface grooves (indicated by an arrow), which might be due to growth irregularity from the nucleation stage. However, only a small fraction of the nanowires grown under high growth rate mode shows such defects and most nanowires have smooth surface morphology as shown in Figure 2f with less tapering than NW0 similar to those reported in ref 14 where GaAs NWs were grown on GaAs(111)B substrate. The TEM and high-resolution TEM (HRTEM) images of these three types of nanowires are shown in Figure 3a c. All nanowires have the zinc-blende (ZB) crystal structure, which is consistent with our previous reports.13,14 NW0, same as shown in our previous work,10 has many 180 rotated crystal segments (a dark band) with serrated sidewalls, which is associated with side faceting behavior due to twin defects and surface tension at high temperature (450 C)10,16,18 20 (Figure 3a). The inset shows a thin twin defect across two ZB crystal segments (A-B-A type). In Figure 3b,c, however, NW1 and 2 show pure ZB crystal structures without any structural defects and have a smooth surface. It is believed that the low-temperature growth in twotemperature growth mode for NW1 results in such smooth sidewalls13 and twin-free ZB crystal structure (Figure 3b). In the case of NW2, where high growth rate was adopted (Figure 3c), high concentration of Ga and As adatoms are believed to play a role to reduce Au-particle surface and Au GaAs interfacial tension14 to hinder the formation of twin planes.21 Group III V semiconductor nanowires usually have truncated triangular or near hexagonal cross-sectional shape with {110}, {111}, or {112} facets.10,18,19,22,23 All facets of our GaAs NWs in this study belong to {112}. However, the different radial growth rates from two types of {112} atomic planes, that is, {112}A, the surface of group III-rich materials, and {112}B, the surface of group V-rich materials, resulted in a truncated triangular cross-sectional shape in NW0 (Figure 3d).16,19,22,23 In contrast, the other two types of nanowires (NW1 and NW2) have nearly perfect hexagonal shape. This difference is due to the amount of radial growth: the triangular cross section is only apparent in the cases with significant radial growth such as NW0. 3111
dx.doi.org/10.1021/cg2003657 |Cryst. Growth Des. 2011, 11, 3109–3114
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Table 1. Summary of Morphological and Structural Characteristics for NW0 2 samples growth mode length (avg)
NW0 standard growth ∼7.7 μm ((0.3)
NW1 two-temperature growth ∼3.8 μm ((0.2)
NW2 rapid growth rate ∼4.5 μm ((0.2)
tapering parameter,
∼29.0 nm/μm
∼12.8 nm/μm
∼23.2 nm/μm
truncated triangular pillar with defects
clear hexagonal pillar without
near-hexagonal pillar with
ΔD/ΔL (avg) cross-sectional shape of NWs
(twins, surface grooves)
any plane defects
almost no plane defects
yield of vertical NWs
over 95%
∼80% (kinking, different
∼90% (some different
Æ111æ direction)
Æ111æ direction)
crystal structure of NWs
zinc blende (ZB) structure with many twin defects and saw-teeth side walls
ZB structure without lattice defect
ZB structure with little lattice defect
Figure 5. (a) Schematic of core shell (CS) GaAs NWs with AlGaAs shell grown on Si(111) substrates coated with GaAs buffer layers; (b d) SEM images of CS NW0 2—all scale bars are 1 μm and samples are tilted 45; (e) TEM images of single GaAs core NW (upper image) and GaAs/AlGaAs CS NW (bottom image) with NW1 as core.
The radial growth can be characterized by the plot of NW diameter as a function of NW length as shown in Figure 4. It plots the nanowire diameter measured at different distances from the tip of nanowires (inset image) for these three different types of nanowires. The slope of each curve, that is, the change in diameter per unit of NW length (ΔD/ΔL) represents the “tapering parameter” of the nanowires.10,13,14 Tapering is significantly reduced in NW1 and 2 compared with NW0. There are two possible growth processes contributing to the radial growth and tapering: (I) adsorbed atoms directly on the nanowire sidewalls and (II) diffusion of adsorbed atoms on the substrate surface.24 Both processes are believed to be kinetic-limited growth.24,25 Since the growth temperature of NW1 is low, both growth processes will be reduced, leading to substantial reduction in radial growth and tapering.13 NW2, grown at high flow
rates, also shows less tapering than NW0. This is because the high flow rates markedly increase the mass-flow controlled axial growth rate,14 but only marginally increase the kinetically limited radial growth rate.14,24,26 Overall, NW1 shows minimum tapering in this study (NW1 < NW2 < NW0), indicating that lowtemperature growth (by two-temperature growth mode) is more effective than rapid growth at high temperature in reducing tapering. Table 1 summarizes all morphological and structural characteristics for NW0 2. A GaAs AlGaAs core shell structure as shown in Figure 5a was used for μ-PL and TR-PL measurements. Figure 5b d shows the overall morphology of the three types of core shell nanowires grown on Si(111) substrates coated with GaAs buffer layers (CS NW0 2). They all show a similar tapered shape where bottom part of the nanowires is very tapered because of 3112
dx.doi.org/10.1021/cg2003657 |Cryst. Growth Des. 2011, 11, 3109–3114
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Table 2. Summary of μ- and TR-PL Characteristics for NW0 2
Figure 6. Normalized (a) micro- and (b) time-resolved (TR) photoluminescence (PL) spectra of CS NW0 2. All PL measurements were carried out at low temperature (15 K).
the enhanced diffusion of adatoms from the substrates13 and cracking percentage of precursors on the sidewalls at higher shellgrowth temperature (650 C).24,27 Figure 5e is a TEM image showing single NW1 and CS NW1 in the same scale. NW1 has a diameter of about 50 nm without tapering (upper image). With NW1 as a core, radial growth of AlGaAs and GaAs shell was carried out to form CS NW1 with a uniform thickness of about 28 nm (bottom image). In figure 6a, we plot normalized μ-PL spectra from three types of core shell GaAs NW samples. The regular ripples in the PL spectra are mainly artifacts from the interference filter used to remove the 1.65 eV laser line. Broader structure in the PL may come from nonuniformity of Al composition in the AlGaAs shell owing to the change of Al incorporation rate with diameter.28,29 All PL peaks are near 1.518 eV ((0.006 eV) with similar, strong intensity (albeit normalized here), which is attributed to free exciton recombination as observed in bulk GaAs.30,31 In our previous work, Joyce et al. reported the lower energy peak between 1.48 and 1.50 eV in GaAs/AlGaAs NWs grown on GaAs substrate, which is attributed to donor acceptor pair (DAP) recombination involving a neutral donor and a carbon acceptor (D0, CAs).14 Interestingly, this DAP-related peak is absent in our GaAs/AlGaAs NWs grown on Si. Though the origin of this absence is not clear, it is certainly an advantage to grow GaAs NWs on Si for optoelectronic device applications. Figure 6b plots TR-PL spectra at the free exciton recombination energy for each core shell GaAs/AlGaAs NWs. Not surprisingly, we obtained similar carrier lifetimes in these nanowires compared with those grown on GaAs substrates.13,14 For example, CS NW0, grown with standard-core nanowires (NW0), shows a short lifetime of 80 ps due to crystal defects inside nanowires (SFs, twin defects). CS NW1, which was grown by the two-temperature mode, has the longest lifetime of 600 ps due to
core NW
growth
PL emission,
exciton lifetime
type
mode
eV (nm)
range (ps)
NW0 NW1
one-temperature growth two-temperature growth
1.516 (818) ∼1.521 (∼815)
