All-Printed, Self-Aligned Carbon Nanotube Thin-Film Transistors on

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Organic Electronic Devices

All-Printed, Self-Aligned Carbon Nanotube ThinFilm Transistors on Imprinted Plastic Substrates Donghoon Song, Fazel Zare Bidoky, Woo Jin Hyun, Steven Brett Walker, Jennifer A. Lewis, and C. Daniel Frisbie ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b01581 • Publication Date (Web): 23 Apr 2018 Downloaded from http://pubs.acs.org on April 24, 2018

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ACS Applied Materials & Interfaces

All-Printed, Self-Aligned Carbon Nanotube ThinFilm Transistors on Imprinted Plastic Substrates Donghoon Song,† Fazel Zare Bidoky,† Woo Jin Hyun,† S. Brett Walker,‡ Jennifer A. Lewis,‡ and C. Daniel Frisbie*,† †

Department of Chemical Engineering and Materials Science, University of Minnesota,

Minneapolis, MN 55455, USA ‡

John A. Paulson School of Engineering and Applied Sciences, Wyss Institute for Biologically

Inspired Engineering, Harvard University, Cambridge, MA 02318, USA

KEYWORDS: single-walled carbon nanotubes, BaTiO3-based dielectric, self-aligned printing, imprinted substrate, reservoirs/capillary channels, high-performance thin-film transistors

ABSTRACT: We present a self-aligned process for printing thin film transistors (TFTs) on plastic with singled walled carbon nanotube (SWCNT) networks as the channel material. The SCALE process (self-aligned capillarity assisted lithography for electronics) combines imprint lithography with inkjet printing. Specifically, inks are jetted into imprinted reservoirs, where they then flow into narrow device cavities due to capillarity. Here, we incorporate a composite high-k gate dielectric and an aligned conducting polymer gate electrode in the SCALE process to

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enable a smaller areal footprint than prior designs that yields low voltage SWCNT TFTs with average p-type carrier mobilities of 4 cm2/V·s and ON/OFF current ratios of 104. Our work demonstrates the promising potential of the SCALE process to fabricate SWCNT-based TFTs with favorable I–V characteristics on plastic substrates.


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INTRODUCTION

Thin film transistors (TFTs) are basic building blocks for flexible electronic systems. To date, most TFTs have been patterned using photolithography, a subtractive manufacturing method. While printing offers additive manufacturing,1-8 fully printed TFTs have been produced by gravure,9-13 inkjet,14-16 aerosol jet,17-19 and screen printing.20-22 In some cases, impressively small feature sizes (1–10 µm),23-24 electrode spacings (0.2–10 µm)23-24 and operating frequencies (~300 kHz)10 have been achieved for discrete devices. However, a central question remains regarding the scalability of these printing strategies for large area, high throughput manufacturing. From our perspective, simultaneously achieving high resolution printing and layer-to-layer registry is the most challenging impediment for printed electronics. It appears that a mechanism for self-alignment of metal, semiconductor, and insulator layers is needed, such that tedious and time-consuming machine-driven alignments are not required. We have been pursuing a self-aligning, scalable strategy that combines imprinting of plastic substrates with inkjet printing.25-28 In this process, which we term SCALE (self-aligned, capillarity-assisted lithography for electronics), a plastic web is first coated with a UV curable liquid. The liquid coating is imprinted with an elastomeric (polydimethylsiloxane, PDMS) stamp under simultaneous UV illumination to create a patterned solid film featuring multilevel device cavities, channels, and reservoirs. Electronic inks are delivered to these easy-to-hit reservoirs using an inkjet printer and capillarity spontaneously draws the ink out of the reservoirs and into the small device cavities. Multi-layered devices are built-up by sequential cycles of ink delivery to the appropriate reservoirs, followed by drying or sintering. To date, we have demonstrated side-gated TFTs, resistors, capacitors, interconnects, and cross-overs using the SCALE process.25-28


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Here, we take important additional steps in developing SCALE for self-aligned printing of TFTs. Specifically, we have improved our TFT design in three respects: (1) We have developed a top-gate TFT structure for the first time that employs only three ink reservoirs - one for the semiconductor, dielectric and gate inks, collectively, and two for the source and drain electrodes. Our previous side-gate design had five ink reservoirs which increased the device areal footprint.25-26 (2) We have employed a network of single walled carbon nanotubes (SWCNTs)29 in the channel, which gives higher charge mobility. (3) We have employed a composite high-k dielectric that enables low voltage operation. These three improvements allow us to operate the printed, self-aligned TFTs at a few kHz with only a 10 V supply voltage. Overall, our results highlight the good performance that can be achieved for all-printed TFTs, and they demonstrate the generality of the SCALE process for creating multilayered, self-aligned devices with complex geometries using a variety of electronic inks. Such flexibility will be necessary in ongoing work to build functional circuits using a roll-to-roll (continuous) version of SCALE.

RESULTS AND DISCUSSION

The imprinting process involving the PDMS stamp, adhesive, and flexible substrate is depicted in Figures 1a-c. First, a UV-curable liquid, NOA73, was coated on the O2-plasma cleaned polyimide substrate (~75 µm in thickness), and then the PDMS stamp was pressed into the liquid on top. By solidifying the liquid under UV irradiation (~1000 W/m2 for 20 min), the reservoirs and capillary channels were encoded in the cured NOA73 film. Delamination of the PDMS stamp was straightforward, as the NOA73 film was well-adhered to the polyimide substrate. The clean surface of the imprinted substrate is shown in Figures 1d,e, with the


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reservoirs and capillary channels appropriately located at three levels. We achieved high fidelity with the imprinting process, as further demonstrated by the clean edges (Figure S1) and the wellpreserved substrate profile (Figures 1f,g and Figure S2). The key constituents of each electronic ink for the SCALE TFTs are displayed in Figure 2. All inks were inkjet-printable and were annealed at low-temperatures (≤120 °C), compatible with the imprinted polyimide substrate and also with other common plastic substrates. In addition, the inks have a low viscosity (≤50–100 mPa·s) which is essential not only for efficient jetting, but also for the complete filling of reservoirs and capillary channels. Self-aligned printing steps for SCALE TFTs are described in Figure 3. Particle-free Ag inks can exhibit low viscosity and good capillary flow,30-31 and one such ink30 was used for the source and drain electrodes. First the Ag ink was delivered to the source and drain reservoirs (diameter and depth: 500 µm and 3.4 µm). Capillary flow drew the ink to the end of the electrode channels (width and depth: 5 µm and 3.4 µm), as depicted in Figures 3a,e,i. A flow distance of ~1.5 mm was obtained by virtue of the low ink viscosity (~10 mPa·s) and the low contact angle (~10°) of the ink with the cured NOA-73 (Figure S3). Annealing at ~100 °C for 5 min produced conductive Ag electrodes (thickness: ≈400 nm) with sheet resistances of 65 kΩ/□. To reduce the sheet resistance we found that a second delivery of ink to the reservoirs followed by annealing (a second pass) afforded much better sheet resistance 1.4 Ω/□. We employed the two pass approach. Figure 4a shows the granular morphology of the Ag film, after annealing. A high-purity commercial SWCNT ink comprising semiconducting-enriched tubes wrapped with polymers (blend ratio: ~1 tube/4 polymers), with the composition ratio of 0.1 mg tubes/1 ml toluene, was exploited to make the semiconducting TFT channel. The SWCNT ink was jetted into the semiconductor reservoir (diameter and depth: 500 µm and 3.4 µm), (Figures


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3b,f,j and Figure S4), and then dried. A portion of the polymer coating was removed by dipping the sample into toluene for 10 s. Finally, annealing at a reduced pressure (15) offer high-performance and stable device operation. For example, 5–10 µm thick BTO films ensure low voltage operation (≤10 V) and good encapsulation of the SWCNT film.20 The BTO ink, composed of 5 eV) metals35 would be a feasible route to suppress the slight ambipolarity. The representative transfer characteristics (ID–VG) of the p-type TFTs for VG ≤10 V are shown, measured at 2 V/s sweep rate


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at varying drain voltages (VD) (Figure 5a). Due to the good encapsulation by the thick BTO dielectric film, small gate leakage currents of

All-Printed, Self-Aligned Carbon Nanotube Thin-Film Transistors on

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