providing analyzed soybean and oyster samples. LITERATURE CITED (1) A. A. (2) A. (3) C. (4) T. (5)
(6)
(7) (8) (9)
(10)
T. Hubbard and F. C. Anson in “Electroanalytical Chemistry“, VoI. 4, J. Bard, Ed., Marcel Dekker, New York, N.Y., 1970, Chapter 2. T. Hubbard, Crit. Rev. Anal. Chem., 3, 201 (1973). N. Reilley, Rev. Pure Appl. Chem., 18, 137 (1968). Kuwana and W. R. Heineman, Acc. Chem. Res., 9 , 241 (1976). D. M. Oglesby, L. B. Anderson, B McDuifie,and C. N. Reilley, Anal. Chem.. 37, 1317 (1965). K. Stulik and M. Stulikova, Anal. Lett., 6 , 441 (1973). N. F. Zakharchuk, I. G. Yudelevich, and S.V. Cheonov, Zh. Anal. Khim. 30, 1201 (1975). T. P. DeAngelis and W. R. Heineman, Anal. Chem., 4 8 , 2262 (1976). D. T. Napp, D. C. Johnson, and S. Bruckenstein, Anal. Chem., 39,481 (1967). B. McDuffie, L. B. Anderson. and C. N. Reilley, Anal. Chem., 38, 883 (1966).
(11) J. Anderson and D. Tallman, Anal. Chem., 4 8 , 209 (1976). (12) “Metexchange Reagent M for I n Vitro Iliagnostic Use”, Environmental Science Associates, Inc., Burlington, Mass. (13) E. Barendrecht in “Electroanalytical Chemistry”, Vol. 11, A. J. Bard, Ed., Marcel Dekker, New York, N.Y., 1967. (14) T. R. Copeland, R. A. Osteryoung, and R. K. Skogerboe. Anal. Chem., 46, 2093 (1974). (15) G. D. Robbins and C. G. Enke, J . Electroanal. Chem., 23, 343 (1989). 116) R. Clem. unDublished results. (17) L. B. Anderson and C. N. Reilley, J. Electroanal. Chem., 10, 538 (1965). (18) M. A. Brooks, J. A. F. desilva, and M. R. Hackman, Am. Lab., Sept., 23 (1973). (19) R . E. Bond and W . R. Heineman, unpublished results.
RECEIVED for review April 12, 1977. Accepted July 13, 1977. The authors gratefully acknowledge financial support provided by National Science Foundation Grant CHE74-02641.
High Speed Synchronous Data Generation and Sampler System: Appiication to On-Line Fast Fourier Transform Faradaic Admittance Measurements R. J. Schwall, A. M. Bond,*’ R. J. Loyd, J. G. Larsen, and D. E. Smith” Department of Chemistry, North western University, Evanston, Illinois 6020 1
A synchronous data generation and sampler (SYDAGES) system constructed to assist broadband FFT electrochemical relaxation measurements Is described and evaluated. SYDAGES consists of a digital-to-analog converter, two analog-to-digital converters, three 1024-word shift register memories, and control circuitry. It functions as a programmable signal generator and two signal averaging data acqulsltlon channels which are Synchronized up to data rates of 500 kHz. SYDAGES Is run directly by a minicomputer without manual control. Its performance characteristics are demonstrated here using dummy cell and electrochemical cell admittance data. In the latter instance, good quality cell admittance data are obtained to 125 kHz, enabling dynamic nonfaradaic measurement and compensation to reveal the faradaic admittance up to 40 kHz.
Previous work in this laboratory (1-5) has demonstrated t h e benefits of on-line multiple frequency Fast Fourier Transform (FFT) faradaic admittance measurements using a particular applied pseudo-random waveform. The benefits include the ability to acquire kinetic and thermodynamic parameters with unprecedented speed and precision and to characterize reactions with very high rates. T h e particular waveform suggested has the following important properties. (a) It is periodic. (b) It contains a limited number of frequency components of approximately equal amplitude which are selected specifically to cover the frequency range of interest without being overly redundant. (c) All frequency components are odd harmonics of the lowest.
’
On leave f r o m Department of Inorganic Chemistry, U n i v e r s i t y of Melbourne. Parkville, V i c t o r i a 3052, Australia.
(d) The phases of the various frequency components are randomized as a function of frequency and measurement pass. (e) The signal is generated by a digital-to-analog converter (DAC) from a data array of 2” points ( n is an integer). (f‘) The applied waveform generation is synchronized to the analog-to-digital converter (ADC) operations which acquire the reference-working electrode potential and the cell current signals. In reported work the signal generation and sampling was controlled directly by a minicomputer, which could repeat a complete conversion cycle (two sampling and ADC steps, one DAC operation, and data storage) on a period no shorter than 100 p s . The effects of solution ohmic resistance (R,) and double-layer capacitance ( c d l ) were removed by analog techniques restricted to liquid-metal electrodes under strictly controlled conditions, including accurate potentiostat operation. One overall result of this strategy was an effective measurement bandpass limitation of a few kiloHertz. A far more general method of acquiring the faradaic admittance is the frequency domain analysis of the total cell admittance, as recommended originally by Sluyters ( 6 ) , but modified to include correlation of measured input and response waveforms as invoked by delevie (7) and Pilla (8). This approach has the advantage of providing, in the presence or absence of a faradaic component, rapid, dynamic measurement of R, and c d l which will detect changes in these variables with time. This can be very important in many situations, such as when monitoring reaction kinetics as a mercury electrode grows (9),or with solid electrodes, especially outside the clean laboratory environment. Of course, the acquisition of the nonfaradaic component magnitude enables convenient vectorial subtraction of these contributions from the total cell admittance to reveal the faradaic response. However, for many chemical systems this total cell admittance analysis requires that the data be acquired a t significantly higher frequencies than a 100-ps conversion cycle will allow. Another stimulus toward performing higher-frequency ANALYTICAL CHEMISTRY, VOL. 49, NO. 1 2 , OCTOBER 1977
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measurements is the possibility of monitoring still faster rate processes. Yet another is the prospect of acquiring information at high frequencies which complement data a t lower frequencies, thus providing confirmation checks on proposed mechanisms (10). In response to these stimuli we undertook the construction of a device capable of generating arbitrary signals from one 1024-word memory through a DAC, while synchronously sampling two signals via two ADCs and storing these points in two additional 1024-word memories with provision for time-domain signal averaging. No such device exists commercially, to our knowledge, nor can a reasonable compromise be realized using combinations of commercial data recorders for less than four times the cost (including construction time assessments) of the unit described here. Our approach provides a generalized transfer function measurement system with quite high frequency capabilities.
INSTRUMENTATION A block diagram of the synchronous data generation and sampling (SYDAGES) system is shown in Figure 1. The device has only four external connections: one output waveform generated through the DAC; two input signals sampled through the buffer amplifiers, sample-and-hold circuits and ADCs; and a 26-wire data bus to the computer. SYDAGES has no manual controls. By executing a single input/output instruction, the computer can effect any one of t h e following functions: ( A ) R e a d 1 word from memory A; ( B ) R e a d 1 word from memory B; ( C ) Load 1 word into memory G; (D)R e a d DELAY a n d PASS counter word; ( E ) R e a d STATUS word; (0Load PERIOD into clock; (G) Load DELAY a n d PASS comparator registers; (H)START data sequence; (0 ERASE entire A a n d B memories; (J)R e t u r n all memories to HOME position; ( K ) C L E A R interrupt; ( L ) DISABLE interrupt; (M) ENABLE interrupt. Commands A , B a n d C each result in all three memories being shifted one position. The memories are basically shift registers, are accessed only sequentially, and always shift together. T h e numbers p u t in the DELAY and PASS comparators (1 to 255) are used to control the number of waveform cycles to be used when START is executed. One “cycle” is a memory cycle of 1024 words (one waveform period) with the period between individual words being defined by the word in the CLOCK register. During DELAY cycles the output signal is generated through the DAC, but the A and B memories are shifted unchanged. This is to allow startup transients to become negligible, validating the steady-state approximation ( 1 1 ) and improving the accuracy of the FFT algorithm (12). During PASS cycles, output signal generation continues, but converted data from the signal inputs are added into the A and B memories, in the fashion of a digital signal averager. Commands D and E allow the computer to monitor the progress of SYDAGES through its automatic operations, which are initiated by commands H , I , and J. The done flag is a bit in the STATUS word (read by command E ) which goes on when a n automatic sequence is completed. If command M has been given, every appearance of the done flag causes a n interrupt in the computer. This feature allows the computer to execute other programs while SYDAGES is executing an automatic sequence. A rather typical command sequence program used in running SYDAGES follows (upper case letters designate 1798
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commands in the foregoing list): K a n d L; J, t o send memories t o H O M E position; E repeatedly until DONE flag appears, t h e n K ; I t o erase, M a n d adjust computer’s interrupt software t o go to s t e p 6 when interrupted; Proceed with program; Execute C 1024 times, transferring o u t p u t waveform from computer to SYDAGES G memory; F to p u t shift period into CLOCK register; G to fill DELAY a n d PASS comparators; H , K , M t o start, adjust interrupt software t o point t o s t e p 11; Proceed with program; L and K t o free computer’s interrupt hardware; Execute A 1024 times to read all of A memory into computer memory; Execute B 1024 times t o read all of B memory into computer; Go t o s t e p 4. “Proceed with program” may include such tasks as generating new time domain waveforms, and transferring sampled waveforms t o bulk storage (e.g., disc). T h e STAR BOX mentioned in Figure 1 is a general input-output interface adaptor for the Raytheon computers. I t was designed and built locally by Drake and Schwa11 (13). MASTER CONTROL is the part of SYDAGES that interprets the computer’s commands, controls the interface gates, and monitors the status of the major control lines. It also generates the single CONVERT pulse each time a command A , B , or C is executed. T h e INTERFACE operates under the command of the signals on the interface control cable to gate data between the computer and the various elements of SYDAGES only when the appropriate computer command is executed. T h e CLOCK is a 10-MHz crystal oscillator with programmable frequency division controlled by the clock register. Available clock periods are of the form A x loB seconds, where A is 1, 2, or 5 and B is an integer from -6 to 0. A and B are entered into the clock register in coded form. Under control of RATE signal from MASTER CONTROL, the CLOCK will run a t a 500-kHz rate independent of the clock register. This is used for commands I and J. The CONVERT signal is exerted once for each pulse during any automatic operation and once on any A, R or C command. The ADCs then immediately begin conversion. While they are converting, they hold EOC (end of conversion) signals false, thus locking the sample-and-hold modules in the hold state. When the conversion is complete, both EOC signals become true and the SYNC module shifts the memories. The memories always are shifted together and the SHIFT COUNTER keeps count of the shifts and exerts the H O M E signal once in 1024 shifts. T h e memories are built from 1024 X 1-bit CMOS shift registers and 4-bit adders. A and B memories are 16-bits wide. On each shift they will add the input data word to the word currently at the output port, or they will force zeros into the current word, depending on the state of the ERASE signal. The G-memory is 10-bits wide and either will simply circulate data past the output port, or will force in data from the input port, depending on the state of the LOAD signal. The buffers are unity gain subtractor circuits built from DATEL Model 100 operational amplifiers. The sampleand-hold units are DATEL Model SHM-2. The ADCs are DATEL Model ADC-GlOB4C 10-bit types with extra gating circuitry to force zeros onto the output if the GATE signal is not true. The DAC is a 10-bit DATEL Model DACVlOBBD. All other circuitry is home-built from the T T L integrated circuits. All circuitry is mounted on twenty-one
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Flgure 1. Block diagram of the SYDAGES device. Numbers in parentheses above double-lines are numbers of bits in multibit signals ANALYTICAL CHEMISTRY, VOL. 49, NO. 12, OCTOBER 1977
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