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ALD Alumina Passivated Silicon Nanowires: Probing the Transition from Electrochemical Double Layer Capacitor to Electrolytic Capacitors Dorian Gaboriau, Maxime Boniface, Anthony Valero, Dmitry Aldakov, Thierry Brousse, Pascal Gentile, and Said Sadki ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b01574 • Publication Date (Web): 23 Mar 2017 Downloaded from http://pubs.acs.org on March 26, 2017

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ACS Applied Materials & Interfaces

ALD Alumina Passivated Silicon Nanowires: Probing the Transition from Electrochemical Double Layer Capacitor to Electrolytic Capacitors Dorian Gaboriau,a,b Maxime Boniface,b Anthony Valeroa,b Dmitry Aldakov,a Thierry Brousse,c, d Pascal Gentile,b Said Sadkia* a Univ. Grenoble Alpes, CEA INAC-SyMMES, F-38000 Grenoble, France b Univ. Grenoble Alpes, CEA INAC-PHELIQS, F-38000 Grenoble, France c Institut des Matériaux Jean Rouxel, Université de Nantes – CNRS, 2 rue de la Houssinière, 44322 Nantes Cedex 3, France d Réseau sur le Stockage Electrochimique de l’Energie (RS2E), FR CNRS 3459, 80039 Amiens Cedex, France * Corresponding author e-mail: [email protected] KEYWORDS : Chemical Vapor Deposition, Supercapacitors, Atomic Layer Deposition, Silicon Nanowires, EMI-TFSI electrolyte, XPS, TEM

ABSTRACT: Silicon nanowires were coated by a 1-5 nm thin alumina layer by Atomic Layer Deposition in order to replace poorly reproducible and unstable native silicon oxide by a highly conformal passivating alumina layer. The surface coating enabled probing the behavior of

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symmetric devices using such electrodes in EMI-TFSI electrolyte, allowing to attain a large cell voltage up to 6 V in ionic liquid, together with very high cyclability with less than 4% capacitance fade after 106 charge/discharge cycles. These results yielded fruitful insights on the transition between an electrochemical double-layer capacitor behavior and an electrolytic capacitor behavior. Ultimately, thin ALD dielectric coatings can be used to obtain hybrid devices exhibiting the large cell voltage and excellent cycle life of dielectric capacitors, while retaining energy and power densities close to the ones displayed by supercapacitors.

Introduction Improving energy storage devices is one of the key challenges of the last decades. In the field of micro power sources, supercapacitors combine long term cyclability, high power and fair energy densities with an often superior microfabrication compatibility compared to conventional batteries.1-3 In particular, Electrochemical Double Layer Capacitors (EDLCs) can experience millions of charge/discharge cycles without significant damage due to their purely electrostatic charge storage mechanism. Among numerous EDLCs electrode materials, carbon4 is the most studied, with abundant results in the literature using graphene,5-10 activated carbon,2, 11-13 onionlike carbon2, 14 and others. However, some incompatibilities remain for its small scale integration such as resistance at high temperature and the need for a silicon substrate to ensure compatibility with most microfabrication steps. For carbon-based EDLCs the role of silicon is limited to the passive substrate, whereas it could be advantageously used as an electrochemically active material. Silicon is undeniably the material of choice for most microtechnology devices, with a wide array of possible micro and nanostructure morphologies; it is inherently “on-chip integrable”, moreover its electrochemical


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characteristics can be tailored to match carbon. Silicon based nanomaterials have recently attracted substantial attention in the field of supercapacitor owing to their capacitive properties,15 large voltage window16 and exceptional cyclability.17 Silicon can be synthesized in different morphologies, such as bottom-up nanowires (Si-NWs)18, 19 and nanotrees (Si-NTrs),17 top-down metal assisted etched Si-NWs,20 porous silicon…21, 22 Several studies have been published about surface modification of silicon EDLC electrodes, for instance using carbon,23-25 silicon carbide26 or conducting polymers.27 Enlarging the cell voltage of EDCL device28 is of crucial importance since energy and power densities vary with the square of maximum cell voltage (Umax), and certain applications could require high voltage (i.e. higher than 3-4 V) in order to be properly operated. The latter issue is often overlooked and addressed by adding multiple supercapacitive cells in series, which adds complexity and cost and drastically reduces the effective capacitance per unit of volume of the device. Maximum cell voltage is primarily governed by the electrolyte chemistry and more precisely by oxidative and reductive potential limits which lead to Umax ranging from 0.7-1.2 V for water based electrolytes, 2-3 V for organic solvent and finally, 3-4 V for ionic liquid.4 Silicon is usually covered by a native oxide layer with a thickness of 1-2 nm.29 The formation of this native layer occurs within a few tens of minutes upon exposure of silicon to ambient air and moisture, yielding a conformal yet loosely resistive and passivating layer largely varying depending on ambient conditions. This layer has already been extensively studied and resulted in a large number of misconceptions and experimental conundrums that hindered the use of bare silicon as electrode material in electrochemical devices. Moreover, the maximum cell voltage of silicon materials is highly dependent on this surface layer. It was shown that silicon EDLCs can withstand a cell voltage up to 3.5-4 V in ionic liquids, 16 but the role of the native oxide layer


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remains mysterious especially for silicon nanostructures. For instance, several reduction and oxidation reactions can occur during the first galvanostatic or cyclic voltammetry cycles of SiNWs samples, and few tens of cycles are necessary to stabilize the electrochemical response of the system.16 This issue has been scarcely addressed due to the low reproducibility, extreme reactivity of the electrode surface and lack of understanding of the phenomena at stake, although some possible explanations are envisioned such as native oxide modification or ionic liquid impurities degradation (i.e. traces of water, oxygen, halides…). This issue can be addressed by replacing the unstable and poorly reproducible native oxide with a highly conformal protecting layer such as Al2O3 deposited by Atomic Layer Deposition (ALD). ALD is a well-known deposition method using sequential self-limiting surface reactions to deposit inorganic material layers.30, 31 This method possesses the ability to result in deposition of extremely conformal, pinhole-free materials on high aspect ratio structures,32 while retaining an excellent thickness control at the atomic level. Initially used in the semiconductor industry to deposit electronic insulators or passivation layers, ALD recently attracted a considerable attention for a wide range of applications, where its unique conformability and thickness control can be used pertinently. Recent reviews highlighted its new promising applications in catalysis, nanomaterial surface functionalization and energy storage devices.33-35 The latter was notably explored for lithium-ion batteries since the seminal works of Jung et al.36-38 generating tremendous developments in the last five years.39, 40 Several inorganic materials (Al2O3, TiO2, ZnO, TiN…) were studied and ultrathin (0.5-10 nm) Al2O3 layers proved to efficiently protect positive and negative electrodes (including silicon micro- and nanostructures)41-45, and prevent rapid electrolyte degradation.46


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In the field of supercapacitors, only a few proof of concept studies have been published dealing with the use of ALD for improving supercapacitor devices. For example, a thin TiN ALD coating has been deposited on porous silicon,47 allowing stability and capacitance enhancements. Another notable example is the use by Hong et al.48 of a thin Al2O3 layer to encapsulate activated carbon particles, permitting a cell voltage enhancement to 3 V in organic electrolyte and a significant gain in electrolyte stability. Few studies also dealt with the use of ALD Al2O3 as a sacrificial template.49 However, to the best of our knowledge, no study focused on the surface passivation of silicon nanostructures for EDLC and capacitors application using ALD. The present study investigates an innovative way for enhancing the cell voltage of silicon based capacitors by fine tuning of the electrode/electrolyte interface through thin Al2O3 film deposition using Atomic Layer Deposition (ALD). Both nanostructured and flat highly doped silicon samples were coated with thin layers of alumina in order to replace the uncontrolled native oxide layer with a controlled highly stable passivating layer. These synthesized electrodes were then electrochemically characterized using EMI-TFSI ionic liquid as the electrolyte. The addition of a thin pin-hole free dielectric layer on the surface allowed obtaining devices combining EDLCs and electrolytic capacitors features, with large cell voltages of 5.5-6 V and extended cyclability owing to the excellent surface passivation provided by conformal ALD Al2O3 coatings. Materials and methods Sample preparation Highly n doped silicon wafers (100 mm diameter, orientation, As doping) from Silicon Materials Inc. were diced into 10x10 mm² square samples, and used for bulk and Si-NWs studies


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after extensive rinsing in acetone, isopropanol and piranha solution (H2SO4 96 % + H2O2 30 % 3:1). Prior to any surface modification, native oxide was removed by immersing the samples in hydrofluoric acid 10 % for 1 minute, followed by copious water rinsing and nitrogen drying. Silicon nanowires synthesis Silicon nanowires were grown by Chemical Vapor Deposition using the Vapor Liquid Solid method (VLS). Gold was used as the VLS catalyst and was deposited by electroless plating,50 achieved by drop casting an aqueous solution containing 2 mM AuCl4-, 0.1 M HCl and 2.5 M HF for 15 s on the sample, followed immediately by water rinsing and nitrogen blowing. This yielded a partially covering gold layer, whose surface density was roughly estimated at 7 µg.cm-2 by careful weighting of multiple samples. Consecutively, the nanostructure growth was conducted in a hot wall quartz tube CVD reactor, at 650 °C and under 6 Torr total pressure, using 700 sccm (standard cubic centimeter per minute) H2, 40 sccm SiH4 and 90 sccm PH3 (0.2 % PH3 in H2) respectively as carrier, precursor and doping gases. 100 sccm HCl gas was added during the growth in order to reduce surface gold migration and enhance the morphologies of the SiNWs as previously reported.51 The growth rate under these conditions is about 2.5 µm.min-1 and the fabricated Si-NWs were chosen to be 50 µm long. Si-NWs morphologies were studied by Scanning Electron Microscopy (Zeiss Ultra 55) with 10 kV accelerating tension, and the SEM micrographs were subsequently analyzed using ImageJ (Rasband, W.S., ImageJ, U. S. National Institutes of Health, Bethesda, Maryland, USA, http://imagej.nih.gov/ij/, 1997-2014). The mean Si-NW diameter was estimated at 61 nm ± 26 nm from more than 300 single SEM measurement using top view micrographs on several representative zones. Si-NWs density was roughly estimated to be 7.107 Si-NWs.cm-2, from top


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view SEM micrographs using the “Find Maxima” function of ImageJ with a careful choice of the noise tolerance to pick Si-NWs tips only. ALD deposition method Atomic Layer Deposition of Al2O3 thin films were carried using trimethylaluminum (TMA) and H2O as precursors in a Fiji200 reactor (Cambridge Nanotech). The deoxidized samples were placed in the deposition chamber under 250 °C, 10-2 Torr, argon purge gas and an automated recipe alternating 4 steps (0.06 s TMA, 8 s purge, 0.06 s H2O and 8 s purge) was performed until the desired amount of cycles was attained. The deposition rate was estimated to be roughly around 0.9 Å.cycle-1, thus 1, 2, 3 and 5 nm thick layers were obtained using respectively 11, 22, 33 and 54 ALD cycles. Silicon nanowires samples will be referred as Si-NWs / 1, 2, 3 and 5 nm Al2O3 for Si-NWs covered by 1, 2, 3 and 5 nm Al2O3 respectively. XPS measurements X-ray Photoelectron Spectroscopy (XPS) analyses were carried out with a Versa Probe II spectrometer (ULVAC-PHI) equipped with a monochromated Al Kα source (hν = 1486.6 eV). The core level peaks were recorded with constant pass energy of 23.3 eV. The XPS spectra were fitted with CasaXPS 2.3.15 software using Shirley background and a combination of Gaussian (70%) and Lorentzian (30%) distributions. Binding energies are referenced with respect to the adventitious carbon (C 1s BE = 284.6 eV). TEM characterization High resolution scanning-TEM (HRSTEM) and Energy Dispersive X-ray spectroscopy (EDX) measurements were performed in a probe corrected Titan Themis transmission electron


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microscope operated at 200kV and equipped with 4 superX EDX detectors. Samples were prepared by drop-casting an extremely dilute dispersion of nanowires scratched from their substrate in ethanol onto lacey carbon-coated copper mesh grids. HRSTEM measurements were then performed with a High Angle Annular Dark Field detector (HAADF), a convergence semiangle of 18 mrad and 60 pA of beam current. The later was increased to 300 pA for EDX measurements in order to improve the signal on noise ratio (SNR) for hypermaps acquisition. Electrochemical characterizations All electrochemical characterizations were performed in an argon filled glove box (H2O and O2 contents measured: ≤ 1 ppm and ≤ 2 ppm respectively) at room temperature using EMI-TFSI (1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide) ionic liquid as the electrolyte, purchased from Solvionic (France) with 99.5 % purity (≤ 0.05 % water and ≤ 0.001 % of halide content) and used without further purification. The ionic liquid wets extremely well the nanostructured silicon electrodes, with no measurable contact angle of an ionic liquid droplet with the surface. All electrochemical characterizations were performed several times with samples from separate CVD and ALD batches using the same conditions, displaying a good reproducibility. Three electrodes cell characterization were conducted using a homemade Teflon cell connected to an Autolab PGSTAT302 potentiostat/galvanostat equipped with FRA 2 module, using the silicon sample (active area 0.4 cm²) as the working electrode, a twisted platinum wire as the counter electrode and an Ag/Ag+ reference electrode (10 mM silver trifluoromethanesulfonate in EMI-TFSI). Cyclic voltammetry at different scan rates (between 50 mV.s-1 and 10 V.s-1) and with various maximum cell voltages (ranging from 0.7 V to 6.2 V) were


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conducted. Electrochemical Impedance Spectroscopy (EIS) was also measured using 10 mV amplitude signals at frequencies ranging from 10 mHz to 100 kHz. Two electrodes cell devices were assembled by sandwiching an EMI-TFSI soaked Whatman n° 41 paper separator between two symmetric silicon samples connected to a potentiostat/galvanostat (VM3, Bio-logic, France). Cyclic voltammetry (scan rate: 50 mV.s-1 – 200 V.s-1, cell voltage: 4 – 6.5 V), galvanostatic charge/discharge cycles (current density: 50 µA.cm-2 – 20 mA.cm-2, cell voltage: 4 – 6.5 V) - and electrochemical impedance spectroscopy (signal amplitude: 50 mV, frequency: 10 mHz – 400 kHz) were performed. Equivalent Series Resistance (ESR) was estimated from the real part of the impedance at maximum frequency in EIS measurements. Areal capacitance values were derived either from the capacitive current measured in the center point of the cell potential window in cyclic voltammetry curves, or from the slope of the galvanostatic measurements. Energy and power densities were calculated from galvanostatic charge/discharge curves. Results and discussion Figure 1 a) and d) exhibit SEM micrographs of the as grown Si-NWs samples, showing a dense forest of highly conductive, 50 µm-long silicon nanowires grown on a silicon wafer substrate. The samples were subsequently coated with Al2O3 by ALD immediately after native oxide removal and studied by X-ray photoelectron spectroscopy (XPS). Figure 1 b) displays the high resolution XPS spectra of pristine and alumina coated Si-NWs samples in the Al 2p and Si 2p regions. With increasing alumina thickness one can observe the appearance and gradual increase of a peak at 76 eV corresponding to the aluminum from Al2O3 accompanied by the decrease of the silicon signal intensity at 99-100 eV. The average probing depth of XPS is about 2-3 nm, and


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the disappearance of the Si signal for Si-NW / 5 nm Al2O3 confirms a good coverage of the nanowires by the alumina layer. The same XPS spectra recorded for Al2O3 coated non-nanostructured silicon samples (Figure S1) displayed very similar signals, which is consistent with previous studies.52 This can be interpreted as a marker of good conformity of the ALD-deposited layer, with no discernable differences in the alumina coating between flat and nanostructured samples. A small peak around 101 eV visible for 1 nm Al2O3 coated samples can be ascribed to SiOx species due to incomplete surface coverage of the alumina, which is expected since the growth mechanism of ALD Al2O3 on H-terminated silicon is usually “island type” during the first 10 ALD cycles (~1 nm), then 2D pin-hole free afterwards.31, 53 No peak corresponding to SiOx species could be identified for thicker Al2O3 layers, proving that the ALD coating effectively prevents silicon oxide reformation, and that no substantial silicon oxidation occurs upon alumina deposition. High resolution STEM HAADF micrographs were recorded for Si-NWs with 1, 3 and 5 nm thick Al2O3 layers. The extremely thin 1 nm coating was hardly discernable in STEM, however a highly conformal coating with a uniform thickness throughout the full length of single nanowires was observed for 3 and 5 nm thick Al2O3 coated Si-NWs. Figure 1 e) exhibits a representative sample consisting of a single nanowire coated with 3 nm Al2O3. The images were recorded at the tip (End 1), the center and the other extremity of the Si-NW, where it was scratched out of the substrate (End 2). A regular, 3 nm thick amorphous coating is clearly visible at the edges of the crystalline Si-NW and is composed of aluminum oxide as suggested by EDX elemental mapping. The central section mapping is shown in Figure 1 c) to exemplify this result. It is worth noting that EDX revealed the 1-2 nm amorphous layer visible at End 2 in Figure 1 e), consisting of


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native silicon oxide formed in ambient air after scratching the nanowire out of the substrate (see Figure S2 for elemental mapping and profiles of both ends of the Si-NW). Linear composition profiles were plotted along the section of the different Si-NW / Al2O3 samples, and confirmed the high conformity of Al2O3 layers, as shown in the profile in Figure 1 f) corresponding to the EDX signal integrated over the dashed line area highlighted in Figure 1 c). Interestingly, the oxygen signal closely follows the aluminum signal, indicating the absence of any distinguishable silicon oxide layer under the Al2O3 layer, implying that the ALD Al2O3 process performed quickly after silicon deoxidization effectively replaced the native oxide and prevented any silicon re-oxidation upon exposure to ambient air and moisture. The replacement of native oxide by a highly conformal Al2O3 layer on high aspect ratio nanostructures and the following surface passivation proves extremely promising for electrochemical applications. Single Al2O3 coated silicon electrodes were studied in a three electrode cell configuration and displayed outstanding operational voltage window enhancements. As previously reported, the best pristine silicon materials are able to withstand a maximum cell voltage of 3.5-4 V16 at maximum in ionic liquids. For Al2O3 coated Si-NWs, the maximum cell voltage has been enlarged to 6 V in EMI-TFSI as depicted in Figure 2 a) for Si-NWs / 5 nm Al2O3, which is an unprecedented value for any electrode material used in supercapacitor devices. The maximum cell voltage becomes wider with increasing Al2O3 thicknesses with 4, 4.3, 4.6, 5.1 and 6 V for pristine (0 nm), 1, 2, 3 and 5 nm Al2O3 coated Si-NWs samples, respectively. Strikingly a cell voltage up to 6V (between -3.5 and 2.5 V vs. Ag/Ag+) can be performed without damaging the electrode material in the EMI-TFSI electrolyte54, which may be attributed to reduction and oxidation kinetic hindrance achieved by the Al2O3 passivating layer.


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It should be noted that this exceptional result is accompanied by a reduction of the areal capacitance of the device. This decrease can be explained by the added dielectric capacitance of the Al2O3 layer in series with the electrochemical double layer capacitance of the silicon based electrode. This is clearly visible in Figure 2 b), where the cyclic voltammetry curves of all samples are compared at 1 V.s-1. While Si-NWs / 1 nm Al2O3 samples are fairly comparable to pristine Si-NWs, 2, 3 and 5 nm Al2O3 layers reduce the areal capacitance by 25, 35 and 70%, respectively. The effect of this significant reduction of the capacitance is alleviated by power and energy density considerations stating that these parameters are proportional to the square of the cell voltage. In order to assess the full capacitor device behavior, two electrode cell symmetric devices were assembled and tested. The Bode diagrams of the Si-NWs samples before cycling are depicted in Figure 2 d) and e). These supercapacitor/dielectric capacitor cells showed quasi-ideal capacitive behavior with phase angles close to -90 ° at frequencies up to several tens of Hertz, revealing extremely short characteristic times of 4 to 7 ms (- 45° phase angle frequency between 150 and 250 Hz). Similar to the single electrode measurements, a decrease of the device capacitance from 63 to 30 µF.cm-2 with increased Al2O3 thickness from 0 to 5 nm, respectively, was observed. A simplified model for this behavior can be studied by using a Helmholtzian definition of the electrochemical double layer capacitance:

∝

where the capacitance Csurf is proportional to the relative dielectric constant of the double layer, the specific surface area S, and the inverse of the effective thickness of the double layer . Assuming that the double layer thickness within the electrolyte remains unchanged by


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adding a thin native oxide or Al2O3 layer of thickness and dielectric constant , the insulating layer adds a contribution to the double layer capacitance as follows: 1

∝

. . +

Thus the inverse of the areal capacitance should depend linearly on the Al2O3 thickness. The measurements performed both with single electrode and symmetric supercapacitive devices with flat and nanostructured electrodes are in good agreement with this model as shown in Figure 2 c), where the inverse of the areal capacitance of the devices (measured at 1 Hz) is plotted for various Al2O3 thicknesses. Adding the capacitance of reference sample made of pristine Si-NWs on that same plot reveals that the contribution of the native oxide to the reduction of the capacitance is roughly equivalent to an Al2O3 thickness comprised between 1 and 2 nm. From the slope of the inverse of the capacitance with the alumina thickness measured on flat silicon (see Supporting Information), one can evaluate the relative dielectric constant of the ALD alumina to 7.3, which is remarkably close to the value reported in the literature (between 7 and 9)30. If this constant remains the same for Si-NWs, one can calculate from the slope of the model in Figure 2 c) the surface enhancement allowed by the nanostructuration, which is in this case a factor of 65. Detailed calculation (see Supporting Informations) allow to determine that the double layer term of the previous equation remains predominant for alumina thicknesses lower than respectively 3.6 and 2.1 nm for flat and Si-NWs samples, while native oxide covered samples’ capacitances are predominantly due to double layer capacitance. Thus the range of alumina thicknesses studied here permits a fine study of the transition from a quasi-purely EDLC behavior to a mixed double layer/dielectric capacitor behavior, different than purely dielectric capacitors, where the dielectric layer is often thicker than 10 nm.


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The devices were then subjected to 1 million galvanostatic charge/discharge cycles at a current density of 1 mA.cm-2 and 4 V cell voltage. As shown in Figure 2 f), the cyclability was found to be greatly enhanced by the addition of the alumina passivation layer, with capacitance fade values being decreased from 20-23 % for pristine electrodes and 1 nm Al2O3 coated electrodes, down to 12, 3.4 and 3.1 % for 2, 3 and 5 nm Al2O3 coated Si-NWs, respectively. The absence of any substantial damage for 3 and 5 nm coated Al2O3 proves that the extremely beneficial surface passivation provided by the alumina layer allows to drastically increase the cycle life of the devices. Although Si-NWs coated with 1 nm Al2O3 and pristine Si-NWs samples exhibit higher capacitances before cycling, this fact is mitigated by a quick capacitance fade for these samples, thus reducing their capacitances after 1 million cycles. The difference between the capacitance of Si-NWs / 5 nm Al2O3 and pristine Si-NWs decreased from 58 % to 48 % respectively before and after 1 million cycles. This drastic stability improvement originates from the replacement of the poorly controlled native silicon oxide layer by a pin-hole free, conformal alumina layer on the silicon surface. While the exact mechanism of the capacitance fade for supercapacitive silicon electrodes remains unresolved, the alumina layer seems to effectively prevent electrode and/or electrolyte degradation upon cycling, possibly by reducing the kinetics of irreversible reactions, such as electrolyte impurities degradation or surface defect reactions with the electrolyte. The hindrance to electron transfer between the conducting electrode and the electrolyte also adds overpotentials to reduction and oxidation reactions, yielding an enlarged electrochemical window 16. Comprehensive in situ studies or computational analysis could allow for a better understanding of the phenomena at stake at this interface.


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Table 1 summarizes the electrochemical characteristics of the different supercapacitor devices studied. Maximum power densities (and thus cell voltage) increase with alumina thickness, reaching more than 300 mW.cm-2, although equivalent series resistances slightly increase upon enhancing the coating thickness. More interestingly, alumina coated Si-NWs display higher energy densities after cycling than pristine Si-NWs, with up to 0.56 J.cm-2 for Si-NWs / 3 nm Al2O3 with a cell voltage of 5.5 V, representing a 40 % improvement compared to pristine SiNWs with a cell voltage of 4 V. These figures support the fact that the capacitance fade due to the added dielectric layer is not harming the good capacitive properties of the Si-NWs in terms of energy and power densities. While the energy density remains average compared to some silicon supercapacitors, the power densities of the Si-NWs / 3 nm Al2O3 based supercapacitors surpass most literature results (see supporting information). Moreover, the extremely high maximum operating voltage and outstanding electrochemical stability of alumina coated Si-NWs remain unchallenged, even for carbon based EDLCs, while the capacitance values still can be dramatically improved by using more advanced silicon nanostructures (such as silicon nanotrees)55 potentially increasing the energy density considerably due to the increased specific surface. When considering the parameters altogether, Si-NWs / 3 nm Al2O3 appear to be the most promising compromise between the enhancement of the maximum cell voltage and capacity, while showing a very limited capacitance fade during galvanostatic cycling. The devices were then subjected to cycling at cell potentials above 4 V for 100 000 charge/discharge cycles for each cell voltage. Figures 3 a) and c) exhibit respectively the capacitance fade and Coulombic efficiency evolution upon cycling of pristine Si-NWs and of SiNWs / 3 nm Al2O3 at high cell voltages. Pristine Si-NWs experienced sharper capacitance fade at


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higher voltage, which can be related to the accelerated ageing of the cell at high potentials because of the decrease of the Coulombic efficiency. On the other hand, Si-NWs / 3 nm Al2O3 do not show any capacitance fade and keep an excellent Coulombic efficiency over 99.6 %, even upon cycling at 5.5 V. These outstanding capacitive properties of the alumina-coated Si-NWs are clearly displayed in Figure 3 b), where the galvanostatic charge/discharge profiles at 1 mA.cm-2 are nearly ideal at 5.1 V, and show negligible degradation when the cell potential is increased to 5.5 V (dashed red line). Surprisingly, cycling the devices at very high potentials even improved the cyclic voltammetry response without damaging the cells as displayed in Figure 3 d). The cyclic voltammetry curves of Si-NWs / 3 nm Al2O3 exhibit a small deviation from the ideal capacitive behavior with a slight oxidative current peak observed at 4.5 V, which however is progressively reduced after cycling at 5 V (purple line) and 5.5 V (red line) probably due to the consumption of any remaining surface defects or ionic liquid impurities, which could be at the origin of this oxidation peak. Apart from this peak, no changes can be observed when comparing cyclic voltammetry curves before and after 8 x 100 000 cycles at cell voltages varying from 4.2 to 5.5 V, proving the robustness of the double layer/dielectric hybrid capacitor based on alumina coated Si-NWs. This improvement of the cyclic voltammetry response upon cycling at cell voltage exceeding 4 V is taken into account in Table 1, where the maximum cell voltages recorded without any significant cell damage are displayed in bold. One can conclude that potential window for full capacitor devices closely follow the trend already observed for three electrode cells, with values up to 5.1-5.5 V for Si-NWs / 3 nm Al2O3 and 5.5-6 V for Si-NWs / 5 nm Al2O3. Conclusions


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Bottom-up highly doped silicon nanowires were coated by thin Al2O3 films by ALD and used as electrodes for symmetric capacitor devices. The alumina layer was found to be highly conformal and efficiently covered native oxide on silicon nanowires, yielding a pertinent passivation of the surface. Single electrodes showed unprecedented values of cell voltage for EDLCs as high as 6 V in EMI-TFSI ionic liquid, and symmetric devices reached outstanding cycle lives and cell voltages while maintaining the power and energy densities of pristine Si-NWs. In particular, SiNWs coated with 3 nm Al2O3 were cycled up to 5.5 V cell voltage without significant damage (capacitance fade < 5 %) and displayed ideal capacitive behavior with maximum power and energy densities reaching respectively 376 mW.cm-2 and 0.56 J.cm-2. These results prove the interest to probe the transition between an EDLC and a dielectric capacitor device, where the advantages of both systems can be used. Further developments of ALD Al2O3 surface coatings on very-high surface area silicon materials, such as silicon nanotrees or porous Si-NWs should allow accessing high voltages and large capacitance devices. This promising result paves the way to high voltage, on-chip integrated hybrid EDLC/dielectric capacitors for future micro high power sources. Acknowledgements The authors would like to thank the French Agence Nationale de la Recherche funding the ISICAP project (ANR-12-BS09-0032), the Direction Générale de l’Armement and the CEA for financial support.


17


FIGURES

a)

b)

c)

7000

Si 2p

Al 2p

6000 XPS intensity (A.U.)

Al2O3 thickness:

5000

Pristine

4000

1 nm

3000

3 nm

1000

5 nm

0 105

d)

O

2 nm

2000

10 µm

10 nm

Al

100 75 Binding energy (eV)

70

e)

f) End 1

Si-Kα

20 µm 3 nm 3 nm 3 nm Center 3 nm3 nm End 2

EDX intensity (A.U.)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 18 of 31

Al-Kα O-Kα

10 nm 0

10

20 30 40 Distance (nm)

50

Figure 1. a) and d) SEM micrographs of Si-NWs samples: 45° top view and 90° cross-sectional view, respectively; b) XPS analysis of the Si-NWs samples with Al2O3 of various thicknesses; c) STEM HAADF EDX elemental mapping of a 50 nm diameter Si-NW coated with 3 nm Al2O3, displaying Al-Kα (red), O-Kα (blue), Si-Kα (yellow) signals and a composite view of the mapping; e) STEM micrographs displaying different regions of a single 50 nm diameter Si-NW coated with 3 nm Al2O3; f) EDX elemental profiles along the direction indicated in c).


18

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Figure 2. Si-NWs electrochemical characterization: a) Three electrode cell cyclic voltammetry curves of Si-NWs / 5 nm Al2O3 with a potential window varying between 4 to 6 V (with a final electrochemical window between -3.5 and 2.5 V vs. Ag/Ag+) ; b) Cyclic voltammetry curves of samples with pristine Si-NWs (black) and Si-NWs covered by 1, 2, 3 and 5 nm Al2O3 (red, yellow, green and blue lines, respectively) in three electrode cell configuration; c) Inversed two electrode symmetric device capacitance plotted versus Al2O3 thickness for Si-NWs samples; d) and e): Bode diagrams extracted from EIS measurements of the two electrodes devices; f) Capacitance retention upon charge/discharge cycling at 1 mA.cm-2 with a 4 V potential window.


19


b)

50

6

4.5 V

4.4 V

4.3 V

4.1 V

Pristine Si-NWs 60

4.2 V

70

5 Cell voltage (V)

a)

6

10 cycles; Umax = 4 V

20 0.0

5.0x105

1.0x106

5.5 V

5.4 V

5V

5.2 V

4.8 V

4.6 V

Si-NWs / 3 nm Al2O3

30

4.4 V

40

4.2 V

Capacitance (µF.cm-2)

4 3 2 1

1 mA.cm-2

0 0.0

1.5x106

0.1

5

5.0x10

6

1.0x10 Cycle number (-)

5.5 V 5.4 V

5V

5.2 V

99.6

4.8 V

Si-NWs / 3 nm Al2O3

4.6 V

99.8

4.4 V

100.0

Current density (mA.cm-2)

4.5 V 4.4 V

99.6

4.3 V

Pristine Si-NWs

4.2 V

99.8

0.0

0.3

0.4

0.5

d)

100.0

4.1 V

c)

0.2

Time (s)

Cycle number (-)

4.2 V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 20 of 31

6

1.5x10

0.10 0.05 0.00 -0.05

1 V.s-1

-0.10 0

1

2 3 4 5 Cell Voltage (V)

Figure 3. Electrochemical characterization of symmetric capacitor devices based on Si-NWs / 3 nm Al2O3 and pristine Si-NWs: a) Evolution of the capacitance during galvanostatic charge/discharge cycling at 1 mA.cm-2 using different maximum cell voltages; b) Galvanostatic charge/discharge curves for pristine Si-NWs with 4 V cell voltage (solid black line) and for SiNWs / 3 nm with 5.1 and 5.5 V cell voltage (respectively solid and dashed red lines); c) Evolution of the Coulombic efficiency of the galvanostatic charge/discharge at 1 mA.cm-2 using different maximum cell voltages; d) Cyclic voltammetry curves evolution of Si-NWs / 3 nm Al2O3 during the cycling described in figure 3 a) and c): up to 4 V (blue), up to 5 V (purple), and up to 5.5 V (red); The black dashed line represents the cyclic voltammetry curve of pristine SiNWs after cycling at 4 V.


20

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Table 1: Comparison of electrochemical properties of Al2O3 coated Si-NWs 2 electrodes devices.

a

Al2O3 thickness (nm)

ESRa

Umaxb

C (µF.cm-2)

C fadec

Pmaxd

Ee

After cyclingc

(%)

(mW.cm-2)

(mJ.cm-2)

Coulombic efficiencyf (%)

(Ω.cm2)

(V)

Initial

Pristine

15.7

4

63

50.5

19.8

255

0.40

99.92

1

18.1

4.3

73

56.1

23.2

256

0.52

99.94

2

17.7

4.7

46.1

40.4

12.4

313

0.45

99.89

3

20.1

5.1 - 5.5

38.3

37.0

3.4

324 - 376

0.48 - 0.56

99.97

5

23.1

5.5 - 6

28.7

27.8

3.1

328 - 390

0.42 - 0.50

99.95

derived from high frequency zone in EIS, recorded before cycling;

b

derived from cyclic

voltammetry at 1 V.s-1 after cycling at 1 mA.cm-2, 4 V; in bold italic: maximum cell voltage tested during cycling, without any significant capacitance fade occurring;

c

after 106

galvanostatic charge/discharges cycles under 1 mA.cm-2 between 0 and 4 V cell voltage;

d

derived from ESR and Umax; e derived from Umax and capacitance after cycling at 1 mA.cm-2;

f

averaged Coulombic efficiency for the last 100 000 cycles during cycling at 1 mA.cm-2, 4 V;


21


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Page 22 of 31

Supporting Information. Further physiochemical characterization of the silicon nanowires and bulk silicon coated by Al2O3 including electrochemical characterization, XPS, STEM HAADF EDX. Moreover a Ragone plot of the symmetric Si-NWs / 3 nm Al2O3 supercapacitors performances compared to other silicon based supercapacitors and state of the art micro-supercapacitors can be found. ASSOCIATED CONTENT This material is available free of charge via the Internet at http://pubs.acs.org. AUTHOR INFORMATION Corresponding Author *Said Sadki, Corresponding author e-mail: [email protected] Author Contributions The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript. ABBREVIATIONS ALD, atomic layer deposition; CVD, chemical vapor deposition; EDLC, electrochemical double layer capacitor; EDX, energy dispersive x-ray spectroscopy; EIS, electrochemical impedance spectroscopy; EMI-TFSI, 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide; ESR, equivalent series resistance; HAADF, high angle annular dark field detector; SEM, scanning electron microscopy; Si-NWs, silicon nanowires; Si-NTrs, silicon nanotrees; STEM, scanning transmission electron microscopy; TEM, transmission electron microscopy; TMA, trimethylaluminum; VLS, vapor liquid solid; XPS, x-ray photoelectron spectroscopy.


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Table of Contents Graphic


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