Bandwidth Limitation of Directly Contacted GrapheneâSilicon

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Bandwidth limitation of directly contacted graphene-silicon optoelectronics Dun Mao, Thomas Kananen, Tiantian Li, Anishkumar Soman, Jeffrey Sinsky, Nicholas Petrone, James C. Hone, Po Dong, and Tingyi Gu ACS Appl. Electron. Mater., Just Accepted Manuscript • Publication Date (Web): 22 Jan 2019 Downloaded from http://pubs.acs.org on January 22, 2019

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ACS Applied Electronic Materials

Bandwidth limitation of directly contacted graphene-silicon optoelectronics Dun Mao1, Thomas Kananen1, Tiantian Li1, Anishkumar Soman1, Jeffrey Sinsky2, Nicholas Petrone3, James Hone3, Po Dong2, Tingyi Gu1* 1

Department of Electrical and Computer Engineering, University of Delaware, Newark, Delaware 19716,

USA 2

Nokia Bell Labs, 791 Holmdel Road, Holmdel, New Jersey 07733, USA

3

Department of Mechanical Engineering, Columbia University, New York, NY 10027

ABSTRACT. Electrically contacting layered materials on a Complementary Metal-Oxide-Semiconductor Transistor (CMOS) processed lateral silicon homojunction offers a new platform enabling post-fabrication free high-speed hybrid optoelectronic devices on chip. Understanding detailed junction formation and radio frequency (RF) response on the multi-component interface between directly contacted silicon nanophotonic devices and low bandgap materials is essential for predicting the performance of those active components. Electrostatic carrier distribution, as well as the dynamics of externally injected carriers, are strongly influenced by spatially varying Schottky barriers on the vertical heterojunctions. In this work, we analyze the high-speed RF response of a graphene ‘bonded’ lateral silicon p-i-n junction. The multi-junction structure on the hybrid structure is parameterized by fitting a small-signal model to the broadband coherent radio-frequency response of the hybrid device at a set of different carrier injection rates. By engineering the device dimensions, it is possible to suppress the resistance-capacitance delay to be less than a picosecond and enable sub-Terahertz bandwidth operation.

Keywords: graphene, RC constant limit, small signal model, P-I-N junction, heterojunction.

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INTRODUCTION The development of a back-end-of-line compatible hybrid integration of direct bandgap material on a scalable silicon (Si) nanophotonic platform is desired for low power miniaturized photonic transceivers and on-chip optical sensor systems. The low loss Si waveguide provides a platform for large scale integration, however, Si’s carrier mobility/indirect bandgap limit the bandwidth/efficiency of Si based active devices. Graphene (G), given its superior electrical and thermal conductivity, is promising for being the 'beyondCMOS' material1. However, deterministic and scalable localized doping control in semimetal G is still a challenge. Low interfacial defects between G and Si can improve the carrier injection rate,2 as well as reducing the low frequency noise.3 In this paper, we focus on understanding the depletion region formation of G on Si-on-insulator (SOI) substrate, and the high-speed response of the G homojunction. A hybrid approach of inducing G homojunctions through substrate induced electro-static doping on lateral Si p-i-n junction has been developed as a post-fabrication free process. It has been demonstrated that by contacting G on atomically flat crystallline Si substrate with varying doping levels, it is possible to modify G’s carrier mobility and Fermi levels.4-10 The junction operates fundamentally different from the metal-G heterojunction-based field effect transistor designs with top/back gating, where the carrier transportation is dominated by diffusion process and the built-in electric field is mostly concentrated in a narrow G-metal contact region.11-14 The G-Si hybrid structure with lateral p-i-n junction is useful for components in the high-speed optical communication with low cost and reliable fabrication process.2 The multiple Schottky contacts are calibrated by the small-signal model and the parameters of the junction can be separated through curve fitting the model. The study of the collective RF response in directly contacted twodimensional (2D) material-silicon hybrid device sets a foundation towards back-end-of-line compatible electric-terahertz oscillator,15-17 energy efficient tunneling field effect transistors18-19 ultrafast photodetector20-23 and other integrated optoelectronic devices.24-27


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EXPERIMENTAL SECTION The top view of the device layout is illustrated in Figure 1(a). The input light can be coupled into/out of the PhC WG (~180 μm) though channel WGs.29 The optical mode is confined in the suspended PhC WG and evanescently coupled to the G layer (Figure 1(b)). G is electrically connected to heavily p and n doped silicon while isolated from metal electrodes (Figure 1(c)). The metal electrodes are connected with the doped Si extended under the SiO2 layer through via. The PhC WGs are defined on the 250 nm Si device layer, supported by the 2 μm oxide layer. The suspended G near the edges of the trench are removed during an Acetone bath and thus electrically isolated from metal electrodes, as shown in the scanning electron microscope (SEM) image in Figure 1(d). The atomic force microscope (AFM) image (Figure 1(e)) shows the detailed profile of G cladding on suspended silicon membrane, indicating full coverage of G on Si PhC WG region. The p and n doped Si in the device layer of SOI configuration is achieved by ion implantation by Boron and Phosphorus respectively. The doping density, carrier mobility and resistivity of p-type and n-type Si are characterized to be 5×1018 cm-3, mobility 70.8 cm2/V-s, resistivity 8.8 mΩ-cm, and 5×1018 cm, mobility 115 cm2/V-s, resistivity 5.4 mΩ-cm respectively. The intrinsic region is left non-intentionally

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doped, which is characterized to be lightly n doped (doping density of 1016 cm-3, mobility 1184 cm2/V-s, resistivity 0.53 Ω-cm).15 The Root Mean Square (r.m.s.) surface roughness of the CMOS processed Si is measured to be less than 1 nm. The r.m.s. roughness increases to 2 nm after wet-transferring of chemical vapor deposition. 28 The substrate induced electrostatic doping in G is characterized by Micro-Raman spectrometer, with 532 nm excitation laser and spot size of 0.6 µm (Figure 1 (f-g)). The optical power is kept below 1 mW for avoiding any nonlinear response. The blue, black and red curves in Figure 1(f) represent the Raman spectra of graphene directly contacting to n-Si, i-Si and p-Si respectively (the three laser-probed areas marked in Figure 1(d) and (e) with the correspondent color). The three Raman spectra were taken at three adjacent spot on the same sample (plot in log scale). All the laser parameters are kept same throughout the measurement and leave the substrate doping level as the only variable. Higher doping levels significantly reduce the free carrier lifetime and phonon lifetime, and thus gives rises to lower background signal of the 3 ACS Paragon Plus Environment


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G Raman spectra (red and blue solid curves). The substrate induced electrostatic doping in G is confirmed by evidences in the Raman spectra: (1) Reduced 2D versus G peak intensity ratio and (2) red shifted 2D peak wavenumber. As 2D peaks lies on double and triple resonance between adjacent carbon atoms, they can be sensitive to the doping level variations in graphene. The wavenumber blue shifted 5 cm-1 for G on p-doped Si and 4 cm-1 for n-doped Si. Both doping dependent Raman spectra trends align with the observations reported in previous work.14 The Dirac point of G is between the conduction and valence bands of Si. Direct contact between graphene and p/n-doped Si forms positive/negative band bending in silicon and leads to electrostatic charge in graphene in opposite signs.2 It is noted that the metal contact is isolated from G and WG by a SiO2 isolation layer. All the Raman spectra were taken without external bias. The measured Raman parameters on the doped Si membrane are the average between the suspended G (intrinsic) and the supported G (doped). The suspended G over the holes takes about 30% of the whole sheet.

Figure 1. Device schematics (a) Optical image of the device top view (Scale bar: 20 µm). (b) The cross sectional optical mode profile at 1550 nm for G-Si photonic crystal waveguide (PhC WG). (c) The crosssectional electrical design of the device.2 (d) Scanning electron microscope (SEM) image of the G cladded Si PhC WG (Scale bar: 20 µm). Inset: Enlarged image of the device schematics, three circles from top to 4 ACS Paragon Plus Environment

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bottom mark the probed laser spot for G on p-doped Si, i-doped Si and n-doped Si for Raman spectra respectively (Scale bar: 1 m). (e) Atomic Force Microscopy image of G covered Si PhC WG. (f) Raman spectrum of G on n-doped, intrinsic and p-doped Si. (g) Raman spectra of 2D peak in (f). We compare the direct current (DC) and alternating current (AC) responses of the monolithic and hybrid devices (Figure 2). Agilent PNA-X N5247A is used for measuring the broadband AC response after careful calibration through a GGB CS-8 calibration Substrate (Short-Open-Load one port calibration). A GGB 40A-GS-150-P-N probe was employed for DC and RF measurements. Input power was leveled to -5 dBm (through power level calibration at an earlier time) at the end of the coaxial cable to avoid any nonlinear response.

Figure 2. Direct current and alternating current characterization for the hybrid devices. (a) I-V curves for Si p-i-n (red triangular), fitted I-V for Si p-i-n (red line), G-Si hybrid p-i-n junction (blue circle) and fitted I-V for G-Si hybrid p-i-n junction (blue line). (b) Measured and modelled S11 magnitude of Si. (c) Measured and modelled S11 magnitude of G-Si. Direct Current (DC) Measurement. Figure 2(a) compares the DC current-voltage (IV) responses of monolithic (red triangular) and hybrid (blue circle) devices as shown in Figure 1. It is observed that the highly conductive G channel on Si p-i-n junction does not increase dark current. By fitting the diode equation30-31 (𝐼 = 𝐼0 𝑒

𝑞(𝑉+𝐼𝑅𝑠 ) 𝑛𝑘𝑇

+

𝑉+𝐼𝑅𝑠 ) into the experimental data, we can quantitatively understand the difference 𝑅𝑆𝐻

of the diode parameters between the two devices. In the diode equation, I is the dark current, 𝐼0 is the reverse saturation 5 ACS Paragon Plus Environment


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current, RS is the total series resistance (including p/n doped region resistance, interconnect resistance and DC probe contact resistance during the test). RSH is the shunt resistance, k is Boltzmann constant, and T is temperature. The series resistance reduces from RS_Si = 0.51 kΩ (monolithic device) reduces to RS_G-Si = 0.29 kΩ (hybrid device). The shunt resistance reduces from RSH_Si = 148 kΩ (monolithic device) to RSH_G-Si = 36 kΩ. (hybrid device). The reverse saturation current increases from I0_Si = 0.286 µA (monolithic device) to I0_G-Si = 2.36 µA (hybrid device) with the additional graphene layer. G’s high conductivity reduces the series and shunt resistivity of the hybrid device. As the reverse saturation current is inversely related to the carrier lifetime, it is estimated that the effective carrier lifetime in the hybrid device reduces to 1/10 compared to the monolithic device. Alternating Current (AC) Measurement. DC measurement shows the overall diode characterization of the hybrid device, as the simple DC measurement can’t distinguish individual components of the multiple vertical and lateral junctions in the hybrid device, we combine Small-Signal Model and broadband AC measurement (0.7 ~ 40 GHz) for separating parameters of different junctions. Figure 2 (b) and (c) compare the S parameter of monolithic (Figure 2(b)) and hybrid p-i-n junction under forward bias. The experimental data (dashed curves) are fitted by small-signal model (solid curves), optimized by Advanced Design System (ADS) from Keysight.32 Bias voltages of 0, 4 and 8 V are shown here for clarity, and S11 response at other bias voltage can be found in supporting information file S1. From figure 2(c), we observed that the forward bias significantly modifies the junction formation in the hybrid device (capacitance, inductance and resistance in G/Si contacts) and thus the broadband S11 response, while the depletion region of monolithic device changes little with forward bias to 8V. RESULTS AND DISCUSSION Small-signal model. The small-signal model for monolithic and hybrid devices (solid curves in Figure 2(bc)) are illustrated in Figure 3(a) and (b) respectively.31,33-35 The red, blue, deep-blue regions represent the Si p doped, intrinsic and n doped region in Figure 3. For the hybrid device (Figure 3(b)), G (golden part) is contacted to Si p-i-n junction, across the p and n doped regions. Gradient algorithm was used for the optimization process of curve fitting in ADS. At each bias voltage, the corresponding circuit elements (R, 6 ACS Paragon Plus Environment

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L, C) are optimized globally for minimizing the difference between the simulated and the measurement data. We first extract the junction parameters of the silicon junction by curve fitting into monolithic devices (Figure 2(b)). Next, we construct the hybrid device by adding the G-Si heterojunctions and G homojunctions in the hybrid structure (Figure 2(c)) onto the parameter space of the monolithic devices. In the monolithic device (Figure 3(a)), R3 is the contact resistance between metal and heavily doped Si. R5 is the series resistances of doped Si. C1 and R2 are the parasitic the capacitance and resistance from the substrate. The leakage current between the electrodes is presented by R1. Rpi and Rin are the resistances between p-i region, i-n region respectively. Cpi, Cin represent the capacitances between p-i region, i-n region respectively. In the small-signal model for the hybrid device (Figure 3(b)), we add additional G related components (vertical diodes for G-Si contacts and G homojunctions) to the monolithic model. Rgp-i and Rgni

are the series resistances of G between p-i and n-i regions respectively, Lgp-i and Lgn-i are the inductances

of G between p-i and n-i regions respectively. Three independent Resistance-Capacitance (RC) elements represent the vertical junctions formed between G and silicon with different doping levels: junction capacitances Cjp, Cji and Cjn denote the capacitances between G and p, i, n regions. Junction resistances Rjp, Rji and Rjn represent the resistances between G and p, i, n regions respectively.

Figure 3. Small-signal models for (a) monolithic Si p-i-n junction, (b) G-Si hybrid p-i-n junction. The small-signal models in Figure 3 are constructed based on the built-in electric field distribution (Figure 4). The simulation of two-dimensional built-in electric field is performed by by using 3D finite element Poisson/drift-diffusion solver (Lumerical DEVICE).36 Figure 4(a) and (b) are simulated x component (in plane) and z component (out of plane) built-in electric field distribution on the cross-sectional plane of the 7 ACS Paragon Plus Environment


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monolithic PhC WG (corresponding to figure 3(a)). Figure 4(c) and (d) are the ones for hybrid devices (corresponding to figure 3(b)). Figures 4(e) compares the in-plane built-in electric field on top surface of Si PhC membrane. It is observed that the in-plane electric field is formed in the highly conductive G layer (blue curve in Figure 4(e)). Compared to the monolithic sample (grey dashed curve in Figure 4(e)), the inplane built-in electric field shifts from the Si p-i junction to the graphene-n Si contact region. Figure 4(f) compares the out-of-plane built-in electric field along graphene plane. As the Fermi level of G is between the one of p doped and n doped silicon, the out-of-plane built-in electric field changes direction for G on p doped Si (left side for the blue curve in Figure 4(f)) and n doped Si (right side for the blue curve in Figure 4(f)), which guides the electrons (on G-n Si interface) and holes (on G-p Si interface) from G into Si.

Figure 4. Built-in electric fields at G-Si interface under zero bias. (a) x and (b) z component of built-in electric fields on the cross-sectional plane of monolithic Si p-i-n junction. (c) x and (d) z component of built-in Electrical fields of the hybrid device. (e) x and (f) z component of the built-in electric field on graphene/air-top silicon interface. Lateral forward bias can modify the multiple vertical built-in electric field in the hybrid device (supporting information file S2). Under forward bias, the higher injection level increases the effective G doping level, and thus its inductance and conductivity (supporting information file S3). Through curve 8 ACS Paragon Plus Environment

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fitting the small-signal model to the voltage varying S11, we can separately study each junction variation with forward bias. The voltage dependent capacitance, inductance and resistance of p-i-n junction for G-Si contact interface are extracted from the small signal model fittings (Figure 5). Both resistance and inductance of G homojunctions (Lgp-i, Lgn-i, Rgp-i, Rgn-i) reduces with bias, indicating increased carrier density in G with carrier injection through substrate p-i-n junction. Among the heterogeneous junction elements (capacitance and resistance of G and Si interface), capacitance (Figure 5(c)) and resistance (Figure 5(d)) of the G-n Si region vary most significantly with forward bias.

Figure 5. Elements of G-Si junction (in Figure 3(b)) varying under bias. (a) Inductance of G homojunction (Lgp-i, Lgn-i) versus bias voltage and the estimated carrier density in G (supporting information file S3); (b) Resistance of G homojunctions (Rgp-i, Rgn-i) versus bias voltage37-38 and estimated carrier density in G. The details of G inductance and resistance estimation are in the supporting information file S3; (c) Capacitance of G-Si junction in p, i and n region; (d) Resistance of G-Si junction in p, i and n region (rest of circuit elements varying with bias can be seen in supporting information file S4). The error bars in (c) and (d) are negligible.



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In Figure 5(a-b), the voltage dependent capacitance variation of G-Si contacts depends on the substrate doping levels. G-p Si and G-i Si contact capacitances vary little with bias increases while G-n Si capacitance increases with bias. The junction resistance shows that Rji and Rjp change only by a small amount while Rjn decreases as the bias increases. The bias dependent RC constants indicate most of the voltage drop is applied on the G-n Si contact junction, as its junction capacitance Cjn and resistance Rjn decreases dramatically with forward bias (Figure 5 (c-d)). The small-signal fitted parameters are consistent with the simulated built-in electric fields: that the z component (which is corresponding to vertical junction) of the built-in electric field around the G-n junction is much larger than other junctions as shown in Figure 4(d). From the resistance and capacitance in graphene, we estimated the range and scale of G doping levels (more details can be seen in supporting information file S3). Based on the relation between inductance, resistance, and carrier density: the fitting results turn out to be reasonable and consistent within the estimated range. The carrier density in G is estimated to be around 1013 cm-2 (supporting information file S3).

Figure 6. Bias dependent depletion region on G-n Si. Built-in electric field components (a) Ex under 0V, (b) Ex under 8V, (c) Ez under 0V, (d) Ez under 8V bias at G-n region of Si interface for the vertical junction, respectively. For the built-in electric field components of the hybrid device under other intermediate biases voltage across the p-i-n junction (see supporting information S2 for more details). 10 ACS Paragon Plus Environment

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Comparing the small signal model and built-in electric field simulations, we observed that the G-n Si vary most significantly with the forward bias. Figure 6 compares the in-plane (Ex) and out-of-plane (Ez) built-in electric field components at the G-n Si interface under bias of 0V and 8V. At forward bias, strong lateral electric field (Ex) is formed out of the boundary of G/n-Si contact (Figure 6(b)), while the extra vertical built-in electric field concentrates under the edge of G (Figure 6(d)). The extra depletion region formed near the edge of G/n-Si contact leads to the decreased resistance and capacitance (Figure 6 (b)(d)).

Figure 7. Broadband RF response of the device. (a) Measured (solid blue curve) and small signal model extrapolated S11 (red dashed line) from 0 to 120 GHz under zero bias (b) measured photoresponse S21 from 0 to 40 GHz for G-Si p-i-n junction. Finally, we then use the constructed small-signal model to extrapolate the 3dB bandwidth of the device limited by the RC constant (Figure 7(a)). The extrapolated model predicts the RC constant limited 3dB bandwidth to be over 100 GHz. As the optoelectronic device’s speed is limited by both RC constant and carrier transit time, we experimentally verify the optoelectronic response (photo-electron conversion) up to 40 GHz (Figure 7(b)). The flat response from DC to 40 GHz indicates the bandwidth of the optoelectronic responses can be well beyond the instrument bandwidth limitation. The RC constant limited bandwidth could be further improved by reducing the capacitance of G and n-Si contact. Among the multi-components in the small signal model, the overall 3 dB bandwidth of S11 is most sensitive to the capacitance variation on G/n Si region. Decreasing G/n Si capacitance will lead to deduction of overall RC constant and further improve the 3 dB bandwidth. The capacitance of G/n Si contact can be reduced through increasing the 11 ACS Paragon Plus Environment


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depletion region in n Si. Reducing the doping density in n Si can effectively enhance the depletion region. Also, the bandwidth can be enhanced by fabricating a gate electrode for controlling the Fermi level in G, which can be used to balance the capacitances among G/p-Si, G/i-Si and G/n-Si for achieving the net RC constant. CONCLUSION In this work, we investigate the voltage dependent multi-junction variation in the hybrid graphene-Si lateral p-i-n junction. The Si substrate is a CMOS processed lateral p-i-n junction with different doping levels. The multiple G-Si junction and G homojunctions are parameterized by curve-fitting the small-signal model to the experimental data. The results are compared to the electric field distribution through directly solving Maxwell equations. The simulation results show that 1) the potential bandwidth of the new device configuration could be more than 100 GHz; 2) The forward bias applied through Si p-i-n junction substrate can effectively modify the G doping levels and vertical built-in electric field on G-Si contact; 3) The G-n Si space varies most significantly with forward bias. As the RC constant limit is always the bottleneck of hybrid 2D material based active silicon photonic component, the result will be useful for the design of new device configurations that can be incorporated into the design of ultrafast integrated active optoelectronic devices on active Si photonics platform. ASSOCIATED CONTENT Supporting Information. This material is available free of charge via the Internet at http://pubs.acs.org. S1, S11 Curve fitting results for the small-signal model; S2, Simulated built-in electric field components Ex, Ez at hybrid junction interface (xz cross-sectional plane) of G and Si n region under bias of 0 V, 2 V, 4 V, 6 V, 8 V; S3, Estimation of graphene inductance, resistance; S4, Bias dependent junction parameters; S5. Summary of G based Photodetectors and modulators. AUTHOR INFORMATION Corresponding Author 12 ACS Paragon Plus Environment

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*E-mail: [email protected] Notes The authors declare no competing financial interest. ACKNOWLEDGMENT T. L. acknowledges the discussions with members of State Key Laboratory of Advanced Optical Communication Systems and Networks, China. D.M. thanks for fruitful discussion with Dr. Mercante and Dr. Prather from E.C.E. department of University of Delaware. D. M. and T. K. are supported by AFOSR YIP program (FA9550-18-1-0300). T. L. is supported by NASA ECF (80NSSC17K0526) and A. S. is supported by NASA EPSCoR program (80NSSC17M0035). J.S. and P.D. acknowledge the support from Nokia Bell labs. N.P. and J.H. acknowledge the support from Columbia University. REFERENCES

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