Carbon-Radical's Intra-Grain-Diffusion for Wafer-Scale, Direct Growth

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Cite This: ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

Intergrain Diffusion of Carbon Radical for Wafer-Scale, Direct Growth of Graphene on Silicon-Based Dielectrics Phong Nguyen,†,§ Sanjay K. Behura,†,§ Michael R. Seacrist,‡ and Vikas Berry*,† †

Department of Chemical Engineering, University of Illinois at Chicago, 810 S Clinton Street, Chicago, Illinois 60607, United States SunEdison Semiconductor, 501 Pearl Drive, Saint Peters, Missouri 63376, United States

‡

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S Supporting Information *

ABSTRACT: Graphene intrinsically hosts charge-carriers with ultrahigh mobility and possesses a high quantum capacitance, which are attractive attributes for nanoelectronic applications requiring graphene-on-substrate base architecture. Most of the current techniques for graphene production rely on the growth on metal catalyst surfaces, followed by a contamination-prone transfer process to put graphene on a desired dielectric substrate. Therefore, a direct graphene deposition process on dielectric surfaces is crucial to avoid polymer-adsorption-related contamination from the transfer process. Here, we present a chemical-diffusion mechanism of a process for transfer-free growth of graphene on silicon-based gate-dielectric substrates via low-pressure chemical vapor deposition. The process relies on the diffusion of catalytically produced carbon radicals through polycrystalline copper (Cu) grain boundaries and their crystallization at the interface of Cu and underneath silicon-based gate-dielectric substrates. The graphene produced exhibits low-defect multilayer domains (La ∼ 140 nm) with turbostratic orientations as revealed by selected area electron diffraction. Further, graphene growth between Cu and the substrate was 2-fold faster on SiO2/Si(111) substrate than on SiO2/Si(100). The process parameters such as growth temperature and gas compositions (hydrogen (H2)/methane (CH4) flow rate ratio) play critical roles in the formation of high-quality graphene films. The low-temperature back-gating charge transport measurements of the interfacial graphene show density-independent mobility for holes and electrons. Consequently, the analysis of electronic transport at various temperatures reveals a dominant Coulombic scattering, a thermal activation energy (2.0 ± 0.2 meV), and two-dimensional hopping conduction in the graphene field-effect transistor. A band overlapping energy of 2.3 ± 0.4 meV is estimated by employing the simple two-band model. KEYWORDS: graphene, CVD, direct growth, defects, electrical transport

1. INTRODUCTION

metal-oxide-semiconductor devices, such as radio-frequency switches and photonic modulators. High-quality and large-area graphene films have been successfully produced on various metal surfaces via catalytic chemical vapor deposition (CVD).4 For characterizations and device fabrications, it is essential to transfer the as-grown graphene onto selected dielectric substrates. However, in such wet/dry transfer processes, graphene is supported by a sacrificial polymer layer followed by etching of the metal layer. Subsequently, the polymer/graphene is transferred to a desired substrate, and the supporting polymer is removed either by dissolving in a solvent or by thermal treatments. The graphene located via these transfer steps is unfavorable for high-performance nano- and optoelectronic devices and industrial applications as these graphene films still contain polymeric adsorbates on the top surface and metallic

Graphene, conclusively isolated in 2004, is a monolayer (thinnest material ∼0.34 nm) of sp2 bonded carbon atoms arranged in a two-dimensional (2D) honeycomb lattice and is the primary building block of all of the carbonaceous materials of all other dimensions such as graphite (three-dimensional), carbon nanotubes (one-dimensional), and fullerene (zerodimensional).1 Graphene possesses a plethora of extraordinary properties, such as ballistic electronic transport (mean free path over 0.4 μm) with high charge carrier mobility (200 000 cm2 V−1 s−1) at 300 K, superior thermal conductivity (5000 Wm−1K−1), room-temperature quantum Hall effect, and low intrinsic noise (shot noise and dark noise). According to the International Technology Roadmap for Semiconductors,2,3 owing to exceptional electronic and thermal properties of graphene, it can be considered for post-silicon (Si) electronics. Furthermore, the strong interaction of graphene with photons and its high electrochemical stability could enumerate advanced functions to silicon (Si)-based complementary © XXXX American Chemical Society

Received: May 9, 2018 Accepted: July 16, 2018 Published: July 16, 2018 A

DOI: 10.1021/acsami.8b07655 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces

Figure 1. Synthesis and characterizations of directly grown interfacial graphene on Si-based gate-dielectric substrates (SiO2/Si): (a) LPCVD system setup for the direct growth of graphene. (b) Graphene film on SiO2/Si(111) surfaces. (c) Scanning electron microscopy (SEM) topography. (d) SAED and its intensity profile of the A−B stacking region. (e) X-ray photoelectron spectroscopy (XPS) of C 1s at high resolution and at room temperature (300 K).

ature charge transport measurements of the interfacial graphene layer are also elucidated.

impurities at the bottom, which further deteriorate intrinsic characteristics of graphene. To date, the growth of graphene via catalyst-free CVD methods have been developed on various nonmetallic substrates such as Si-based dielectric substrates,5−11 aluminum oxide (Al2O3),12 strontium titanate (SrTiO3),13 and hexagonal boron nitride (h-BN).14−16 Such techniques require high growth temperature, longer growth time, or additional modification of CVD setup. Incorporating thin catalytic transition metal films (copper (Cu), nickel (Ni), or cobalt (Co)) on desired dielectric substrates helps in reduction in the growth temperature, reaction time, and defects, enabling the synthesis of high-quality graphene films. In case of Ni, the formation of graphene at the interface of substrate and catalytic film is due to the segregation of carbon radicals from the Ni bulk (carbon solubility in Ni ∼ 1.2 atom % at 900 °C).17−19 Owing to this nonequilibrium process, the production of uniform and low-defect density graphene films requires a precise control of cooling rates. In contrast, Cu catalyzes lowdefect density graphene films due to the surface adsorption mechanism (carbon solubility in Cu ∼ 0.02 atom % at 1084 °C).18,19 Further, Su et al.19 have demonstrated the growth of graphene at the interface of polycrystalline Cu thin film and SiO2/Si substrate. However, the formation mechanism of such interfacial graphene is not well comprehended. In this article, we present the chemistry and mechanistic understanding of direct-growth, transfer-free graphene, which nucleates at the interface of polycrystalline Cu and the Si-based gate-dielectric substrates. In addition to the detailed structural characteristics, including Raman spectroscopy and selected area electron diffraction (SAED) pattern analysis, low-temper-

2. EXPERIMENTAL SECTION A thin film (∼150 nm) of Cu was thermally evaporated from Cu pellets (99.999% purity, Kurt. J. Lesker) on selected dielectric substrates of different crystallographic orientations such as SiO2/ Si(100) and SiO2/Si(111). For the synthesis of graphene, the Cucoated dielectric substrate (Cu/SiO2/Si) was placed inside the center of the heating zone of a quartz tube (ϕ = 1″). The quartz tube was set inside a split MTI-OTF-1200X furnace designed as a low-pressure CVD (LPCVD) system, as shown in Figure 1a. Here, methane (CH4, 99.95% purity, Praxair) as the carbon source and hydrogen (H2, 99.9999%, Praxair) as the reducing gas were used. The oxidizing impurity concentrations associated with these gases are shown in the Supporting Information Section 1. To synthesize thin films of graphene directly on the Si-based substrates, the growth was conducted via the following steps: (1) thermal annealing of Cu/ SiO2/Si substrate was carried out at 750 °C with 15 sccm of H2 (PTot = 80 mTorr), (2) growth of graphene was performed at a temperature range of 750−900 °C with different ratios of CH4:H2 (PTot = 2 Torr), and (3) the furnace was cooled slowly (∼20 °C min−1) to 700 °C, and then cooled fast by opening the furnace cover (∼100 °C min−1). Finally, the graphene films were formed on both the top and bottom surfaces of Cu (top graphene and interfaced graphene). The top graphene film and the Cu layer were subsequently removed via oxygen plasma etching and wet-chemical etching with ferric nitrate (Fe(NO3)3) solution (0.6 mg mL−1), respectively. An interfacial graphene film directly produced on SiO2/Si substrate (area 0.8″ × 0.8″) is demonstrated in Figure 1b. Further details on the substrate preparations for the CVD growth, transmission electron microscopy characterizations, and low-temperature electrical transport measurements are presented in the Supporting Information Section 1. B


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Figure 2. (a) Process involved in the synthesis of graphene at the interface of SiO2 dielectric and Cu metal. (b) Formation of interface graphene at the edge of the grain boundaries and the corresponding Raman G band mapping (scale bar: 4 μm [red] and 10 μm [white]). (c) Coverage rate of the interfacial graphene on SiO2/Si(111) and SiO2/Si(100) substrates. (d) X-ray diffraction (XRD) pattern of post-CVD Cu crystal lattice on SiO2/Si(111) and SiO2/Si(100) substrates.

3. RESULTS AND DISCUSSION Because the directly-grown, transfer-free, and large-area graphene will have immense application potential, it is critical to evaluate its structural, crystallographic, and associated defects via combined microscopic and spectroscopic techniques. Scanning electron microscopy (SEM) topographic image depicts that the surface of the continuous, thin, and directly grown graphene film on SiO2/Si consists of multilayer domains (Figure 1c). Despite the growth under low-pressure conditions, this evidence implies that the interfacial graphene growth is not controlled by the surface reaction step.20 The details of the growth mechanism and the resultant graphene structure are discussed in later sections. Further, selected area electron diffraction (SAED) pattern analysis was conducted to analyze the crystallinity and rotation angle of the interfacial graphene. A mixture of A−B stacked and turbostratic arranged layers was observed in the synthesized graphene films. Hexagonal symmetry (6-fold) (bright SAED patterns) is clearly noticed, indicating the crystalline nature of the graphene domains, and the Bravais−Miller (hkil) indices were used to label the diffraction peaks, as shown in the left side of Figure 1d. The calculated lattice (d) spacing is 2.4 Å, which corresponds to the graphenic structure.21 Further, the intensity of the inner peaks from the equivalent planes {1100} is always lower than that of the outer peaks from {2100}. The intensity ratios of I1̅1̅20/I1̅010 and I12̅10/I1̅100 are greater than 2 and 3, respectively, as shown in the right side of Figure 1d, indicating the nontwisted A−B stacking structure (0° rotation) of the interfaced graphene on average22 (see the Supporting Information Section 2 for turbostratic graphene). The findings obtained here are in good agreement with the results of the graphene produced on top of metal catalytic surfaces via CVD.23 Further, the quality of the graphene films was analyzed

by X-ray photoelectron spectroscopy (XPS, Kratos AXIS-165). The elemental survey scan shows no metallic elements arising from the Cu catalyst and Fe(NO3)3 etchant (see the Supporting Information Section 3). The presence of graphene is further speculated by the characteristic sp2 CC peak at 284.5 eV. Further, the deconvolution of the C 1s peak shows the presence of defects in graphene domain, which may be attributed to the sp3 carbon components, C−O and O−CO peaks at 286.1 and 289.4 eV, respectively.24 The sp3 carbon components may originate from three sources: (1) adventitious carbon in the XPS chamber, (2) adventitious carbon from the ambient condition, and (3) defects in the synthesized thin graphene domains, which are further confirmed through Raman spectroscopy presented in the following section. Further, a control experiment is also conducted with no carbon sources to see whether the contaminants with carbon during substrate cleaning using piranha solution can produce any graphene by themselves. The Raman spectroscopic results show that there is no signature of graphene formation (see the Supporting Information Section 4). This work elucidates the growth mechanism of the interfacial graphene, which is described in the following elementary steps, as shown in Figure 2a. (1) The precursors (CH4 and H2) transport through the bulk boundary layer and adsorb on the Cu surface. (2) Next, the decomposition of the CH4 precursor to carbon radicals (Cx or CHx [x = 1−4]) occurs in the presence of reducing agent (H2) and catalyst surface (Cu). This is followed by the exothermic reaction of the carbon dimerization 2C*(s) → C2 spontaneously on the Cu surface.25,26 Hence, the major constituent of the carbon radicals is expected to be dimer and monomer species.27 (3) Such carbon radicals subsequently mobilized on the Cu surface, transported through the Cu grain boundary to the C


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Figure 3. (a) Raman spectra of the directly grown interfacial graphene on Si-based gate-dielectric substrates (SiO2/Si) at multiple areas. Inset shows a representative fit of the 2D band. (b) Raman spectra of D and G bands at various reaction temperatures. (c) Domain size (La) and ID/IG ratio with respect to the reaction temperatures. (d) Domain size (La) and ID/IG ratio with respect to the H2/CH4 flow rate ratio.

films developed here is different. Further, the mobility of the carbon radicals on Cu surface is relatively fast.32 The kinetics of these serial events suggests that the rate-limiting step should be the grain boundary diffusion of carbon radicals (see the Supporting Information Section 9). Figure 2c shows the coverage rate of the interfacial graphene on SiO2/Si(100) and SiO2/Si(111) surfaces. It is critical to note that at the beginning of the growth, the concentration of the carbon radical has to reach the critical value to compete with desorption; hence, there is a delay in the growth results. Further, we have also observed that the growth of graphene at the interface of Cu and SiO2/Si(111) takes place 2-fold faster than that of Cu and SiO2/Si(100). Therefore, it is critical to understand this phenomenon by obtaining the X-ray diffraction (XRD) pattern of polycrystalline Cu films on SiO2/Si(111) and SiO2/Si(100) surfaces, as shown in Figure 2d. The XRD pattern exhibits a dominant Cu(111) phase over Cu(100) in both the SiO2/Si(111) and SiO2/Si(100) samples. This is because Cu(111) is the lowest energy Cu surface.33 Both the Cu(111) and Cu(100) crystalline phases are sharp and intense on SiO 2 /Si(111) than that on SiO 2 /Si(100) substrate, which further indicates a higher density of both the Cu crystallinities on SiO2/Si(111). Further, it is also observed that the multilayer graphene is energetically favorable to grow on Cu(111) compared to that on (100) due to its lower surface adsorption energy and lower diffusion energy.33,34 Consequently, the thin graphene films grow faster on SiO2/Si(111) than on SiO2/Si(100) surfaces. Because the

interface of Cu and SiO2/Si.28,29 (4) It is noted that the oxygen (SiO2) at the interface further dehydrogenates the CHx to form carbon radicals C*.30,31 Such complete dehydrogenation allows graphene multilayer formation at the interface. The G band mapping (Figure 2b) indicates the formation of interfacial graphene at the reaction temperature of 850 °C (see the Supporting Information Section 5). As the carbon concentration reaches a critical value,29 a series of multilayer graphene islands, 400 nm in lateral size, are nucleated and connect to each other to form a graphene grain-network in the spider-web fashion (see the Supporting Information Section 6). (5) Subsequently, as the carbon radicals continue to replenish, these graphene strings continue to expand inside the interface and consequently form a continuous film. The growth mechanism proposed here is in contrast to the formation of graphene on the top surface of the Cu, where the graphene film grows outward (see the Supporting Information Section 7). To elucidate further the role of oxygen on the interfacial graphene, a control experiment is designed to synthesize graphene on nonoxide surfaces (i.e., hexagonal boron nitride (h-BN)). As shown in the Supporting Information Section 8, the graphene is formed on h-BN substrate via diffusion of carbon radicals through Cu and nucleation at the Cu and h-BN interface. The limiting step in the proposed growth mechanism is analyzed. For graphene nucleation on the top surface of Cu via LPCVD, the growth-limiting step is the surface reaction,20 in which the surface morphology of graphene is uniform. However, the observed surface of interfacial graphene thin D


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Figure 4. Electrical transport properties of directly grown interfacial graphene on Si-based gate-dielectric substrates (SiO2/Si): (a) Conductance vs carrier concentration characteristics with inset: (left) a schematic of graphene field-effect transistor (GFET) device and (right) the optical microscopic image of the GFET. (b) Resistivity vs carrier concentration characteristics at various temperatures (10−140 K) with inset presents the charge-independent mobility (hole) as a function of temperature. (c) Normalized background conductivity vs temperature with inset shows the band structure of the graphene film, where the simple two-band (STB) model is suitable for energies near the Fermi level (EF), and as the energies are far from the EF, the dispersion curve behaves like a Dirac cone as for single-layer graphene. (d) Arrhenius model fit for GFET transport (40− 160 K) with inset of the variable range hopping (VRH) model fit for GFET transport (40−160 K).

the directly grown graphene at various temperatures (750−900 °C). It is critical to note that in these temperature ranges, the graphene film covers >90% of the substrate (see the Supporting Information Section 10). At low temperature (750 °C), a high D band intensity and the presence of the D′ band (∼1626 cm−1) indicate a reduced graphitization,39,40 as shown in Figure 3b, and the presence of high density of sp3 carbon. Owing to the endothermic dehydrogenation of CH4 reaction, as the temperature increases, the G peak becomes sharper (FWHM(G) = 20 cm−1) with the disappearance of the D′ peak, implying an increase in the crystallization of the graphene films. Such improvement of the graphene crystallization can be characterized with the in-plane crystallite size (La) via the Tuinstra and Koenig relationship41

mass transfer is an important kinetic step in the overall process, the geometric effects of the gas flow and CVD reactor geometry will play an important role in the determination of the quality of the produced graphene. Figure 3a shows a typical Raman spectrum of the directly grown graphene thin films with three prominent vibrational bands: D band (∼1350 cm−1), G band (∼1580 cm−1), and 2D band (∼2700 cm−1).35 The relative intensity of the D band over the G band (ID/IG) indicates the presence of defects in the film, which is in the range of 0.1−0.4 for a low defect and polycrystalline graphene film. Furthermore, the shape of the 2D band is important to identify the stacking of the multilayer graphene.36 As discussed above (in the SAED analysis), the stacking order of the directly grown thin graphene film is speculated to have a mixture of A−B stacking and turbostratic orientations (i.e., random orientation of the adjacent layers). Multiple areas were selected to obtain the fitting of 2D peaks with a Lorentzian curve. Further, most of the fitting obtained on the 2D peak is symmetric in shape. A representative fitting is presented in the inset of Figure 3a, which shows a single Lorentzian fit, with a full-width at half maximum (FWHM) of ∼40 cm−1. These findings suggest a dominantly disoriented stacking in the directly grown graphene.33,37,38 Reaction temperature plays an important role in CVD graphene synthesis, and Figure 3b shows the Raman spectra of

ij I yz La (nm) = (2.4 × 10−4)λ 4jjj D zzz j IG z k {

−1

(1)

where λ (nm) is the laser wavelength, La (nm) is in-plane crystallite size, and ID/IG is the intensity ratio of D and G bands. Figure 3c shows the in-plane crystallite size (La) and ID/ IG ratio with respect to the reaction temperature. The estimated La (nm) is ∼140 nm, which further illustrates that 900 °C is the optimized reaction temperature in the CVD setup. Further, at 950 °C, Cu starts to evaporate strongly, E


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ACS Applied Materials & Interfaces leading to noncontinuous and high defect density (high ID/IG) graphene films. Further, the G band downshifts (∼8 cm−1) as the reaction temperature increases from 800 to 900 °C, which can be attributed to the increase of oxygen doping during hightemperature growth at the interface of Cu and SiO2/Si substrates.42 Owing to the reduction of the ID/IG ratio, the defect density also decreases, leading to the reduction of oxygen adsorption (p-doping) on the graphene surface after the sample is unloaded from the furnace.42 It is also observed that the N2 gas in the atmosphere shows no influence on the position of the G peak.42 Further, Figure 3d shows the in-plane crystallite size (La) and ID/IG ratio with respect to the gas composition flow rate ratio of H2 and CH4 gases (FH2/FCH4) at the temperature of 850 °C (see the Supporting Information Section 10 for the Raman spectra and Raman ID/IG mappings). During the graphene CVD process, the oxidizing impurities, which arise from gas feedstock, air leakage, and Cu substrate,43 can significantly impact the growth conditions by altering the balance between growth and etching.44 The solution to this challenge is to optimize the flow rate ratio of H2 and CH4 (FH2/FCH4), which can displace these impurities (O2, H2O, CO, and CO2), hence enhancing the graphene quality.45 In the absence of hydrogen (FH2/FCH4 = 0), due to high oxidizing impurities in CH4 and air leakage, the thin graphene film can be etched or converted into oxidized graphene (sp3 carbon46), which leads to the formation of multilayer graphene patches and poor graphene crystallization (presence of D′ peak [∼1626 cm−1]) (the Supporting Information Section 10). This evidence suggests that the introduction of H2 would benefit the formation of graphene. On the contrary, if H2 exceeds a threshold value, it inhibits the adsorption of CH4, which reduces the rate of the dehydrogenation of CH4 and hence affects the crystallization of the graphene.47 Further, H2 can create point defects, which consist of hybridized sp3 C−H bonds,48 and leads to the increase in the Raman intensity (ID/ IG) in the presence of the D′ band (FH2/FCH4 = 2:1) (the Supporting Information Section 10). In this study, the optimized ratio FH2/FCH4 (1:5) corresponds to the high La value (∼90 nm). It is important to understand the electronic properties of the directly grown interfacial graphene film, which is transferred onto 300 nm SiO2 coated on Si (n++) substrate. A typical backgate graphene field-effect transistor (GFET) device was fabricated with the dimensions of 12.5 μm × 25 μm (L/W ∼ 2) by depositing Cr/Au film (15:95 nm) as the source and drain contact electrodes and with n++-doped Si as the gate source (as shown in the insets of Figure 4a). To minimize the external doping, all of the measurements were carried out under high vacuum conditions ( 40 K), which suggests an activation energy over energy gap (EA) of charge transport. To further understand this transport mechanism of GFET in the absence of back-gate voltage (VBG = 0 V), a series of I−V measurements were carried out in the temperature range (40−160 K). The transport can be elucidated by two common mechanisms: (i) the Arrhenius thermal activation model shown as ij I yz jj zz ∝ exp[−EA /2kBT ] kV {

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.8b07655. Substrate preparations (Section 1); SAED analysis of turbostratic graphene (Section 2); XPS of metal trace in directly grown graphene (Section 3); Raman spectroscopic measurement of the substrate after CVD reaction with no carbon sources (Section 4); formation of graphene at the interface of Cu and SiO2/Si(100) and of Cu and SiO2/Si(111) (Section 5); Raman mapping of the grown graphene islands (Section 6); formation of graphene on top of Cu surface (Section 7); Raman spectroscopic characterization of graphene formed at the interface of Cu and h-BN (Section 8); coverage rate at various Cu thicknesses (Section 9); effects of growth conditions on the quality of the interface graphene (Section 10); derivation of the diffusive transport equation (Section 11); field-effect mobility by derivative of the Drude formula (Section 12); electron-independent mobility vs temperature (Section 13); AFM measurement of the thickness of directly grown fewlayer graphene (Section 14); derivation of the resistivity−temperature relationship (Section 15) (PDF)

(4)

and (ii) the variable range hopping (VRH) model65,66 shown as ij I yz jj zz ∝ exp[−(To/T )α ] kV {

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Sanjay K. Behura: 0000-0001-7339-9997 Vikas Berry: 0000-0002-1102-1996 Author Contributions §

P.N. and S.K.B. contributed equally to this work.

Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS V.B. acknowledges financial support from SunEdison Semiconductor. This work made use of instruments in the Electron Microscopy Service (Research Resources Center, UIC) and Nanotechnology Core Facility of University of Illinois at Chicago.

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