NANO LETTERS
Catalyst-free Growth of Single-Crystal Silicon and Germanium Nanowires
2009 Vol. 9, No. 2 864-869
Byung-Sung Kim,†,‡ Tae-Woong Koo,†,‡ Jae-Hyun Lee,†,‡ Duk Soo Kim,‡,§ Young Chai Jung,‡,§ Sung Woo Hwang,*,‡,§ Byoung Lyong Choi,| Eun Kyung Lee,| Jong Min Kim,| and Dongmok Whang*,†,‡ SKKU AdVanced Institute of Nanotechnology, School of AdVanced Materials Science and Engineering, Sungkyunkwan UniVersity, Suwon 440-746, Korea, Research Center for Time-domain Nano-functional DeVices, Korea UniVersity, Seoul 136-701, Korea, School of Electrical Engineering, Korea UniVersity, Seoul 136-701, Korea, and Samsung AdVanced Institute of Technology, Yongin 449-712, Korea Received December 12, 2008
ABSTRACT We report metal-free synthesis of high-density single-crystal elementary semiconductor nanowires with tunable electrical conductivities and systematic diameter control with narrow size distributions. Single-crystal silicon and germanium nanowires were synthesized by nucleation on nanocrystalline seeds and subsequent one-dimensional anisotropic growth without using external catalyst. Systematic control of the diameters with tight distribution and tunable doping concentration were realized by adjusting the growth conditions, such as growth temperature and ratio of precursor partial pressures. We also demonstrated both n-type and ambipolar field effect transistors using our undoped and phosphorusdoped metal-free silicon nanowires, respectively. This growth approach offers a method to eliminate potential metal catalyst contamination and thus could serve as an important point for further developing nanowire nanoelectronic devices for applications.
Semiconductor nanowires are the focus of great scientific interest due to their wide array of potential applications in various nanoscale devices.1-4 In particular, nanowires of elementary semiconductors, such as Si and Ge, are a natural choice for the building blocks of future functional nanoscale devices because of their compatibility with existing silicon technology. So far, metal-catalyzed chemical vapor deposition (CVD) methods5 have proven to be the most successful in producing Si nanowires and Ge nanowires and their related heterostructures,6-13 as the structures, locations and electrical properties can be tailored in a wide range. One special feature of the silicon nanowire is the existence of stable oxides. Contamination of nanowire/oxide interface by heavy metals, such as gold, would eventually be considered fatal to the long-term reliability of gate oxide because of the large diffusion constants of these metals.14 Also, metal-induced deep-level defects are efficient recombination and generation centers that have detrimental effects on the behavior of most electronic and optoelectronic * To whom correspondence should be addressed. E-mail: (D.W.)
[email protected]. (S.W.H)
[email protected]. † Sungkyunkwan University. ‡ Research Center for Time-domain Nanofunctional Devices, Korea University. § School of Electrical Engineering, Korea University. | Samsung Advanced Institute of Technology. 10.1021/nl803752w CCC: $40.75 Published on Web 01/21/2009
2009 American Chemical Society
devices.15 The elementary semiconductor nanowires grown by metal-catalyzed methods have been successfully used to a wide range of high-performance devices with characteristics equal to or exceeding those of current complementary metal oxide semiconductor (CMOS) devices.16 However, the problem of metal contamination may apply to these nanowire devices, since metal impurities are unavoidable as long as metal-catalyzed growth approaches continue to be used.17,18 Much progress has been made in catalyst-free growth for compound semiconductor nanowires by various methods, including laser ablation,19 physical vapor deposition,20 chemical vapor deposition,21 vapor phase epitaxy.22-25 These catalyst-free anisotropic growths have been explained by selfcatalytic vapor-liquid-solid (VLS) mechanism,26 dislocation-driven process,21,27 oxide-assisted growth,19,28 or vaporsolid growth.25,29 On the other hand, the noncatalytic growth of elementary semiconductor nanowires have been mainly studied by the oxide-assisted growth (OAG) approach in which evaporation and deposition of oxide vapor can form crystalline nanowires with amorphous oxide shell.28,30,31 This oxide-assisted growth method produces a large amount of metal-free one-dimensional nanostructures, but the method requires high temperatures (>850 °C for the growth region). Furthermore, control of structural defects, the physical
Figure 1. (a) A typical SEM image showing high-density, uniform Si nanowires grown from a planar thin SiOx film on a silicon surface; scale bar ) 5 µm. (inset) A TEM image of the straight and uniform silicon nanowires; scale bar ) 100 nm. (b) A SEM image of Si nanowires on a silica fiber; scale bar ) 2 µm. (upper inset) A lower magnification SEM image of Si nanowires; scale bar ) 10 µm. (lower inset) An optical image of numerous nanowires grown on silica wool surfaces; scale bar ) 1 cm. (c) Lattice-resolved TEM images taken at the middle and end (lower inset) of a single-crystal Si nanowire. The arrow highlights the nanowire axis, which corresponds to the direction; scale bar ) 5 nm. (upper inset) The corresponding diffraction pattern (ED) recorded along the [111] zone axis. (d) A SEM image showing high-density, uniform Ge nanowires grown from a planar thin SiOx film on a silicon surface; scale bar ) 3 µm. (inset) A TEM image of the Ge nanowires; scale bar ) 100 nm. (e) A Lattice-resolved TEM image of a single-crystal Ge nanowire. The arrow highlights the nanowire axis, which corresponds to the direction; scale bar ) 5 nm. (inset) The corresponding diffraction pattern (ED).
dimensions and in situ doping are not as viable as in the metal-catalyzed chemical vapor deposition (CVD) method. Here, we present a novel approach to noncatalytic CVD growth of single-crystal elementary semiconductor nanowires with controlled diameters and tunable electrical conductivities. We were able to induce nucleation of nanocrystalline seeds on the reactive oxide surface without metal catalyst and subsequently achieve anisotropic growth using lowpressure chemical vapor deposition (LPCVD) process. The diameter and doping level of the nanowires were well controlled during growth, while under similar growth conditions as usual metal-catalyzed growths. We also demonstrate that field effect transistors (FETs) fabricated from our undoped and phosphorus-doped metal-free Si nanowires have ambipolar and n-type characteristics, respectively. In our typical growth process of Si nanowires, a piece of hydrogen-terminated silicon wafer was etched with ultrapure water to generate a reactive silicon-rich oxide (SiOx) layer on the substrate surface.32 Si nanowire growth was initiated on the surface at 520 °C and 15 Torr using SiH4 (10% diluted in H2) for 2 min and then the anisotropic growth of the singlecrystal nanowires was carried out at a reduced temperature Nano Lett., Vol. 9, No. 2, 2009
of 490 °C to minimize nonspecific decomposition of SiH4 on the nanowire surface for 10 min. Ge nanowires were also grown with a similar two-step growth method by the flow of a mixture of GeH4 and H2 gases. We note that the growth conditions are almost identical to that of the optimized condition for Au-catalyzed VLS growth of Si and Ge nanowires. Field emission scanning electron microscopy (FESEM) and transmission electron microscopy (TEM) images of typical as-grown Si and Ge nanowires on a planar silicon substrate show that highly dense nanowires were obtained with an aspect ratio (length/diameter) of more than 103 (Figure 1). Significantly, we were also able to grow massive amount of the Si nanowires from the large surface of quartz wool.33 Figure 1b shows optical and SEM images of the Si nanowires (∼100 mg) that were grown on the surface of quartz wool with a single run of growth inside the 2 in. furnace tube of the CVD system. No metal catalyst was observed with electron dispersive X-ray spectrometry (EDX) analysis or in the TEM images of the nanowire ends (Figure 1c), confirming that the nanowire growth was not based on metal catalyst. High-resolution TEM images and electron 865
suggested for the catalyst-free CVD growth of III-VI compound semiconductor nanowires. However, the selfcatalytic VLS mechanism should be excluded for our metalfree growth of Si and Ge nanowires since it requires multiple components in the nucleation and growth of nanowires.
Figure 2. (a) A schematic for the proposed catalyst-free Si nanowire growth model. (b) Cross-sectional TEM images of a Si crystalline seed; scale bar ) 10 nm. (inset) Lower magnification TEM image of the seeds; scale bar ) 100 nm. The silicon substrate was etched with ultrapure water at 100 °C to generate reactive oxide layer and the silicon seeds formed after reaction for 1 min at 520 °C. (c) A SEM image of metal-free Si nanowires grown on a patterned substrate; scale bar ) 10 µm. The growth substrate was photolithographically patterned using a silicon (100) wafer with a 50 nm oxide layer. The selected area was chemically etched to remove oxide layers and treated with ultrapure water at 100 °C to generate the reactive SiOx surface.
diffraction (ED) patterns of the Si and Ge nanowires show that most of the wires are single crystals growing predominantly along the and directions (Figure 1c,e). These preferred growth directions are presumably attributed to the tendency to minimize their total surface energy and have been typically observed in other Si and Ge nanowires.9,30,31 The mechanism of our metal-free growth of Si nanowires can be understood with the vapor-solid (VS) growth model (Figure 2a). When the degree of reactant supersaturation is lower than that for homogeneous deposition or for the growth of bulk crystals, the precursors are adsorbed on the reactive thin oxide surface and decomposed to form nanocrystalline seeds (Figure 2b), thus promoting anisotropic nanowire growth outward from the surface in a thermodynamically preferred direction. For the formation of nuclei, reactive surface sites are required so that the precursor can be easily deposited. We observed that high-density silicon nanowires were selectively grown on the regions covered by the reactive thin SiOx film, whereas no wires were found in the area covered with stable SiO2 (Figure 2c). The result shows that the reactive SiOx layer on the growth substrate plays a key role in the nucleation of our metal-free nanowires. This is similar to the cases of noncatalytic nucleation of InP and In(As)P nanowires24,34 assisted by thin silicon oxide surfaces, and we believe the growth of Ge nanowire can be also explained with this model though more study is needed for detailed investigation of the growth mechanism. VS growth process25 and self-catalytic VLS mechanism26 are usually 866
Optimum temperature range for growth of uniform singlecrystal nanowires was quite narrow, and the nanowires grown at higher temperature tended to be tapered and sheathed by nonspecific deposition of precursors. However, with additional flow of HCl we were able to grow single-crystal wires without amorphous shell at much higher temperature in a relatively wide temperature range. In order to investigate temperature effect in Si wire growth, growth experiments were carried out at temperatures between 620 and 660 °C with additional HCl flow while keeping the other experimental conditions constant. Uniform metal-free silicon nanowires were grown at the temperature range and the average diameter of the wires increases in proportion to an increase in growth temperature with quite narrow diameter distributions, which demonstrate that the diameter of these wires can be controlled without using predefined monodisperse metal nanoparticle catalysts (Figures 3 and 4).7 The uniform and systematically controllable diameter of nanowires is necessary for device applications, since the properties of nanowires are strongly size dependent. On the other hand, single-crystal Ge nanowires grown by the similar growth method were tapered at increased temperature (Figure 5). The difference in temperature dependence of wire shape for Ge and Si nanowires seems to attribute to surface oxidation of Si wires during the growth. It has been reported that a small amount of oxygen impurity is inevitable in conventional CVD systems and, unlike Ge nanowires, Si wires can be easily oxidized even at the very low oxygen pressure.35,36 The adsorption and accumulation of oxygen impurities on the side walls may assist the growth of uniform Si nanowires by the retardation of lateral growth, because the sticking coefficient of the precursors is extremely small on oxide surfaces at low supersaturation conditions. In addition, the growth rate of the Si nanowires (>2 µm/ min), which is much faster than that of the Ge wires (
