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Control of Multilevel Resistance in Vanadium Dioxide by Electric Field Using Hybrid Dielectrics Kaleem Abbas, Jae Seok Hwang, Garam Bae, Hongsoo Choi, and Dae Joon Kang ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.6b16424 • Publication Date (Web): 29 Mar 2017 Downloaded from http://pubs.acs.org on April 4, 2017

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ACS Applied Materials & Interfaces

Control of Multilevel Resistance in Vanadium Dioxide by Electric Field using Hybrid Dielectrics Kaleem Abbas 1, Jaeseok Hwang1, Garam Bae1, Hongsoo Choi2 and Dae Joon Kang1,* 1

Department of Physics and Energy Science, Sungkyunkwan University, 2066, Seobu-ro, Jangan-gu, Suwon 16419, Gyeoggi-do, Republic of Korea *[email protected] 2

Department of Robotics Engineering, Daegu Gyeongbuk Institute of Science and Technology (DGIST), 711-873, Daegu, Republic of Korea Keywords: vanadium dioxide, Insulator-metal transition, electric field, mott transister, hybrid dielectric.

ABSTRACT: We investigate the electric-field effect on VO2 back-gated field effect transistor (FET) devices. By using hybrid dielectric layers, we demonstrate the highest resistance 2 modulation on the order of 10 in VO2 at a positive gate bias of 80 V (1.6 MV/cm). VO2 FET devices are prepared on SiO2 substrates with different thicknesses (100 nm to 300 nm) and hybrid dielectric layers of Al2O3/SiO2 (500 nm). For thicknesses less than 300 nm, no electric-field effects are observed, while for a 300 nm thickness, a small decrease in resistance is observed under a 0.2 MV/cm electric field. Under the electrostatic effect, the carrier concentration increases in VO2 devices, decreasing the resistance and the transition temperature from 66.75°C to 64°C. The leakage analysis shows that the interface quality of VO2 films on hybrid dielectric layers can be further improved. These studies suggest a multilevel, fast resistance switching with the electric field and give an insight into the gate-source leakage current, which limits the phase transition in VO2 in an electric field.

Introduction: Correlated electrons in vanadium oxides are responsible for their extreme sensitivity to external stimuli such as tem1 2 3 perature, doping, electric field, or strain. As a result, several vanadium oxides undergo insulator-to-metal phase transition (IMT) accompanied by structural change. Of those, VO2 is particularly interesting as it exhibits an insulator-metal transition (IMT) at around 68°C, close to room temperature, along with a structural phase change, providing rich physics to explore. IMT is an alluring property of transition metal 4 oxides, that has been studied extensively for applications in 5-6 switching and logic devices, field-effect transistors 7-10 11-14 15 superconductivity, magneto(FETs), Mott transistors, 10 15-16 resistances, and ferroelectrics. The extreme sensitivity of IMT in VO2 to these stimuli presents a great opportunity for diverse applications, but makes it difficult to understand and tailor the required properties for the devices. Furthermore, the VO2 properties vary as a result of growth techniques,

growth conditions, crystal structure (whether being a single crystal or polycrystalline), and substrate effects due to varia17-29 tion in stoichiometry, stress, and strain. Controlling of the carrier density by electric field is a salient feature of transistors restricted by the "Boltzmann limit" in conventional electronics. The ultrafast IMT switching in VO2 is motivation for research on how to circumvent the 30-35 limiting issue in transistors. During IMT, the electron density increases by many orders of magnitude, enabling the materials to show exotic emergent properties. The problem of IMT in an electric field has received increasing attention in the recent time. The electric field is normally applied using ionic liquids (ILs) and solid state gate-bias geometry. Many researchers have successfully demonstrated IMT in VO2 but there exists controversy over the prevailing mechanism. ILs are used in the form of an electric double-layer capacitor (EDLC) configuration to apply a very high electric field. Using ILs, a reversible structural phase change in VO2 36 was demonstrated, while another study showed a non37 reversible IMT owing to the formation of defects. Some 38 reported no electrostatic effects in VO2 except doping. Until now, solid state gate-biasing has shown limited success 2, 21, 39-41 with very small modulations in resistance. Here, we investigated the pure electrostatic effect using a solid state back gate-bias configuration. This work is focused on understanding the pure electrostatic effects in VO2 and the limitations of this geometry for reversible and fast transitions. In this work, sol gel processed VO2 films were pre+ pared on SiO2/Si substrates with different thicknesses of the dielectric layers (100 nm to 300 nm) and hybrid dielectric layers of Al2O3/SiO2 (200 nm/300 nm) as shown in Table S1. The transport properties were measured using the Keithley 2612 system and structural characterization was performed as described in the experimental section.

Experimental Methods: Experimental VO2 thin films were prepared by using a 0.12 M solution of vanadium oxytriiosopropoxide (Sigma Aldrich). The prepared solution was stirred overnight for aging. The substrates were spin-coated at 2000 rpm for 20 s and

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then dried at 250°C for 3 min on a hotplate. The process was repeated several times to obtain a film thickness of 100 nm and the spin-coated samples were annealed in a furnace at 450°C for 30 min at a rate of 5°C/min in air. These annealed samples were then reduced to VO2 films using H2 gas or a vacuum at 500°C. The channel bars were patterned using photolithography. The VO2 thin films were etched by CF4. Ti/Au (10 nm/80 nm) electrodes were deposited using a home-made electron beam evaporator to produce twoterminal VO2 (10 × 10 µm2) devices. All current-voltage (I-V) measurements were made using the Keithley 2612 system in an ambient environment. Direct current (DC) bias was applied between the source and the drain electrodes with a compliance limit of 1 mA and bias voltage of 1 V for characterization of all the FET devices. X-ray diffraction (XRD) data were collected from the MiniFlex 300/600 system (Rigaku) at a grazing angle using a Cu Kα (λ=1.5406 Å) source. Raman measurements were made using a Renishaw inVia microRaman spectrometer with 532-nm lasers at 100% power intensity.

Results and discussion: A schematic of the electric-field effect (FE) in a twoterminal VO2 device is shown in Fig. 1. The VO2 channel devices are fabricated on the p-Si substrate with a 300-nmthick SiO2 dielectric layer. A thin film of VO2 is deposited on SiO2/Si+ substrates; the method is described in the experimental section and the characterizations are shown in Fig. 2a and b. The VO2 film is patterned as a channel layer and then etched as described in the experimental section. Ti/Au electrodes are deposited as the source and drain on the VO2 channel. First, the resistance-temperature (RT) curve of the VO2 devices is measured without any gate-bias. Change in the resistance across the transition (∆R) of the VO2 devices show an IMT on the order of 103, TIMT at 66.75°C, and the hysteresis width (TH) of 10°C. To investigate the FE in VO2, gate-biased RT measurements are taken. Figure 3a show the RT measurement from a FE-VO2 device on a 300 nm dielectric layer. When positive Vg is applied, the resistance of the VO2 device decreases. The decrease in resistance (∆R) increases with the increase in positive Vg. The applied gatebias voltage on FE-VO2 devices reached the limiting value of 5 V, after which the leakage current increased rapidly. While applying a negative Vg, a slight increase in resistance was observed. The Vg applied on 300 nm FE-VO2 was limited by the leakage current through the gate source. In order to apply a higher gate-bias voltage while minimizing leakage, an additional dielectric layer of Al2O3 (200 nm) is deposited on a SiO2 (300 nm)/Si+ substrate as shown in Figure S1. Al2O3 has an additional benefit of having better VO2 crystal quality than SiO2. FE-VO2 devices of the same configurations are made. Figure 3b shows the RT measurement of FE-VO2 devices on a 500 nm dielectric layer at different positive Vg values. At a positive Vg, the resistance of the VO2 channel decreases. With increased dielectric layer thickness (i.e. 500 nm), up to Vg = 80 V was applied compared to Vg = 5 V on a 300 nm dielectric layer, which shows a decrease in the resistance on the order of 102 in the VO2 device. The leakage current remained small compared to the source and drain. When a negative Vg is applied, resistance in the FE-VO2 devices increases linearly with increasing negative Vg. At Vg = -5 V, the VO2 channel resistance increases.

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The decreases in resistance of the VO2 channel show an ntype behavior. When a positive Vg is applied, it induces charge carriers in the channel layer, which increase the electronic conductivity and reduce the resistance. The increase in conductivity with the positive gate is ascribed to an electrostatic effect. The electric field exerts an external strain on 25 the monoclinic phase of VO2. This external force caused by strain provides energy for the dimerization of V ions, which is a concomitant process for the movement of oxygen ions, as 13, 42-45 indicated in Fig. 1c. These shifts of ions tend to delocalize the localized electrons in the monoclinic phase (insulating). As Vg increases, more electrons are liberated, causing an increase in electron concentration and hence increasing the conductivity of the FE-VO2 device. At negative Vg, the electric field tightly binds the electrons and minimizes their movement in a similar manner to that of the phenomena of the depletion mode, thus increasing the resistance in the FEVO2 device. The VO2 devices switch to their pristine resistance state instantly when gate-bias is turned off. The swift switching of VO2 to its pristine state shows no voltage dependent hysteresis at 20°C. The electronic induction originates from delocalization mechanism instead of formation of oxygen vacancies. The oxygen vacancies are stable and VO2 can only be recovered by reverse gate-bias. Fig. 3c and d show TIMT of the FE-VO2 device estimated from the dR/dT curves. TIMT of VO2 depends upon the electron concentration. As electronic concentration increases, TIMT decreases. TIMT decreases from 66.75°C to 64°C with Vg = 0 V to 80 V, respectively, and narrows the hysteresis width. The resistance modulation in the FE-VO2 device under Vg is similar to enhancement and depletion modes. The enhancement of the induced carrier is similar to the doping effect in VO2, which reduces the transition temperature. However, no change in the transition temperature is observed in the depletion mode because the depletion of electrons is not enough to increase the TIMT compared to that of the enhancement mode. Figures 4a and b show the change in resistance (∆R) as a function of the electric field for FE-VO2 devices with different dielectric layer thicknesses. For an FET-VO2 device with a 500-nm-thick dielectric layer, the ∆R is initially small and then increases with the electric field. It saturates at 0.4 MV/cm and increases slowly up to 1.6 MV/cm. For a reverse electric field, ∆R is initially small but attains a steady value. We note that the resistance change is up to 90%. A similar graph is obtained for FET-VO2 with a 300-nm-thick dielectric layer. Both graphs show enhancement effects in VO2 and the absence of IMT in FE-VO2. This is because the applied electric field is much smaller than the electric field applied by electric double layer transistor (EDLT) IL gating in VO2. In ILs, the applied electric field is greater than 10 MV/cm. As shown in Fig. 5, the dielectric layers of 300 nm and 500 nm thickness are used for leakage analysis. The leakage current of the dielectric layers before the VO2 coatings are applied, is shown in Fig. 5a. The leakage current remains small when the gate-bias voltage is applied and suffers no appreciable degradation upon repeated cycles. After VO2 coating and fabrication of the FET devices, the leakage current in the 300 nm dielectric layer rapidly increases with increasing Vg and upon repeated cycles, the quality of the dielectric layer degrades continuously as in Fig 5b. In the 500-nm thick hybrid dielectric layer, leakage current remains small but in-


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creases slightly with the increase of Vg in repeated cycles as shown in Fig 5c. These results confirm that leakage through the dielectric layer is the main limiting parameter in VO2 FET applications. Figure 4c shows the dielectric thickness vs. the maximum Vg that was applied in FE-VO2 devices. The transport properties of the FE-VO2 devices show that the limitation is in the suitable dielectric material. The properties of the dielectric materials degrade when coated with VO2, irrespective of the methods used. Leakage analysis is performed on the FET VO2 of different dielectric layer thickness.

Conclusion: In summary, we demonstrated the FE on VO2 as back-gate devices. Our results showed that when a 1.6 MV/cm electric field is applied to a hybrid dielectric layer, the VO2 resistance decreases by an order of 102, which causes a 3°C decrease in the transition temperature of VO2. The change in the resistance and transition temperature of VO2 using solid backgate geometry is the highest among the reported values, to the best of our knowledge. We also find that current leakage limits the applied electric field and hinders the IMT in VO2 using solid-state gate effects.

AUTHOR INFORMATION Corresponding Author *Dae Joon Kang, *[email protected] Department of Physics, Sungkyunkwan University, 2066, Seobu-ro, Jangan-gu, Suwon 16419, Gyeonggi-do, Republic of Korea

Notes The authors declare no competing financial interests.

ACKNOWLEDGMENT This work was supported by the Center for BioNano HealthGuard, funded through the Ministry of Science, ICT and Future Planning (MSIP) of Korea as a Global Frontier Project (HGUARD_2013M3A6B2), and a National Research Foundation of Korea grant funded by Korean government (NRF-2014R1A2A1A11052965). HSC would also like to acknowledge the financial support provided by the Korean Evaluation Institute of Industrial Technology (KEIT) funded by the ministry of Trade, Industry & Energy (MOTIE) (NO. 10052980).

Supporting Information The supproting information is available on ACS Publication website. The SEM crossectional image of hybrid dielectric layer as Figure S1; the summary of VO2 devices fabricated on different dielectric layer thickness are given in the Table S1

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Table of figures Figure 1| Schematic and optical images of the VO2 gate bias devices is shown. a) Schematic of the FE-VO2 back-gate device. b) 2 Optical micrograph of the 10 × 10 µm VO2 devices with Ti/Au electrodes. c) Schematic of monoclinic phase of the VO2 unit cell under gate-bias is shown. With positive gate voltage, the electric field exerts stress on the V-V ions which move to minimize the energy. This movement of V-V ions also causes the shift of O-ions, which loose bound electrons that increase the conductivity of the VO2. With increase in the gate voltage movement of ions under bias tends to dimerize, and delocalization of localized bound electrons is shown. Figure 2 | X-ray diffraction patterns and Raman spectra of the VO2 thin film. a)The XRD peaks show the monoclinic phase of VO2. The (100), (011), (-202), and (-211) diffraction peaks and (002) plane of VO2 are identified at the 2θ values of 18.36°, 27.90°, 36.98°, 37.10°, and 39.94°, respectively. The characteristic monoclinic peak of (011) at 27.90° corresponds to the M1 phase and belongs to the P21/c space group. Diffraction patterns are matched with JCPDF2 (03-065-2358). XRD analysis was performed on the Rigaku Miniflex 300/600 with Cu Kα (1.5406 Å). b)The Raman spectra in VO2 thin film are taken using a 532 nm laser at 100% power. The sharp peaks correspond to the crystal nature of the film. The Raman active modes are observed at 142, 194, 227, -1 -1 -1 310, 393, 491, and 617 cm . The peaks at 194 cm and 227 cm-1 correspond to the V-V pairing and tilting modes and 617cm the VO vibrations. These are characteristic Raman peaks for the VO2 monoclinic phase. The symmetry of all these modes (Ag) is same and all modes are shifted slightly toward higher frequencies because of oxygen excess or of surface stoichiometry. Figure 3| Resistance vs. temperature measurement and dR/dT curves of the VO2 devices on a 300 nm and hybrid dielectric layer of 500 nm. a) The gate-bias dependent RT measurement of the 300 nm dielectric (SiO2) layer is shown. A small change in resistance is observed as gate-bias change from Vg = -3 V to 6 V. b) the gate-biased RT measurement of the VO2 on hybrid dielec2 tric layer (Al2O3 (200 nm)/ SiO2 (300 nm)) is shown. VO2 devices show the decrease of resistance on the positive gate-bias of 10 orders at Vg = 80 V. c and d) The dR/dT curves of the VO2 devices on SiO2 300 nm and hybrid dielectric layer of Al2O3/SiO2 200 nm/300 nm. The dR/dT curves decreases with positive gate voltage and hysteresis curves narrows. While on negative gate voltage, dR/dT curves increases. The dR/dT curves peaks of VO2 on hybrid dielectric layer shifts from 66.75°C to 64°C, showing a decrease in transition temperature. Figure 4 | Electric field vs. resistance graph of a VO2 device on 300-nm and 500-nm thick dielectric layers and the gate bias voltage vs. dielectric layer thickness in VO2 devices: a and b) The electric field-induced electronic phase transition in a FE-VO2 device on SiO2 300 nm and hybrid dielectric layer of Al2O3/SiO2 (200 nm/ 300 nm) of 500 nm respectively. The change in re-

∆R = R ± − R

(1)

∆R × 100 R

(2)

∆R% =

sistance (∆R) is calculated by equation 1 and 2, are plotted verses the electric field. The FE-VO2 devices shows n-type behavior and electrons are induced when a positive electric field is applied. The magnitude of the applied electric field is eight times higher with hybrid dielectric layer compared with 300 nm SiO2 layer. There is a nonlinear increase, without any jump in conductivity. This suggests that only an electronic transition has occurred. The low value of the electric field rules out any space charge effect in the FE-VO2 devices. c) The graph shows that the gate-bias voltage depends upon the dielectric thickness. The dielectric properties of the SiO2 material degrade with VO2. In SiO2 thicknesses below 300 nm, leakage is dominant and we cannot observe any gate biasing effect. Figure 5| Leakage current (Ig) analysis in gate-biased VO2 devices on 300 nm and 500 nm dielectric layers. a) The leakage current in the bare substrate before VO2 film coating. b) A leakage current (Ig) in the FE-VO2 device on 300 nm dielectric layer. The leakage rapidly increases with gate-bias and repetition of measurements (cycles). c) The leakage current (Ig) in FE-VO2 devices on hybrid dielectric layer of 500 nm thickness. The Ig values remain small and slightly increase with every cycle. The IV measurements were taken by Keithley 2612 system. The sweeping gate bias is assigned to the source meter from 0V to 80V to measure the IV characteristics. The system never settles at 0V instead it shows a nontrivial voltage. Moreover, the system has sensitivity of nA range.


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Figure 1


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Figure 2


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Figure 3


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Figure 4


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Figure 5


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