Controllable Switching Filaments Prepared via Tunable and Well

Nov 28, 2017 - The filament is formed with a confined vertical nanoscale gap by using a well-defined single vertical truncated conical nanopore (StcNP...
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Cite This: Nano Lett. XXXX, XXX, XXX−XXX

Controllable Switching Filaments Prepared via Tunable and WellDefined Single Truncated Conical Nanopore Structures for Fast and Scalable SiOx Memory Soonbang Kwon,† Seonghoon Jang,† Jae-Wan Choi,† Sanghyeon Choi,† Suk-Jae Jang,‡ Tae-Wook Kim,*,‡ and Gunuk Wang*,† †

KU-KIST Graduate School of Converging Science and Technology, Korea University, 145, Anam-ro, Seongbuk-gu, Seoul 02841, Republic of Korea ‡ Applied Quantum Composites Research, Institute of Advanced Composite Materials, Korea Institute of Science and Technology, San 101 Eunha-ri, Bongdong-eup, Wanju-gun, Jeollabuk-do 55324, Republic of Korea S Supporting Information *

ABSTRACT: The controllability of switching conductive filaments is one of the central issues in the development of reliable metal-oxide resistive memory because the random dynamic nature and formation of the filaments pose an obstacle to desirable switching performance. Here, we introduce a simple and novel approach to control and form a single silicon nanocrystal (Si-NC) filament for use in SiOx memory devices. The filament is formed with a confined vertical nanoscale gap by using a well-defined single vertical truncated conical nanopore (StcNP) structure. The physical dimensions of the Si-NC filaments such as number, size, and length, which have a significant influence on the switching properties, can be simply engineered by the breakdown of an Au wire through different StcNP structures. In particular, we demonstrate that the designed SiOx memory junction with a StcNP of pore depth of ∼75 nm and a bottom diameter of ∼10 nm exhibited a switching speed of up to 6 ns for both set and reset process, significantly faster than reported SiOx memory devices. The device also exhibited a high ON−OFF ratio, multistate storage ability, acceptable endurance, and retention stability. The influence of the physical dimensions of the StcNP on the switching features is discussed based on the simulated temperature profiles of the Au wire and the nanogap size generated inside the StcNP structure during electromigration. KEYWORDS: Switching conductive filament, single nanopore structure, breakdown process, resistive memory, SiOx nanoscale conductive filaments, whose formation/annihilation can be controlled by the redox-,8−10 thermal-,11,12 or electricfield domination13,14 principle. Although the nanoscale conductive filaments could potentially overcome the scaling challenges of Si-based flash memory,2−4 their stochastic and unpredictable formation result in device variability15,16 and significant degradation of the switching performance17,18 or device failure under repeated electrical stimulation.17,18 Therefore, the control of the switching filament formation and dynamics is necessary for the practical application of resistive

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wo-terminal resistive memory has risen rapidly as a strong candidate for future nonvolatile random access memory applications because of the nanoscale conductive filaments, nanosecond switching, simple fabrication process, and low energy consumption.1−6 Generally, resistive memory consists of a metal oxide material sandwiched between two conductors and can be switched between two distinct resistance states (a high resistance state (HRS) and low resistance state (LRS)) under electrical control.1,4,7 Because of the simplicity of the device structure and the presence of various oxide materials with different crystallographic phases, the field of resistive memory using oxide-based materials has significantly advanced in the last two decades.1−7 The switching effects in oxide-based resistive memory are believed to originate from the presence of © XXXX American Chemical Society

Received: August 6, 2017 Revised: November 14, 2017

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DOI: 10.1021/acs.nanolett.7b03373 Nano Lett. XXXX, XXX, XXX−XXX

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Figure 1. Fabrication of the StcNP SiOx memory. (a−d) Schematic diagrams of the fabrication process for a StcNP SiOx memory device where a switching filament has not yet formed. (a) The microscale (diameter = 1.5 μm) circular Au patch was patterned by photolithography on a SiOx/Pt/ Ta substrate. (b) In a programmable oven, the dewetting process was carried out at 1050 °C with a 1 h ramp-up time to create a set size of agglomerated Au NP and a surrounding SiOx ridge. (c) The formation of a StcNP structure during the continuous heating at 1050 °C, and the Au NP reaching the base Pt/Ta layer after a set heating time. (d) Deposition of a circularly patterned top Au layer on the StcNP structure to form a vertical Au wire. (e) SEM images of the top view of the completed StcNP SiOx memory device (left and lower right) and the nanopore (upper right). The radius of the devices is 100 μm. (f) Structure of a StcNP investigated in noncontact AFM scanning mode. The corresponding pore diameter (dp) decreased at a fixed rate as the pore depth (pd) increased, resulting in the formation of a truncated conical nanopore structure. The inset shows the AFM image at the entrance of the StcNP structure. (g) Pore depth dp as a function of heating time. The inset shows the schematic drawings of StcNP with short (left) and long (right) pd, respectively.

precise control of Si-NC filaments and their formation at desirable locations have not achieved so far. Recently, randomly distributed multiple nanoporous (MNP) SiOx (number of pores ≫1000), formed by an anodizing process, has been fabricated and demonstrated to be a suitable device structure for SiOx memory.31 In this structure, the Si-NC switching filaments are confined to the internal MNP SiOx structure by electromigration, which enables the use of a significantly reduced electroforming voltage and shows potential for desirable and essential switching features. However, this junction structure has a large number of different pore sizes and shapes, even in a single memory cell; thus, randomly distributed and multiple conductive filaments cannot be avoided, which result in device instability and the frequent switching failure. Furthermore, it is difficult to apply this anodizing solution process to wafer-scale production with uniformly well-defined nanoscale pores, resulting in high device variability. In this sense, the main challenges are both to fabricate well-defined single nanopore SiOx by a complementary metal-oxide−semiconductor (CMOS)-compatible process and to form a controlled single nanoscale conductive filament that has desirable switching features for scalable memory devices. In this report, we engineered the number, size, and length of conductive filaments using a well-defined vertical single truncated conical nanopore (StcNP) SiOx structure and utilized them as a reliable two-terminal SiOx memory platform. The StcNP technique, which is based on a simple CMOScompatible manufacturing process, can uniformly form single conductive Si-NC filament of each SiOx memory cell by a

memory technology. Efforts to alleviate the random and nonuniform filament formations have resulted in various approaches including interfacial engineering,19 thermally agglomerated filament formation,20 modulation of the crystallographic structure,21 and incorporation of functional materials such as self-assembled nanoinsulators,22 metal nanoparticles,23 or metal layers.24 However, simultaneously improving the switching features and forming a uniform nanoscale filament at a specified location in a device remains challenging. Since the resistive switching phenomenon of SiOx (x ∼ 2) was first demonstrated,25 various device platforms for investigating its switching behaviors have been suggested.5,24,26−32 SiOx-based memory shows a nonvolatile unipolar switching behavior, which is attributed to the growth and shrinkage of the semimetallic Si nanocrystals (Si-NC) in the SiOx matrix in response to different electrical stimuli.5,27,29 However, this process requires relatively high electroforming voltages (>20 V) and repeatable current−voltage (I−V) sweeps to form the conductive filaments composed of a Si phase at the exposed SiOx edges, which could result in ill-defined numbers and locations of the switching filaments, as well as their nonuniform sizes and lengths.24,27 In addition, the filaments formed at the exposed SiOx edges are not suitable for modern embedded electronic memory architectures because the subsequent processes, such as passivation, can severely affect the exposed filaments. To address these issues, many approaches including stoichiometry control,32 thermal annealing,27 the insertion of thin metal layers,23 and the structural engineering of SiOx31 have been suggested; however, the B

DOI: 10.1021/acs.nanolett.7b03373 Nano Lett. XXXX, XXX, XXX−XXX

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Figure 2. Switching characteristics of the StcNP SiOx memory (|pd| = ∼75 nm). (a) Electroforming (breakdown) process of a StcNP SiOx memory device by electromigration. The breakdown voltage, Vb, is defined at the voltage position where the current abruptly drops. The inset shows the schematic illustrations for the devices before (left) and after (right) the breakage of the Au wire and the nanogap formed after breakage. (b) Statistical histogram of Vb for the 18 different StcNP SiOx memories. The normal distribution curve can be fitted by a Gaussian function. (c) The representative I−V characteristics of the StcNP SiOx memory. The inset represents the switching region in the nanogap, where the phase transition between Si-NC (ON) and α-Si (OFF), depending on the magnitude of the applied voltage, occurs. At the Vread = 1.0 V, a ∼107 ON−OFF ratio was obtained. The corresponding operating voltage regime for Vset and Vreset started at 4 and 9 V, respectively. (d) Multilevel switching properties of the StcNP SiOx memory device according to the magnitude of applied voltage (from 5 to 15 V). Six multistates were found. (e,f) Retention (104 s) and endurance cycling tests (103 times) of the StcNP SiOx memory. Vread = 1.0 V, Vset = 5 V, and Vreset = 16 V with a pulse duration of 500 μs. (g) Switching speed test for the StcNP SiOx memory. The vertical red (blue) arrow indicates the direction of transition of the set (reset) process. The set and reset processes are completed in a time of 6 ns at 5 and 16 V, respectively. The rising and falling edge of the pulses were 2.8 ns. Note that the actual pulse applied to the device is shown in the Supporting Information (Figure S15).

substrate patterned by conventional photolithography were heated in the ambient air for a set time at 1050 °C with a 1 h ramp-up time using a programmable oven. Note that the active SiOx layer was deposited by e-beam evaporation under a pressure of 10−6 Torr and a deposition rate of 0.5 Å/s. During the initial dewetting process, the patterned Au patch often agglomerated to form Au nanoparticles (Au-NP) with diameters (dp) of 120−180 nm surrounded by a soaring rim of SiOx (Figure 1a,b). In fact, the formation of a ridge surrounding the metal NP on the ceramic layer is commonly observed when the annealing temperature reaches approximately half of the ceramic melting point (e.g., for SiO2, Tm = 1600 °C).36 This is because the ceramic can migrate along the interface of the metal NP via surface diffusion toward the air/ metal/ceramic triple line where the metal NP is located.36−39 Under continuous heating at 1050 °C, the Au NP further penetrated the SiOx while its size decreased with heating time because of the thermal evaporation of Au, leaving a StcNP structure that is connected to the wall of the SiOx layer. After some time, the Au NP finally reached the bottom of the Pt/Ta layer (Figure 1c). The direction of the StcNP is normal to the SiOx surface and abruptly narrows downward (Figure 1c). Note that it has been reported that the SiOx encircling the StcNP maintains its original amorphous oxide phase.36 Consequently, to form an Au wire through the vertical StcNP, a patterned top layer of Au was deposited by an electron-beam evaporator (Figure 1d). The vertical connections of the Au wire between both electrodes were confirmed from the electrical short circuit

simplified electroforming process through a single internal vertical nanopore. We demonstrate that the essential switching elements such as the stability, the switching speed, and the switching failure are significantly influenced by the physical dimensions of the StcNP structures. In particular, a SiOx memory device fabricated from the StcNP structure with a pore depth of 75 nm showed switching speeds as fast as 6 ns, which other SiOx devices have not yet achieved, while sustaining other critical switching performance factors such as a high ON−OFF ratio, multilevel storage ability, and acceptable endurance and retention stability. We have developed a comprehensive explanation of the switching features depending on the physical dimensions of the StcNP based on the simulated temperature profiles in an electrically stressed nanoscale Au wire during electromigration. Versatile methods for creating nanoscale pore structures using ion-beam33 or electron-beam sculpting34 and a metal− organic framework35 have been proposed; however, in many cases they are costly, labor-intensive, and have a lowthroughput. Consequently, it is difficult to satisfy the manufacturing demands for a high-density robust nonvolatile SiOx memory. Here, we used the CMOS-compatible, simple nanopore technique to manufacture a single solid-state nanoscale pore inside the SiO2 layer, which has recently been suggested as a nanometric tool by De Vreede et al.36 Figure 1a−d shows schematic diagrams for the fabrication process for a StcNP SiOx memory device. Microscale circular Au patches (1.5 μm diameter and 18 nm thickness) on a SiOx/Pt/Ta C

DOI: 10.1021/acs.nanolett.7b03373 Nano Lett. XXXX, XXX, XXX−XXX

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devices) fitted by a Gaussian function. The Vb was found to be 4.03 ± 0.22 V, slightly higher than that of the MNP SiOx memory (1.6 V) but with half the deviation (±0.22 for StcNP and ±0.4 for MNP).31 The higher Vb might be attributed to the relatively large size of the Au wire, different wire structures, or the resistance increase at the bottom of the Pt/Ta electrode after heat treatment (Figure S4). The potential reason for the reduced deviation in Vb is presumably the relatively uniform size of the Au wire for each StcNP SiOx memory cell. Thus, each cell experiences similar electromigration processes, resulting in the formation of a narrow size distribution of nanoscale gaps. After the electromigration had completed, the StcNP SiOx memory exhibited typical unipolar switching behavior with a high ON-OFF ratio >107. Note that, however, in case of other metal-oxide materials it is not possible to obtain similar switching behaviors using nanopore structures because the SiOx region is nonexistent.41,42 Furthermore, in the exposed sub-10 nm region, the metal-oxide (HfOx, Al2O3−x, TiOx, and Ta2O5−x) devices frequently revealed a hard breakdown after a few voltage sweeps due to the relatively short conducting path or the thickened oxygen vacancy region (Figure S5). As mentioned above, the switching of the StcNP SiOx memory mainly originates from the phase transition between the Si-NC and amorphous Si phases, which is influenced by the competition between the electric field and thermal effects (Joule heating) depending on the applied voltage and current intensity (Figure 2c).5 As shown in the hysteresis curves, the current suddenly jumped at ∼4 V, indicating the threshold voltage (defining the set voltage, Vset) that can switch the device to an ON state (LRS) from an OFF state (HRS). The current then dropped and fluctuated at ∼9 V, indicating the reset voltage (Vreset) where the device can be returned to the OFF state. According to the magnitude of the programmed voltage, which changed from 5 to 15 V with ΔV = 2 V, the resistance at 1.0 V (Vread) increased steplike from 1.01 × 105 to 2.63 × 1011 Ω, exhibiting six states; thus, the device has the potential for use as high capacity nonvolatile memory (Figure 2d). Higher applied voltages increased the degree of the shrinkage of the SiNC phase by amorphization,43 resulting in an increase in the resistance.31 For the same reason, the Vset could be shifted to higher voltages as the Vreset was increased (Figure 2d). To evaluate the nonvolatile switching reliability, we investigated the retention and the cycling endurance for the StcNP SiOx memory (|pd| = ∼75 nm). As shown in Figure 2e, the currents were acquired at 1.0 V for 104 s with a time interval (Δt) of 1 s after applying a single set (5.0 V) or reset (16 V) pulse of 500 μs. The devices sustained the switching currents corresponding to ON and OFF states well, having an ∼105 ratio for 104 s. However, the ON−OFF ratio fluctuated slightly and degraded to ∼103 ratio after the 103-cycle endurance tests (Figure 2e). Although the switching endurance requires further optimization and improvement for robust nonvolatile memory applications, these evaluations provide a framework for further research on the StcNP SiOx memory and insight into the design of the nanopore structure. Generally, the switching speed is determined by how fast the conductive filament can be bridged or broken in the active oxide layer between both electrodes under electrical stimulation.44 Diverse approaches including the use of oxygen-rich and oxygen-deficient double layer structures3,45 and Cu−SiO2 core−shell nanowires46 have been proposed to enhance the switching speed. Until now, the minimum programming pulse width for typical SiOx memory has been reported to be ∼50 ns

in the low bias regime. (Figure S1). Figure 1e shows the scanning electron microscopy (SEM) images of the top view of the StcNP structure (upper right) and the completed SiOx memory device (left and lower right). Figure 1f shows the geometrical parameters of a formed StcNP structure that was characterized by atomic force microscopy (AFM, Park NX10, Park systems). As shown in Figure 1f, there is an inverse relationship between dp and the pore depth (pd). At pd = ∼−75 nm, the diameter of the bottom of the StcNP structure was reduced to around ∼10 nm. Note that the AFM investigation of the nanoscale pores can slightly distort the pd and the dp because the image was obtained in noncontact AFM scanning mode. In fact, to obtain accurate geometric information concerning the StcNP structure itself cross-sectional transmission electron microscopy (TEM) analysis is required.36 Nevertheless, the AFM investigation is sufficient to understand the relationship between pd and dp as a function of heating time and to obtain their approximate values (Figure 1g), which yield meaningful information for the design of StcNP structures. When the heating time was increased, a gradual increase in pd was observed (Figure 1g), a trend previously reported in the literature.36 Note that the variation in the diameters of the AuNP results in a standard deviation of the pd of the StcNP, and a larger volume of the Au-NP can lead to a relatively shorter pore depth for the same heating time. From the experimental results, we expected to be able to engineer the switching filament size because the different StcNP structures allow the fabrication of Au wires with different lengths and sizes. We note here that the initial large size of the patterned Au patch on the SiOx surface (∼6 μm diameter) allows the formation of several nanopore structures because of the presence of several grain boundaries that separately aggregated during the dewetting process (Figure S2).38,40 To form a restricted Si-NC conductive filament in the StcNP structure (|pd| = 75 nm), we carried out the initial breakdown of the Au wire using a single I−V sweep, as shown in Figure 2a, until the current dropped suddenly (the so-called electromigration process). A similar physical breakdown in planar-type SiOx memory composed of a patterned conductive wire such as carbon nanotubes (CNT), graphene, carbon, or metal on SiOx substrates has been observed previously.5,26−30 The formation of Si-NC filament through the nanoscale gap after breakdown has been previously demonstrated from real-time images obtained by in situ TEM5 and from the electroluminescence (EL) spectra profiles,29 which are dependent on the size of the formed Si-NCs. During the electromigration of the conductive wire, the underlying SiOx experiences an intrinsic postbreakdown and high electric field at the nanogap generated by junction breakdown, resulting in the energetically viable redox transformation from the SiOx to Si phase.5,27,29,31 The electromigration of the Au wire through the nanoscale pore at a low breaking voltage and single I−V sweep is expected to contribute to reducing the uncertainty in the stochastic formation of the Si-NC filament, preventing the hard breakdown of the SiOx layer and localizing the filament in the nanogap. In fact, the breakdown voltage (Vb) depicted in Figure 2a can be regarded as the electroforming voltage. Note that the initial breakdown feature of the Au wire and Vb are not dependent on the voltage polarity (Figure S3) because electromigration in electrically stressed nanoscale Au wires significantly depends on the extent of Joule heating, that is, electromigration is heat dependent. Figure 2b shows the statistical histogram of Vb for StcNP SiOx memory devices (18 D

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Figure 3. Switching characteristics of the different types of StcNP SiOx memory. (a) A plot of Vb as a function of different pd and number of Au wires in a device. The error bars represent the standard deviation of each StcNP SiOx memory device (total # of working devices = 55. Note that pd (#) represents the StcNP SiOx memory having a certain number (#) of Au wires (or pores) of diameter pd. The inset shows the AFM image of 10 pores with |pd| = ∼75 nm in a device. (b) The representative I−V characteristics of the StcNP SiOx memory devices corresponding to 25 (1), 75 (10), and 75 (100) devices. (c) A plot of the ON−OFF ratios for 25 (1), 75 (1), 75 (10), and 75 (100) devices, respectively. (d) Endurance cycling test of the 25 (1) device for 103 cycles. Vread = 1.0 V, Vset = 5 V, and Vreset = 16 V with a pulse duration of 500 μs. (g) Switching speed tests for the StcNP SiOx memory. The vertical red arrow indicates the direction of transition of the set process. The vertical black and blue arrows indicate the direction of transition for the reset process. The set process was completed at a pulse width of 2 μs at 5 V but the completed reset process required two pulses consisting of 2 μs at 16 V. The rising and falling edge of the pulses were 100 ns.

for both set and reset processes.24,27,28,31 In the case of our StcNP SiOx memory device, the minimum pulse-widths for complete ON and OFF states were both found to be up to 6 ns at 5 and 16 V, respectively, as shown in Figure 2f. We further confirmed that the switching operation occurred at the switching speeds of 10 and 20 ns for both states (Figure S6). Note that the high electric field attained at very small nanogaps may cause fast switching by the rapid phase transition between Si-NC and α-Si in the filament, which will be discussed further in the following section. The switching speed measurements are described in Methods in detail. To investigate the switching properties depending on the physical dimensions and the number of Au wires (or pores) in a device, we designed and fabricated StcNP SiOx memory devices having different pd (25 or 75 nm) and different numbers of Au wires (1, 10, and 100). To classify the fabricated devices, we denoted them as “pd (#),” that is, a StcNP SiOx memory having a certain number (#) of Au wires of length pd. We assumed that the length and the number of Au wires are identical to pd and the number of pores, respectively. For example, “25 (1)” means that the device has a single Au wire of |pd| = ∼25 nm, and “75 (100)” means 100 Au wires of |pd| = ∼75 nm in a device (Figure 3a). As shown in Figure 3a, the initial Vb for 25 (1) was slightly higher than that of 75 (1). The different Vb values originate from the different wire sizes that are dependent on the pd (Figure 1g and Figure S7) because a larger Au wire requires a higher breaking voltage during electromigration.47−49 However, the Vb values for the devices of |pd| = 75 nm are similar, regardless of the number of Au wires (# = 1, 10, and 100) in a device (Figure 3a). This result indicates that Vb is

almost independent of the number of Au wires that are connected in parallel between the top and bottom electrodes. In the case of the 25 (1) devices, most (∼69%, 11/16 devices) failed to switch after the breakdown process, and few (∼31%, 5/16 devices) showed the desired unipolar switching features, as shown in Figure 3b,c. In contrast, for the 75 (1), 75 (10), and 75 (100) memory devices most (92%, 46/50 devices) exhibited typical unipolar switching behaviors with similar ON−OFF ratios, and few failed at the initial I−V sweep, as shown in Figures 2 and 3b,c. When the number of Au wires in the device was increased from 1 to 100, however, there is a high possibility that multiple Si-NC filaments may form in the StcNP structures where Au wires were connected after electromigration. Therefore, those devices could suffer similar issues to MNP SiOx memory, such as the switching instability induced by the potential variation in nanogap sizes or switching filaments.31 For example, even if there exists only one vulnerable switching path among the many Si-NCs in a device, it is highly likely that the device will become stuck in an ONstate, even after a few hundred cycles (Figure S8). As shown in Figure 3d,e, the 25 (1) memory device exhibited higher fluctuation between the switching states over 103 cycles and much slower switching speeds, ∼2−4 μs for programming, compared to the 75 (1) device (Figure 2g). The switching failure and the performance degradation for the 25 (1) device might be associated with the generation of a relatively large gap after electromigration. This could reduce the possibility of Si phase transition because of the lower electric field at the same programming voltage and thus increase in the uncertainty of the Si-NC formation. In addition, there is a possibility for the E

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Figure 4. Geometry estimation of a truncated conical Au wire and the simulated temperature profile of an Au wire during electromigration. (a) Schematic illustration of a truncated conical Au wire formed through the StcNP structure. pd is the length of Au wire, and dp(pd) and rp(pd) are the diameter and the radius of the Au wire according to pd. The ratio of pore contraction, d(dp (p))/dp = −2.22. (b) Contour plots of the correlation between dp and pd as a function of heating time, which was roughly estimated from the experimental geometric parameters of the StcNP structures (Figure 1f,g). The linear relationship between dp and pd based on the assumption of the constant ratio of pore contraction is shown in the inset. dp(pd) < 0 indicates the nonphysical region, and dp(pd) > 0 indicates the physical region where all fabricated StcNP structures are located. (c) Semilog plots of the estimated Jb as a function of rp for the StcNP SiOx memories with |pd| = ∼75 and ∼25 nm, respectively. The corresponding breakdown currents (Ib) are experimental average values. (d,e) Simulated temperature profiles on the Au wire of |pd| = 75 nm and |pd| = 25 nm during electromigration.

report that used a thermally grown SiO2/Si substrate.36 Note that a higher ratio of pore contraction indicates that the pore diameter rapidly decreases at the same pd. We speculate that this ratio could be influenced by the stoichiometry, the morphology, and the phase of SiOx, which might result in different interface energies between the Au NPs and the SiOx.36,39,40 The ratio can also be changed by the temperature programming,36 as well as the annealing apparatus. To estimate the pore diameter−heating time dependence, we performed the polynomial fitting of Figure 1g and found a rough geometric correlation between dp and pd as a function of heating time, as shown in the contour plot of Figure 4b. These estimated correlations provide the physical dimensions of the StcNP structure that can be tuned by temperature programming, which offers some guidelines for the design of the vertical Au wires. Note that for simplicity we ignored the possibility of a change in the ratio of pore contraction when the size of the Au NPs decreased under heating at 1050 °C. To investigate the different breakdown behavior with different Au wire geometries, we employed a simple 2D thermal model for Joule heating and heat dissipation from the Au wire on the SiO2 substrate that carries the current along the x-axis between two semi-infinite heatsinks.49 This is described by the following heat transfer equation

25 (1) device to break itself during the repeated switching operation due to its thin SiOx layer, causing switching failure (Figure S9). Similarly, in cases of the planar Au wires on a SiO2 substrate, we found that there were different nanogap sizes after electromigration depending on the physical dimensions of the Au wires (Figure S10). All I−V characteristics and the electromigration for each StcNP SiOx memory device are provided in the Supporting Information (Figures S11−S14). To further account for the different switching behaviors of the StcNP SiOx 25 (1) and 75 (1) memory devices, we analyzed the breakdown mechanism in electrically stressed nanoscale Au wires. Generally, it is believed that the breakdown of a metal wire is attributed to the gradual movement of the ions arising from the transfer of momentum from the electrons moving into the metal wire under the influence of the electric field,48−52 which is better known as electromigration. This process can be further accelerated under higher power situations such as with increasing current density, which leads to greater Joule heating through the metal wire because of the greater amount of electron scattering. Because the electromigration rate depends on the Joule heating that depends on the physical dimensions of metal wires, the Au wire geometry, which is vertically formed through the StcNP structure, is an important parameter. From the StcNP structure shown in Figure 1f, we assumed that the Au wire has a truncated conical shape that has different diameters of the top and bottom circles (dp (pd = 0) and dp (pd)), as shown in Figure 4a. From the experimental results shown in Figure 1f, we found the ratio of pore contraction, d(dp (p))/dp, to be −2.22, which is higher than that of a previous

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The solution of eq 1 can be expressed in the following form F

DOI: 10.1021/acs.nanolett.7b03373 Nano Lett. XXXX, XXX, XXX−XXX

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⎛t t Q −m mx Q 1 ⎞ e (e + e−mx) + Q e−mx⎜ w sub − ⎟+ 2 2km km2 ⎠ km2 ⎝ ksub (2)

scalable device platform for SiOx resistive memory. In particular, we achieved sub-10 ns (up to 6 ns) switching speeds for both set and reset process using the designed StcNP SiOx memory with a |pd| of ∼75 nm and a minimum dp of ∼10 nm, while maintaining its excellent switching performances such as a ∼107 ON−OFF ratio, six multistates, and a retention time of 104 s. Moreover, the device endured 103 cycles. In contrast, SiOx memory devices having multiple StcNPs (#: 10 and 100) of |pd| = ∼75 nm, exhibited a relatively higher device variability, which arose from the potential variation in nanogap sizes or the existence of different sizes of switching filaments in a device cell. Furthermore, the designed StcNP SiOx memory with |pd| = ∼25 nm also exhibited a relatively lower device yield (∼31%), much slower switching (>2 μs), and a large fluctuation in the switching during 103 cycles because of the possibility of the formation of a larger gap. By considering the generated temperatures during the electromigration breakdown process of the Au wires and the electric field at the nanogap, we discussed the potential difference in switching performance for the SiOx memory devices with different StcNP pore depths (|pd| = ∼75 and 25 nm). Our approach provides a novel way to control and form single nanoscale conductive filaments that satisfy the prerequisites for nonvolatile resistive memory applications. Methods. Switching Speed Measurement. Each switching state of the StcNP SiOx memory device was programmed by set (5 V) or reset (16 V) pulses of 6, 10, or 20 ns from an Agilent 81104A pulse generator. The rising and falling edge of the pulses were 2.8 ns. Subsequently, I−V sweeps (from 0 to 1.0 V) were performed to measure each switching current using a 4155C semiconductor parameter analyzer. To identify the applied pulses, we used an oscilloscope (Siglent 1304CFL) and recorded the waveforms corresponding to each operating voltage (Figures S6 and S15). The nonsquare and deformed pulse waves were observed due to the bandwidth limit of the oscilloscope and the parasitic impedance components of the measurement system. Note that all electrical characterizations of the devices were performed under ∼10−5 Torr. Although the switching filament consisting of Si-NC is expected to be formed inside a pore, the electroforming process (breakdown process of SiOx) could produce oxygen as a result of the reduction of SiOx to Si. We speculate that this reaction produced oxygen inside a pore and could lead to reoxidation of the exposed Si phase during the switching operation, causing switching failure, which results in the necessity of the vacuum condition for operation.

where T is the temperature of the Au wire, Q is the net energy input expressed as Q = J2ρ, and m is related to heat loss into substrate, expressed as m = (ksub/ktwtsub)1/2 with ksub, kmetal, tw, and tsub being the thermal conductivity and the thicknesses of the metal wire (Au) and the substrate (SiO2), respectively.49 On the basis of the Au wire geometry, we assumed that (i) the width of the wire is reduced from dp (x = 0) to dp (x = |pd|) along the x-axis, (ii) the wire length, L, is |pd|, and (iii) the average thickness of the wire, tw, is rp (pd). Note that we set the values, ρ = ∼6 μΩcm, ksub = 0.5 WK−1 m−1, and k = 300 WK−1 m−1 based on previously extracted parameters for Au and SiO2 material.47 By considering the surface area of Au wire depending on the pd, we calculated the breakdown current densities (Jb) of the Au wire as a function of rp at the point where the experimental current through the wire plummets suddenly, as shown in Figure 4c. When pd and the rp are smaller, a higher Jb is obtained, resulting in a higher Q. For example, the Jb for an Au wire of |pd| = 25 nm is higher than that of |pd| = 75 nm at the same rp, which is consistent with previous theoretical and experimental Jb features.47−49 Figure 4d shows the simulated temperature profile as a function of pd for the Au wire of |pd| = 75 nm during the breakage process. As dp decreased, there was a sharp increase in temperature. We found the hottest point (∼850 °C) at one end of the wire with the smallest dp, and this is similar to the reported temperature range of 157−727 °C (430−1000 K) for Au nanowires at break point.30,49,50,52 It should be noted here that the breaking temperature changes with the wire geometry, junction structure, such as planar and vertical form, and the supporting insulator material.30,49,50,52 At the hotspot, higher temperatures induced by Joule heating can further increase the metal ion mobility, expediting electromigration. Consequently, there is a greater probability of breakage at this point. As shown in Figure 4e, however, the simulated maximum temperature is very high (∼1990 °C) for the Au wire of |pd| = 25 nm, which is much higher than the bulk melting temperature of Au (1064 °C). This excessive heating on short and thick wires during electromigration could make the size of the nanogap larger, and round the ends of the electrodes by local melting,51 which is consistent with the experimental result for our planar Au wire/SiO2 junction. (Figure S10). From these simulations and experiments, it is expected that the nanogap size for the Au wire of |pd| = 75 nm is relatively small compared to that of |pd| = 25 nm, which implies that a stronger electric field can be applied under same programming voltage. In such a case, the mechanical pressurization at the nanogap can be strengthened by a high electric field,5 inducing the phase transitions in Si and causing the faster switching of the StcNP SiOx memory. Indeed, it has been reported that the crystallization rates in phasechange materials can be enhanced in the presence of stronger electric fields because of the reduction in the nucleation barrier.53,54 In contrast, when the nanogap is larger (e.g., |pd| = 25), the electric field at the same programming voltage is relatively low, thus providing insufficient energy for the formation of Si-NC filaments and for phase transition, resulting in a high probability of switching failure (Figure 3b). In this paper, we have suggested a practical approach to control and confine a single Si-NC filament through a tunable and well-defined StcNP structure and utilized it as a reliable and

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ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.7b03373.

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Additional figures (PDF)

AUTHOR INFORMATION

Corresponding Authors

*E-mail: [email protected]. *E-mail: [email protected]. ORCID

Tae-Wook Kim: 0000-0003-2157-732X Gunuk Wang: 0000-0001-6059-0530 G

DOI: 10.1021/acs.nanolett.7b03373 Nano Lett. XXXX, XXX, XXX−XXX

Letter

Nano Letters Author Contributions

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G.W. conceived the project, S.K. performed the experiments and analyses, and together they wrote the paper. S.J., J.-W.C., and S.C. assisted in the measurement of electrical properties such as the endurance, retention, and switching speeds shown in Figures 2 and 3. S.-J.J. and T.-W.K. contributed to drawing the schematics and capturing all SEM images in Figures 1a−d and 2a,c, and those in the SI. T.-W.K. and G.W. oversaw the project and revised the manuscript. G.W. led the effort to completion. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This work was supported by the National Research Foundation of Korea (NRF-2016R1C1B2007330), KU-KIST research fund, Samsung Electronics, a KU Future Research Grant, and the Korea Institute of Science and Technology (KIST) Young Fellow Program.

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