Controlled Fabrication of Silicon Nanowires by Electron Beam

Dec 24, 2004 - Figure 2 overviews scanning electron microscope (SEM) images of some results of the electrochemical size reduction experiments. In Figu...
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NANO LETTERS

Controlled Fabrication of Silicon Nanowires by Electron Beam Lithography and Electrochemical Size Reduction

2005 Vol. 5, No. 2 275-280

Robert Juhasz,* Niklas Elfstro1 m, and Jan Linnros Laboratory of Materials and Semiconductor Physics, Royal Institute of Technology, Electrum 229, SE-164 40 Kista, Sweden Received November 7, 2004; Revised Manuscript Received December 1, 2004

ABSTRACT We demonstrate that electrochemical size reduction can be used for precisely controlled fabrication of silicon nanowires of widths approaching the 10 nm regime. The scheme can, in principle, be applied to wires defined by optical lithography but is here demonstrated for wires of ∼100−200 nm width, defined by electron beam lithography. As for electrochemical etching of bulk silicon, the etching can be tuned both to the pore formation regime as well as to electropolishing. By in-situ optical and electrical characterization, the process can be halted at a certain nanowire width. Further electrical characterization shows a conductance decreasing faster than dimensional scaling would predict. As an explanation, we propose that charged surface states play a more pronounced role as the nanowire cross-sectional dimensions decrease.

Semiconductor nanowires have recently attracted much interest for their potential use in high-density electronics and for the possible self-organization of such wires by new growth techniques. But, semiconductor nanowires may also be used as sensors due to the extreme sensitivity of the current transport on the local environment around the wire. Working essentially as the gate in a field-effect transistor, a nanowire may be used to probe, e.g., biological molecules at very low concentrations.1 The fabrication of nanowires is therefore an important challenge; in particular as most lithographic techniques do not provide enough lateral resolution. Although new methods such as nanowire growth by chemical vapor deposition (CVD), and other self-assembly techniques, indeed offer mass-production at nanosized dimensions,2,3 conventional lithography techniques still offer a greater flexibility and precision in device positioning. We believe size-reduction in combination with conventional (optical) lithography offers a way toward true realization of nanoscale elements in commercial devices. For example, the previously mentioned nanowire detectors could be implemented using a combination of lithography and size reduction to combine conventional circuitry with nanosized device elements, otherwise available only by growth or advanced scanning probe or scanning electron beam techniques. A well-known size reduction method is oxidation,4,5 which was recently used to fabricate nanowire field effect transistors with cross-sectional dimensions ranging down to 10 nm.6,7 * Corresponding author. E-mail: [email protected] 10.1021/nl0481573 CCC: $30.25 Published on Web 12/24/2004

© 2005 American Chemical Society

Oxidation has, however, a tendency to amplify surface inhomogeneities resulting from, e.g., the lithography. For the formation of quantum dots, this effect is desired8 and can even be utilized for single or few-electron devices.9 In this paper, we present an alternative method for size reduction of silicon nanowires by electrochemical etching in a microelectrochemical cell, where in-situ electrical and optical characterization can be performed between the etching steps. Electrochemical etching is a low-temperature process that for etching of bulk silicon offers many regimes of operation: polishing, macropore formation, and porous formation,10-14 and it has previously been used by the authors for size reduction and shape control of silicon nanopillars fabricated from bulk material.15 In this novel application to nanosized device structures, we show that the etching process still can be tuned to access all the possible etching regimes and to achieve optimal size-reduction conditions to reduce nanowires from 100 to 200 nm width in a controlled way to widths ranging down to below 10 nm. Mainly due to design flexibility reasons, the initial structures were here fabricated by electron beam lithography, but the initial dimensions are indeed also accessible by deep UV optical lithography. In comparison to oxidation, the advantages of this size reduction method is low temperature operation, a higher degree of control during size reduction, and a possibility of controlling surface morphology, while a drawback is the requirement of electrical contacts to each nanowire during the etching. Finally, we also explore some of the physics of these devices

Figure 1. Images of sample and setup, with (a) showing the chip layout with gold pads and (b) showing the central device area. The positions of the nanowires are indicated by letters A-C. In (c) a schematic cross-section of the etching setup with a mounted sample is shown, and in (d) a schematic cross-section of the nanowire during etching is shown. The arrows indicate the current flow in the device and the curved arrow indicates photogeneration of carriers.

and present electrical measurements of the nanowires, showing that the conductance at room temperature is largely dependent on back gate voltage. At small widths, we observe a nonlinear decrease of the conductance, which we attribute to the presence of charged surface states. Silicon nanowires were fabricated from silicon on insulator (SOI) material having a 100 nm thick single-crystalline p-doped (F ) 17 - 22 Ωcm) Si layer on top of a 400 nm buried oxide layer separating the bulk silicon layer. A combination of optical and electron beam lithography (EBL) was utilized to fabricate the samples.16 An optical microscope image of the sample can be found in Figure 1a. Ten gold pads (0.2 µm thick) connect to the central device structure consisting of three nanowires and broader (200 µm wide) and more narrow (50 µm wide) connector leads fabricated in the top silicon layer (see Figure 1a). The nanowire positions are indicated by letters A-C in Figure 1b, which shows the device area in detail. Care was taken during the sample design to ensure that the resistance of the contact leads was smaller than that of the nanowires. A variety of different lengths and widths of nanowires were fabricated, with 100 and 200 nm being the main widths, and with nanowire lengths ranging from 0.5 µm to 5 µm. Size reduction was performed by electrochemical etching in a specially designed microelectrochemical cell, shown schematically in Figure 1c. The sample is mounted such that the etching cell is centered on the chip, allowing needle probes to contact nanowires electrically at both ends. The etched area is further delimited to about 100 by 100 µm by partially covering it with a polymer layer. Current and a reference electrodes (platinum) were also included in the cell. Finally, a plastic optical fiber was immersed in the etching solution providing illumination of the sample surface from 276

a 150 W halogen lamp. The etching solution was hydrofluoric acid (HF) diluted by water and ethanol (50%)13,14 where the HF content ranged between 0.12% and 0.03%. (NB! Hydrofluoric acid is corrosive and toxic, and should be handled with appropriate protection.) For electrical characterization and to provide proper electrical conditions for the electrochemical reaction, a computer-controlled Keithley 6487 picoammeter/voltage source and a KPCI-3201 D/A-A/D card were used. High-quality relays were used to switch between two main electric circuits: (i) electrical characterization where a voltage, VDS, was applied between the source and drain of the nanowire, and (ii) electrochemical etching where both source and drain were connected together. In both cases, a back gate voltage, VG, provided additional control of the current, modulating the carrier density in the nanowire. Figure 1d illustrates schematically the current flow in the top silicon layer during etching. At the HF/silicon interface, fluoride ions react with silicon to electrochemically dissolve the surface layer and thus generate a dissolution current. It is well known14 that for bulk silicon the etching reaction can be tuned either to spontaneously etch random (nano-)pores, to etch ordered pores (macropores), or to smoothen the surface (electropolishing). The main governing parameter is the surface hole concentration in the silicon in relation to the fluoride ion concentration of the etching solution. In the present case the thin silicon low-doped layer (100 nm thick) adds a complication, since it will be depleted of carriers due to the band bending occurring at the silicon/ HF interface.17 Thus, photogeneration by the illumination (curved arrow in Figure 1d) is needed to create extra carriers required to tune the etching reaction into an appropriate regime. It should be noted that electrical connections to each end of a nanowire are vital to properly set the etching Nano Lett., Vol. 5, No. 2, 2005

Figure 2. Top SEM views of nanowires before (a) and after etching (b-d). Figure (d) shows a 45 degree tilt view of a nanowire which has been etched free-hanging. Figures (e) and (f) show that an initially rough nanowire (e) can be both size reduced and smoothed (f) using a slightly electropolishing etching condition. Figure (g) shows that two sides of the nanowire can be subject to different etching conditions, with the left side (A) be porously etched and the right side (C) being etched in the “macropore” formation regime (with the square pores, however, being of sub-100 nm width). The inset shows the nanowire (B) in detail.

parameters of each wire, and this poses some limitations on sample design. In the present design, only a single nanowire was exposed to etching solution. A more elaborate scheme with a chip containing arrays of nanowires and additional device structures should be possible. Then, the polymer layer should be lithographically patterned to only expose each nanowire to the etching solution, while protecting the connecting metal pads and other circuitry on the chip. Figure 2 overviews scanning electron microscope (SEM) images of some results of the electrochemical size reduction experiments. In Figure 2a, one example of an initial structure of 100 nm width is shown in top view. Figures 2b and 2d show uniformly size reduced nanowires. Nanowire widths of 20-30 nm could be routinely obtained from initially 100200 nm wide nanowires (Figure 2b), though it was possible to obtain a width of 9 nm in one case (Figure 2c). This wire was not continuous (concluded by SEM observation and electrical characterization), most likely due to variations in the initial structure. Typical parameters for uniform sizereduction are VB ) 0-1 V (etching cell voltage), VG ) 10 V (back gate voltage), 0.03% - 0.06% HF concentration, Nano Lett., Vol. 5, No. 2, 2005

Figure 3. Nanowire width as a function of etching time (a) for two different etching solutions. The etching rate is 0.056 nm/s for the 0.06% solution (solid line) and 0.037 nm/s for the 0.03% solution (dashed line). The error bars indicate the variation in wire width along its length. Figure (b) shows vertical etch amount (measured with AFM) as a function of horizontal etch amount (measured with SEM). The dashed line, fitted to the data, yields a vertical to horizontal etching ratio of 0.498:1. The inset shows a typical nanowire (of ∼100 nm width/height) imaged with AFM.

and 0.2 W/cm2 illumination intensity (measured at the output of the plastic optical fiber), resulting in an etching current of I ) 100 nA, of which 70-80% is caused by the photogeneration. The etch rate was measured from several experiments (see Figure 3) and was found to be 0.056 nm/s and 0.037 nm/s for the 0.06% and 0.03% HF concentration, respectively. Such a low etch rate is indeed advantageous for size reduction into the sub-10 nm regime. Figure 3a plots the remaining nanowire width, as determined from SEM imaging, versus etch time at two different HF concentrations. To address the simultaneous decrease of the nanowire height, atomic force microscope (AFM) imaging was also performed (inset in Figure 3b). The result is plotted in Figure 3b demonstrating an almost perfect 1:2 scaling of the vertical etch rate with respect to the horizontal etching, confirming (as expected) the same etch rate for all three exposed surfaces 277

Figure 4. Nanowire I-V curves for different gating voltages VG. The nanowire is of 100 nm width, 500 nm length, and 50 nm height.

of the nanowire. At the same time silicon dioxide is also etched by the HF solution. Due to the very low HF concentration in the electrochemical etching case, the etching is negligible (measured to < 0.0013 nm/s for the 0.12% solution). However, if pure chemical etching is employed (nanowire totally disconnected), the etching of silicon dioxide dominates and by using a stronger solution (5% HF) the silicon dioxide beneath the silicon can be etched away. Figure 2d shows a 45 degree tilt view of such a free-hanging nanowire (note the slight bending toward the surface). Furthermore, Figures 2e and 2f show that the conditions during uniform size reduction actually lead to a polished surface. The initial structure (Figure 2e) has a nonhomogeneous edge caused by the initial fabrication process. After size-reduction from 200 to 100 nm width, Figure 2f shows that the quality of the edge is improved after etching, with all but the most severe inhomogeneities being smoothed out. This phenomenon could allow for larger error tolerances in a commercial application. Finally, in Figure 2g the regime of porous etching is illustrated. This nanowire was etched in a stronger solution (0.12% HF content) and at VG ) 0 V for 4000 s. Furthermore, it was only connected to the potential VB ) 1 V at the right side (C), while the left side (A) remained disconnected. As a result, a potential drop developed across the length of the nanowire, leading to macropore formation at site C and random nanopore formation at site A. The transition occurs in the nanowire itself (at B, see inset). It can be noted that macropores form even in the nanowire, though it is of roughly the same width as the pores (∼60 nm). Turning to the electrical characterization, Figure 4 shows typical I-V curve families for different gate voltages of a nanowire (before etching). It can be noted that the conductance of the nanowire changes several orders of magnitude from ∼1 µS at VG ) 10 V into the nS range below VG ) 0 V. In Figure 5, the lower plot shows how the conductance (at VDS ) 0 V and VG ) 0 V) evolves during etching of a nanowire. During this experiment, the sample was also removed and characterized in an optical microscope after each etch cycle (images in Figure 5 a-e). Due to the decrease of layer thickness and thus changed interference properties of the top silicon layer, a change in color tone was observed. 278

Figure 5. Optical microscope images (a-e) of a nanowire before and at different time steps of the etching, with the plot indicating the conductance at each specific time. The nanowire was initially of 200 nm width and was found to be of 40 nm width in step (e), where the etching was stopped. A similar nanowire was subsequently etched until is was noncontinuous, and its optical microscope image is found in Figure (f).

Thus, there are both electrical and optical indicators to establish a proper time to stop the etching. In this case, the etching was halted when the device layer had turned into an intense red color (Figure 5e) and the conductance had been decreased from 2.5×10-9 S to 2×10-11 S (still showing a linear I-V curve). SEM observations showed a wire width of 200 nm before etching and 40 nm after etching. Since a positive gate voltage VG increases the conductivity of the nanowire (see Figure 4), the current conduction mechanism in the nanowire is likely to be electron conduction in an inversion charge layer close to the silicon dioxide layer (similar to a MOS transistor). The conductance, G, of the nanowire is then given by G ) µnQn‚W/L,18 with W, L, µn, and Qn denoting the width, length, inversion layer mobility, and inversion layer charge per unit area, respectively. Thus, for nanowires of different dimensions, G ∼ L-1, G ∼ W, and GL/W ) µnQn ) constant. The L-1 proportionality is clearly demonstrated in Figure 6a where the conductance plotted versus inverse length is linear for nanowires of different length. In contrast, the decrease of the width, W, by a factor of 5 (from start to end of etching in Figure 5) should reduce the conductivity equally, by a factor of 5, while the observed decrease is much larger (∼125). To study this in more detail, the expression GL/W ) µnQn was plotted versus nanowire width, for nanowires of different crosssectional dimensions (but constant length, L) and of different surface treatment (Figure 6b). Included in the plot are also data from the broader connection leads, for comparison. For Nano Lett., Vol. 5, No. 2, 2005

Figure 6. (a) Shows conductance, G, versus inverse length, L, for nanowires of different length and gate voltage, VG, and constant width W ) 200 nm. (b) Shows the expression GL/W (at VG ) 0 V) versus width for nanowires of 500 nm length. As-fabricated nanowires (squares) and air exposed nanowires (up-triangles) show a smaller conductivity than freshly etched (circles) and HF dipped nanowires (down-triangles). The arrows indicate the development of GL/Wfor a certain sample in the different stages. For comparison, GL/W was also calculated for a conductor wire of 200 µm length and 50 µm width.

decreasing nanowire widths, there is a large decrease of GL/W. We believe this is due to charged surface states influencing the charge density Qn of the inversion layer. As the nanowire width and height decrease during the progression of the etching, the effect should also be more prominent since the charged surface states become more closely located to the inversion layer charges. The importance of surface effects is further demonstrated by measuring the conductivity during prolonged air exposure after the etching, where the hydrogen passivation that is present on the surface after etching deteriorates, possibly being replaced by a poor quality native oxide, and thus altering the surface state density. The time-decay of the conductance was measured and was found to obey a power law so that G(t) ) g0tk, with t being the time in seconds after the etching solution removal and with k ) -0.348 and g0 ) 1.39×10-7 S. Indeed, after a subsequent HF dip the conductance almost returns to the previous values. In contrast to the present results, Koo et al. Nano Lett., Vol. 5, No. 2, 2005

report7 on an increased factor GL/W for decreasing nanowire width, which in their case is attributed to an increase of µn induced by strain arising from the thermal oxidation used for size reduction. In our case, no strain should be introduced during the electrochemical size reduction (µn constant), but on the other hand, the nanowires are not embedded in oxide so that the surface is more susceptible to external conditions, which may influence the inversion layer charge Qn. Thus, we conclude that surface defects play a crucial role for the conductance of very small nanowires. This effect can be balanced by changing the back gate voltage to achieve a flat band condition. To conclude, we have demonstrated that electrochemical etching offers a novel and flexible tool for controlled nanowire size reduction and for modification of surface morphology, and that all regimes of the electrochemical etching reaction (polishing and macropore and nanopore formation) are available also for nanowires. While nanowires of sizes down to 30 nm (still continuous over a length of up to 1 µm) could be routinely generated from wires of 100200 nm initial size, the smallest wire obtained was 9 nm in diameter. The method allows for a high degree of interactivity, since electrical (and optical) characterization can be performed in situ. A faster decrease in conductance than predicted by the reduction in width as nanowire dimensions decreased below 100 nm was also observed and is attributed to charged surface states influencing the charge density of the inversion layer, responsible for the current conduction through the nanowire. Furthermore, the presented method is not limited to a single step. In a detector application, a fabricated structure could, for example, be subjected first to polishing and size reduction and then to nanopore formation to create a small device with a large surface area. If a flow-cell system was incorporated, the steps of electrochemical etching could be followed by other chemical or biological treatment, such as incubation with detector proteins. The demonstrated sensitivity to charged surface states would furthermore enhance the function of such a detector. Acknowledgment. The authors acknowledge prof. David Haviland for providing access to the electron beam lithography system and John O ¨ sterman for help with the AFM measurements. Finanical support was received from the Swedish Strategic Research Council. Supporting Information Available: Sample fabrication process schematic. This material is available free of charge via the Internet at http://pubs.acs.org. References (1) Cui, Y.; Wei, Q.; Park, H.; Lieber, C. M.; Science 2001, 293, 1289. (2) Hiruma, K.; Yazawa, M.; Haraguchi, K.; Ogawa, K.; Katsuyama, T.; Koguchi, M.; Kakibayashi, H. J. Appl. Phys. 1993, 74, 3162. (3) Alivisatos, A. P.; Johnsson, K. P.; Peng, X.; Wilson, T. E.; Loweth, C. J.; Bruchez, M. P.; Schultz, P. G. Nature 1996, 382, 609. (4) Liu, H. I.; Biegelsen, D. K.; Ponce, F. A.; Johnson, N. M.; Pease, R. F. W. Appl. Phys. Lett. 1993, 64(11), 1383. (5) Li, Z.; Chen, Y.; Kamins, T. I.; Nauka, K.; Williams, R. S. Nano Lett. 2004, 4(2), 245. 279

(6) Yang, F. L.; Lee, D. H.; Chen, H. Y.; Chang, C. Y.; Liu, S. D.; Huang, C. C.; Chung, T. X.; Chen, H. W.; Huang, C. C.; Liu, Y. H.; Wu, C. C.; Chen, C. C.; Chen, S. C.; Chen, Y. T.; Chen, Y. H.; Chen, C. J.; Chan, B. W.; Hsu, P. F.; Shieh, J. H.; Tao, H. J.; Yeo, Y. C.; Li, Y.; Lee, J. W.; Chen, P.; Liang, M. S.; Hu, C. IEEE Symposium on VLSI Techology, IEEE Digest of Technical Papers 2004, 196. (7) Koo, S. M.; Fujiwara, A.; Han, J. P.; Vogel, E. M.; Richter, C. A.; Bonevich, J. E. Nano Lett. 2004, 4(11), 2197. (8) Valenta, J.; Juhasz, R.; Linnros, J. Appl. Phys. Lett. 2002, 80, 1070. (9) Guo, L.; Leobandung, E.; Zheng, L.; Chou, S. Y. J. Vac. Sci. Technol. B 1997, 15(6), 2840. (10) Canham, L. T. Appl. Phys. Lett. 1990, 57, 1046. (11) Lehmann, V. J. Electrochem. Soc. 1993, 140(10), 2836.

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(12) Kleimann, P.; Linnros, J.; Juhasz, R. Appl. Phys. Lett. 2001, 79(11), 1727. (13) Fo¨ll, H.; Christophersen, M.; Carstensen, J.; Hasse, G.; Mater. Sci. Eng. R 2002, 39(4), 93. (14) Zhang, X. G. J. Electrochem. Soc. 2004, 151(1), C69. (15) Juhasz, R.; Linnros, J. Appl Phys. Lett. 2001, 78(20), 3118. (16) A description of the fabrication process can be found in the Supporting Information of this paper. (17) Sato, N. Electrochemistry at Metal and Semiconductor Electrodes; Elsevier Science B. V.: Amsterdam, 1998; p 249. (18) Hauser, J. R. IEEE Trans. Electron DeV. 1996, 43(11), 1981.

NL0481573

Nano Lett., Vol. 5, No. 2, 2005