A Versatile Chemical Vapor Deposition Method to Synthesize One

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J. Phys. Chem. C 2008, 112, 8594–8599

A Versatile Chemical Vapor Deposition Method to Synthesize One-Dimensional Silica-Sheathed Nanostructures D. P. Wei, Y. Ma, H. Y. Pan, and Q. Chen* Key Laboratory for the Physics and Chemistry of NanodeVices and Department of Electronics, Peking UniVersity, Beijing 100871, China ReceiVed: December 20, 2007; ReVised Manuscript ReceiVed: March 13, 2008

We developed a simple and versatile chemical vapor deposition (CVD) method to synthesize uniform silica sheaths with controlled thickness on a series of one-dimensional nanostructures, such as ZnS, CdS, ZnSe, Si, and Ge nanowires. The nanowire/silica nanocables were characterized using electron microscopy and energy dispersive X-ray spectrometry. The silica sheath was observed to dramatically improve the thermal stability of the nanowires while keep their optical properties unchanged. The growth mechanism and the synthesis conditions for the silica shell were studied. 1. Introduction One-dimension (1D) nanostructures are promising building blocks for the electronic or optoelectronic nanodevices.1–3 However, due to the large surface to volume ratio, the random charge transfer, or absorption of impurity on the surface, surface oxidation or reduction can dramatically affect the performance of the devices and hamper their applications. The silica-sheathed 1D nanostructures afford a feasible and effective approach to avoid uncontrollable surface effect, thus improving the reliability and long-term stability of the devices. On the other hand, being an ideal gate dielectric, silica sheath has recently been used to fabricate high-performance surrounding gate field-effect transistors (FETs), which can be directly integrated.4–7 By chemical modification of silica surface, silica-coated FETs can also be used for the detection of chemical and biological species.8 Several methods have been developed to synthesize silicasheathed nanocables. Most of the methods, such as thermal evaporation,9–17physical insertion of silica nanotubes,18 and chemical vapor deposition (CVD),4,5 need high temperature that may destroy the nanowires with low melting point. Some approaches have been developed to fabricate the nanowire and the silica sheath in one step;9–12,14,16,17 although maybe simple, they could not easily control the dimension of the nanowires and the silica sheath independently. Hence, a two-step method is instructive for the synthesis of the heterostructure.7,19 Some chemical methods have been generated to fabricate nanocables at relatively low temperature,20–22 but they are not suitable for the applications like direct integration of FETs. Furthermore, a general method is still absent to controllably coat silica sheath on series of 1D nanomaterials. In the present work, we developed a simple and effective technique to synthesize uniform silica sheaths with controlled thickness on a series of 1D nanostructures, such as ZnS, CdS, ZnSe, Si, and Ge nanowires. The silica sheath was found to dramatically improve the thermal stability of the nanowires while keeping their optical properties unchanged. 2. Experimental Section A high-temperature tube furnace with a quartz tube was used to fabricate the nanocables. ZnS, CdS, ZnSe, Si, and Ge * Corresponding author. E-mail: [email protected].

nanowires were prepared using CVD methods that have been described in the literatures.23–27 Nanowires on the Si substrates were placed in an alumina boat and were introduced in a quartz tube of a high-temperature furnace. The system was first flushed by high-purity Ar for 5 min with flow >2000 sccm (standard cubic centimeters per minute). Then, under a constant flow of a mixture of Ar (150 sccm) and H2 (50 sccm) the furnace was heated to 900 °C at a rate of 30 °C/min. The mixture was then used as the carrier gas flowing through the Si precursor (SiCl4) bath and into the reaction tube. The flow of the SiCl4 gas was controlled by the bath’s temperature, which was 50 °C in the present experiments. Meanwhile, ZnS nanowires on Si substrate were moved from low-temperature region to the position of 580 °C along the downstream side of the gas flow away from the center of the furnace. Similarly, CdS, ZnSe, Si, and Ge nanowires on the substrates were positioned in the region of 400-700 °C. The reaction lasted 5∼20 min according to the thickness of the silica sheath needed. After the reaction, H2 flow was stopped, the tube was flushed with >2000 sccm Ar for 15 min to get rid of unreacted gases. Finally, the furnace was cooled to room temperature. The products were characterized using scanning electron microscope (SEM, FEI XL 30F), transmission electron microscope (TEM, FEI Tecnai G20 and FEI Tecnai F30) and energydispersive X-ray spectrometry (EDS, EDX spectroscope attached to the TEM). UV-vis absorption spectra were obtained using a Hitachi U-3010 spectrophotometer. Photoluminescence (PL) spectra were obtained using a Hitachi F-4500 with excitation wavelength being 250 nm. 3. Results and Discussion ZnS/Silica nanocables were synthesized as an example. Figure 1a shows an SEM image of silica-sheathed ZnS nanocables. High-density 1D nanostructures can be seen with typical lengths up to tens of micrometers and diameters ranging from 50 to 100 nanometers. The inset of Figure 1a shows that original ZnS nanowires have similar morphologies to the silica-sheathed 1D nanostructures. The TEM image in Figure 1b shows that the 1D nanostructure has a core-shell structure. The dark contrast core has a uniform diameter of 50 nm, whereas the light contrast sheath has a uniform thickness of about 15 nm and covers the entire nanowire. Our experiments show that all of the nanowires

10.1021/jp711963p CCC: $40.75  2008 American Chemical Society Published on Web 05/14/2008

Synthesizing 1D Silica-Sheathed Nanostructures with CVD

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Figure 1. (a) SEM image showing a high density of ZnS/silica nanocables. Inset: SEM image of bare ZnS nanowires. (b) TEM image of ZnS/silica nanocables. The lower right inset is the SAED pattern of the area marked by “A”. The upper left inset shows TEM image of bare ZnS nanowire. The bar is 5 µm. (c) HRTEM image of a ZnS/silica nanocable. (d) EDS line profiles taken along the white dashed line in the inset. Inset: STEM image of a silica-coated ZnS nanowire.

Figure 2. TEM images of ZnS/silica nanocables synthesized with growth times of 5 (a), 10 (b), and 20 min (c).

are uniformly coated. The original ZnS nanowire does not have a shell but has a smooth surface, as shown in the upper left inset of Figure 1b. The lower right inset of Figure 1b shows a selected area electron diffraction (SAED) pattern taken from the nanocable marked by “A”. The diffraction spots can be indexed to wurtzite ZnS, indicating that the core has a single crystalline structure with the axis along [001] direction. Several weak diffuse rings can be seen in the SAED due to the amorphous sheath. High-resolution transmission electron microscopy (HRTEM) image (Figure 1c) confirms that the shell is amorphous and the core is a well-crystallized single crystal. The lattice spacing of the planes perpendicular to the growth direction is 0.63 nm, corresponding to (001) plane of wurtzite ZnS. Figure 1d shows a scanning transmission electron microscopy (STEM) dark field image of a nanocable (the inset) and EDS line profiles for different elements along the direction perpendicular to the axis. It shows clearly that the core consists of Zn and S and the shell consists of Si and O, confirming that we have successfully synthesized ZnS/silica nanocables. EDS study shows that the atomic ratio of O to Si in the asprepared silica shell is smaller than 2, indicating the silica is SiOx instead of SiO2. We also observed that annealing the nanocables at 600 °C in the air for 2 min can raise the O to Si ratio of the shell from about 1.4 to about 1.65. Therefore, for

the applications in FET it is better to anneal the nanocables in the air for some time to improve the insulating property of the shell. The shell thickness can be controlled by controlling the growth time. Figure 2 shows TEM images of ZnS/silica nanocables grown at 580 °C with different growth time for the silica shell (5, 10, and 20 min, respectively). The thickness of the silica shell is 8, 17.5, and 36 nm respectively, indicating that the shell thickness is approximately linear with the growth time. Although this controlling method is simple, it is effective to the applications of the nanocables. Thermal stability of the nanowires sheathed by silica layer was found being improved significantly compared with that of bare nanowires. Both bare ZnS nanowires and silica-sheathed ZnS nanowires were calcined at 600 °C for 30 min in the air. Figure 3a shows that the surface of the bare nanowire has recrystallized to nanoparticles. The electron diffraction pattern shown in Figure 3b can be indexed to ZnO instead of ZnS. EDS spectrum in Figure 3e shows the nanowire contains Zn and O but not S. The above evidence indicates that the nanowire has been oxidized to ZnO. The Cu peak in the EDS spectrum comes from the copper grid. On the other hand, silica-sheathed ZnS nanowires maintain their original morphology and crystalline structure, as shown in Figure 3c,d, and the composition of the nanowires remains unchanged (shown in Figure 3e).

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Figure 3. TEM images showing the morphologies of bare ZnS nanowires (a) and silica-coated ZnS nanowires (c) after they were calcined at 600 °C for 30 min in the atmosphere. The corresponding SAED patterns are shown in (b) and (d), respectively. (e) EDS spectra of the nanostructures shown in panels a and c, respectively.

Therefore, silica sheath can protect the inner nanowire from oxidation and benefits better thermal stability of the nanowires. Many semiconducting nanowires have wide applications due to their excellent optical properties. PL from CdS nanorods has been reported to shift to the blue and to increase due to the passivation of ZnS shell.28 To illuminate the influence of the silica sheath to the optical property of the nanowires inside, we measured the UV-vis absorption and photoluminescence properties of the pristine ZnS nanowires and the silica-sheathed ZnS nanowires in the same experiment conditions at room temperature. Figure 4a shows that the UV-vis absorption spectra obtained from the bare ZnS nanowires and the silica-sheathed ZnS nanowires are the same. Two absorption edges are observed at about 320 and 390 nm. Generally, the optical band gap for direct interband transitions can be obtained by extrapolating the linear portion of the plot (Rhν)2 versus hν to R ) 0, where R is the absorption coefficient.29,30 As shown in the insets of Figure 4a, the extrapolation of the plot (Rhν)2 versus hν to R ) 0 gives about 3.7 eV for the high energy absorption edge and about 3.2 eV for the low energy absorption edge. The high energy optical band gap is consistent with the band gap of bulk ZnS (which is about 3.66 eV). The band gap of small ZnS nanorods has been reported to blue-shifted compared with bulk ZnS.30 As the present ZnS nanowires have diameters being at least 30 nm, which is much larger than the Bohr diameter of bulk ZnS materials (about 5 nm), there should be no quantum confinement effect in the present nanowires. The low energy absorption may be attributed to defects or impurities in the ZnS nanowires. The PL spectra taken from the bare ZnS nanowires and the silica-sheathed ZnS nanowires are also the same as shown in Figure 4b. A

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Figure 4. (a) UV-vis absorption spectra measured from bare ZnS nanowires and silica-sheathed ZnS nanowires. The inset are the corresponding plots of (Rhν)2 and hν. (b) PL spectra obtained from bare ZnS nanowires and silica-sheathed ZnS nanowires.

strong excitation peak is observed at around 406 nm, which is consistent with the low energy absorption edge at about 390 nm in the UV-vis absorption spectra. This excitation peak agrees with the reported excitation peak in ZnS nanowires bundles (at 413 nm),31 ZnS nanobelts (at 400 nm),32 and ZnS nanowires (at 398 nm),33 and may be attributed to interstitial sulfur lattice defects.34 Weak emission is also observed from the PL spectra at about 340-350 nm. Such emission is likely attributed to the intrinsic emission of ZnS. The above evidence shows that the silica sheath has little effect on the optical properties of ZnS nanowires. The approach reported here is highly versatile, and we focus on the ZnS/silica core-shell system only as a showcase introduction to this synthetic method. It is possible to fabricate silica-sheathed nanocables using a series of nanowires and nanotubes as core. To demonstrate the versatility of the method, we also successfully coated amorphous silica sheath on ZnSe, CdS, Ge, and Si nanowires. Figure 5 shows the TEM images of these bare and silica-sheathed nanowires. The clean and smooth surfaces of the bare nanowires are beneficial to the formation of ideal nanocables. All the nanowires are sheathed by uniform shell. The SAED patterns of the corresponding nanocables indicate that the core nanowires remain a single crystalline structure after being sheathed. Furthermore, the EDS spectra in Figure 6 verify that all the nanowires remain in their original composition and are coated by silica shell. ZnS, ZnSe, and CdS are widebandgap semiconductors. Their photogenerated charges are quite active and tend to transfer with the outside. Coating a

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Figure 5. TEM images of the bare nanowires (upper left image) and the corresponding silica-sheathed nanostructures (upper right image), and the SAED patterns taken from the nanocables (lower image). (a) ZnSe, (b) CdS, (c) Ge, and (d) Si.

Figure 6. EDS spectra taken from the area marked by the circles in the insets, which are TEM images of the silica-coated (a) ZnSe, (b) CdS, (c) Ge, and (d) Si nanostructures.

silica sheath on these wide-bandgap semiconducting nanowires may effectively avoid the photoinduced charge transfer. Ge and Si, as narrow-bandgap semiconductors, are perfect materials for solid electronic devices. By coating a thin insulating layer, high-performance surrounding gate FETs can be fabricated.6,7 By chemical modification of silica surface, silica-coated nanowires can also be used to fabricate biological and chemical nanosensors.8 The versatile approach reported here to growing silica shell could have broad applications in varies fields. The formation mechanism of the silica sheath was studied. It is known that SiCl4 can react with H2 and produce Si following the reaction:

SiCl4 + 2H2 f Si + 4HCl

(1)

This reaction has been used to synthesize Si nanowires with the help of catalysts.23,35,36 Here, instead of Si silica was formed to cover the nanowires. As no extra oxygen was introduced during the synthesis process, we propose that the Si produced

through the above reaction further react with the residual oxygen in the system

2Si + xO2 f 2SiOx

(2)

The residual oxygen has been reported to contribute to the formation of ZnO.37 Here, the residual oxygen contributes to the formation of silica. The temperature that is suitable to form silica-sheathed nanocables is studied. We found that silica layer can form in a large temperature range, from the highest temperature we used (900 °C) down to 400 °C. However, the nanowires may not stand very high temperature, which limits the suitable temperature range for different nanowires. ZnS nanowires were placed at the positions with different temperature in the furnace and silica layer was grown. Figure 7 shows the TEM images of the products. Only nanotubes were observed in the products synthesized at 900 °C. The nanotubes were confirmed to be silica tubes. Those facts indicate that the ZnS cores have been removed during synthesis process probably by thermal evapora-

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Figure 7. TEM images of the products obtained at different temperature using ZnS as cores. The temperatures are (a) 900, (b) 700, (c) 580, and (d) 350 °C.

tion. The products synthesized at 700 °C are silica-coated nanostructures, whose inner cores are partly evaporated. The sample prepared at 580 °C shows perfect silica-coated ZnS nanocables. At 350 °C, no silica sheaths are deposited on the surface of nanowires. Therefore, the morphologies of the products change from silica tubes to silica-coated nanocables and eventually to bare nanowires with decreasing growth temperature, and optimum temperature for growing silicasheathed nanocables exists. The higher end of the temperature range suitable to grow nanocables is different for different nanowires. For example, Si/silica nanocables can be obtained at 700 °C, at which temperature ZnS silica nanocables cannot be fabricated. Besides the deposition time, there are also other effects that affect the thickness of the SiOx layer. We observed that the deposition temperature does not significantly affect the thickness of the silica layer when the shell can be synthesized. With the same deposition time, the thickness of the silica layers covering ZnS nanowires only changes from 19 to 21 nm when the deposition temperature decreases from 900 to 580 °C. However, the nature of the nanowire to be covered does affect the thickness of the silica layer. After ten minutes deposition, silica covering ZnS, CdS, and ZnSe nanowires is about 17.5, 16, and 16 nm respectively, but silica covering Ge and Si nanowires is 21 and 32 nm, respectively. The thickness difference of the silica shells covering ZnS, CdS, ZnSe, and Ge nanowires may be due to the different absorption of silica on the nanowires. The extraordinary large thickness of the silica layer covering Si nanowires may due to some oxidization of Si nanowires. 4. Conclusions We developed a simple and general method to coat 1D nanomaterials with uniform silica shell with controlled thickness. Using this method, we successfully synthesized silica-sheathed ZnS, ZnSe, CdS, Si, and Ge nanocables. The nanocables were characterized using SEM, TEM, SAED, and EDS. The results of high-temperature annealing showed that the silica-sheathed nanowires have much better thermal stability than the bare nanowires. The optical properties of the silica-sheathed nanowires remain the same as the bare nanowires. The growth mechanism and the optimum conditions to synthesize nanocables were studied. The present approach may have broad applications in nano optical and electronic devices as well as in nanosensors.

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