Catalyst-Free Heteroepitaxial MOCVD Growth of ... - ACS Publications

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Catalyst-Free Heteroepitaxial MOCVD Growth of InAs Nanowires on Si Substrates Yi Jing,† Xinyu Bao,†,∫ Wei Wei,‡,± Chun Li,†,§,Ø Ke Sun,† David P. R. Aplin,† Yong Ding,⊥ Zhong-Lin Wang,⊥ Yoshio Bando,§ and Deli Wang*,†,‡,∥ †

Department of Electrical and Computer Engineering, ‡Material Science and Engineering Program, and ∥Qualcomm Institute, University of CaliforniaSan Diego, La Jolla, California 92093, United States § International Center for Materials Nanoarchitectonics (MANA), National Institute for Material Science, Namiki 1-1, Tsukuba, Ibaraki 305-0044, Japan ⊥ School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332-0245, United States ABSTRACT: We report the systematic study of catalyst-free syntheses of InAs nanowires on Si substrates with various growth parameters and surface treatments. Nanowire morphology and crystal structure were studied using scanning electron microscopy and transmission electron microscopy. High-resolution cross-sectional transmission electron microscopy studies reveal heteroepitaxy of InAs[111] nanowires on Si(111) substrate with clean and sharp interface. Single nanowire field-effect transistor measurements of InAs nanowires under optimal growth conditions indicate a typical electron concentration of 1018−1019 cm−3 and mobility of around 1000 cm2/V·s. III/V on Si devices with InAs nanowire array on p-Si show a broadband photodetection up to wavelength of 3.5 μm.

1. INTRODUCTION III−V compound semiconductor nanowires (NWs) have been attracting extensive research interest for applications as fieldeffect transistors (FETs), lasers, light-emitting diodes (LEDs), photodetectors, solar cells, chemical/biosensors, and thermoelectric devices.1−5 III−V semiconductor devices are usually epitaxially grown on expensive planar lattice-matched III−V wafers, which greatly increase the manufacturing cost. The heterogeneous integration of III−V materials with low-cost substrates, such as Si, is highly desirable because it not only reduces the manufacturing cost but also enhances the device functions. However, owing to the large lattice mismatch and difference in thermal expansion coefficients, the III−V thin films epitaxially grown on Si suffer from large density of dislocations and antiphase boundaries. To this end, the onedimensional (1D) NW structure provides an alternative method to integrate III−V materials to Si. Owing to small dimensions (i.e., small contact area between a NW and its substrate), strains are relaxed within a few atomic layers at the interface,6 thus enabling heteroepitaxy of high-quality single crystalline III−V NWs on Si substrate without the restriction of lattice mismatch. Various methods have been employed to epitaxially grow III−V NWs on Si. The most popular one is the vapor−liquid− solid (VLS) method, first proposed by Wagner and Ellis in 1964.7 By introduction of a catalytic metal nanoparticle, which absorbs reactants in vapor phase to form supersaturated liquid alloy inside the nanoparticle, single crystal semiconductor NWs © 2013 American Chemical Society

can grow from the nucleated seeds at the liquid−solid interface.8 VLS mechanisms have been widely used to synthesize almost all kinds of semiconductor NWs, including Si,7 Ge,9 III−V compounds,8,10,11 II−VI materials,12,13 et al. However, Au, which is the most commonly used metal nanoscale catalyst for NW growth, diffuses and atomically dissolves in semiconductor NWs during growth and thus forms unwanted deep-level traps. These traps are notoriously deleterious to the performance of NW devices.14−16 Thus, it is highly desirable to synthesize III−V NWs without use of Au as nucleation and growth seed, which has been achieved by selfcatalyzed growth17−23 or catalyst-free growth.24−28 In the case of self-catalyzed growth, one or more NW elements, usually In19 or Ga20 droplets, are used as the seed nanoparticles; thus, it is also categorized as VLS growth. On the other hand, no catalyst is used during the nucleation and growth for the catalyst-free method. For example, selective-area growth uses partially masked substrate, usually by an oxide or nitride layer, with lithographically defined opening pattern.24−26 Consequently, semiconductor materials nucleate and initiate NW growth in the openings after increasing the temperature and introducing the reactant precursors. It is also reported that coating of the Si substrate with a layer of organic materials allows nucleation of direct growth of InAs NWs without the use Received: June 28, 2013 Revised: December 4, 2013 Published: December 6, 2013 1696

dx.doi.org/10.1021/jp406428z | J. Phys. Chem. C 2014, 118, 1696−1705

The Journal of Physical Chemistry C

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Figure 1. Flowchart of surface treatment of Si substrates for catalyst-free InAs NW growth.

of catalysts.27 By careful surface treatment but without the use of any predeposited materials or mask, we reported previously a simple catalyst-free growth of III−V NWs on Si substrates.28 In this article, we report a systematic study of the simple direct heteroepitaxial and catalyst-free growth of vertically aligned InAs NWs, on cheap and large-scale Si substrates using metal−organic chemical vapor deposition (MOCVD) method. We studied the effects of various substrate surface preparations and growth parameters on the InAs NW growth yield and morphology. The morphology and structural properties of the NWs were investigated by field-emission scanning electron microscope (SEM), transmission electron microscope (TEM), and selective-area electron diffraction (SAED). The properties of NW/substrate interface are examined by high-resolution cross-sectional TEM. This article aims to develop understanding of the growth mechanism. Single InAs NW back-gate FETs and NW array-based photodiodes are fabricated and characterized to reveal the electronic and optoelectronic properties of the NWs, as well as to illustrate the device applications.

N2 and immediately loaded into a MOCVD chamber for NW growth. 2.2. InAs NW Growth on Si. The InAs NW growth was carried out in a low-pressure close-coupled showerhead (CCS) MOCVD system (Thomas Swan Scientific Equipment Ltd.). The carrier gas used was pure H2 that was purified through a Pd membrane. The precursors for group V and group III materials were 5% H2 diluted arsine (AsH3) and trimethylindium (TMI), respectively. After solvents cleaning and surface preparation processes as described above, the Si substrates were immediately loaded into MOCVD reactor chamber. Unless specifically stated, the NW growth was done as the following. Prior to growth, the Si substrates were annealed at 635 °C for 10 min in H2 ambient. Then the reactor was cooled down to the growth temperature of 550 °C. As soon as the growth temperature was stabilized, the AsH3 and TMI were introduced into the reactor simultaneously to initiate InAs growth. The mole fractions of AsH3 and TMI were 2 × 10−4 and 2 × 10−6, respectively. The chamber pressure was maintained at 100 torr during growth, and the total flow rate of H2 carrier gas was 20 standard L/min. The growth was terminated by shutting off the TMI flow while maintaining AsH3 flow until the reactor was cooled down to below 300 °C to prevent decomposition of InAs NWs. 2.3. Structure Characterization. The morphology of the as-grown NWs was observed by a SEM (Philips XL30) and a high-solution TEM. The crystal structure was studied by SAED. The cross-sectional TEM (JEOL 3000F) was carried out on InAs NWs grown on Si(111) to investigate the NW/substrate interface. For cross-sectional TEM analysis, the as-grown NWs were fully embedded in poly(dimethylglutarimide) polymer (PMGI, MicroChem) by spin-coating and micromachined by ion-milling. 2.4. Single NW FET Fabrication. For single NW device fabrication, the as-grown InAs NWs were dispersed in IPA using ultrasonication. Then the NWs were transferred onto Si substrate with 600 nm thermally grown SiO2 by applying a few

2. EXPERIMENTAL SECTION 2.1. Si Surface Preparation. The substrate surface preparation is critical to achieve catalyst-free growth of InAs NW arrays on Si with high reproducibility and good coverage. Si(111) wafers were cut into 1 × 1 cm2 size for NW growth. The Si substrates were first cleaned with solvents in an ultrasonic bath. Then the Si surface was treated differently for InAs NW growth, as illustrated by the flowchart in Figure 1, including (i) Si substrates with native oxide or 100 nm thick thermally grown SiO2; (ii) Si surface treated with BOE etching and deionized (DI) water rinsing for different lengths of time; (iii) Si surface treated with BOE etching and isopropyl alcohol (IPA) rinsing; (iv) Si surface treated with BOE etching and reoxidation in humid air; (v) Si surface treated with ozone plasma and BOE etching, followed by InAs growth with or without prebaking in H2. The treated substrates were dried with 1697



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Figure 2. SEM images of InAs grown on Si(111) at 45° tilted view. The growth was done at 550 °C for 5 min. Prior to growth, the substrates were prebaked in H2 at 635 °C for 10 min, unless otherwise specified. (a−d) Si substrates were cleaned, BOE etched for 1 s (a), 3 s (b), 30 s (c), and 2 min (d), and rinsed with DI water for 15 s. (e−h) Substrates were treated with ozone plasma, BOE etched for 1 s (e), 3 s (f), 5 s (g), and 30 s (h), and rinsed in DI water for 15 s. (i−k) Substrates were treated with ozone plasma, BOE etched for 1 s (i), 10 s (j), and 30 s (k), and rinsed in DI water for 15 s, except no prebaking was performed. (l) Si substrate with 100 nm thermal SiO2 and (m) Si substrate with native oxide.

islands and nonvertical NWs decreases (Figures 2b, c); when the BOE etching time is longer than 30 s, there is no significant change of islands density when etching time is further increased (Figures 2c, d). This result indicated that the native oxide was completely removed when etched in BOE for 30 s and prebaked in H2 for 10 min, exposing the oxide-free Si surface, which was favorable for InAs NW nucleation. We have also tried, prior to the etching, ozone plasma treatment of the Si substrates, which can remove organic contamination on the Si surface as well as increasing the oxide thickness. Figures 2e−h illustrate the SEM images of a set of samples which were treated with ozone plasma and BOE etching with different times. Compared to the samples without ozone treatment (Figure 2a), the growth done with ozone treatment shows reduced density of islands. The sample with 1 s BOE etch shows no significant change of density of nonvertical NWs. However, the sample with 3 s BOE exhibits much larger density of nonvertical NWs. The density of islands and nonvertical NWs almost diminished for the growth done with 30 s BOE etching, which can be probably attributed to the fact that there is less organic contamination on Si surface after ozone treatment and substrates have a clean and oxide-free surface for NW nucleation. These results suggest that complete removal of native oxide by BOE etching is critical to InAs NW growth. However, there are two other factors to be considered regarding the coverage of native oxide on the Si surface during the NW growth practice. (1) The DI water rinsing may also play a role, as there could be the regrowth of native oxide from Si oxidation in water. Growth under identical conditions on a substrate without DI water rinse cannot be performed due to the nature of HF handling and potential contaminants from the etchant residues. (2) The prebaking practice in H2 at 635 °C prior to the NW growth may reduce the native oxide thickness. Thus we hypothesize that the oxide-free Si surface enables the

drops of the solution on the surface. E-beam lithography followed by lift-off metallization was performed to deposit metal electrodes (Ti/Al) on the two ends of the NWs. 2.5. InAs NW Array-Based Photodetector Fabrication and Measurement. N-type InAs NWs were grown on the ptype Si substrate to form a p−n heterojunction. The as-grown InAs NW array on p-SI substrate was embedded in transparent PMGI by spin-coating. Oxygen RIE etching was employed to remove excess polymer to expose the NW tips, followed by sputtering of indium tin oxide (ITO) as front contact and soldering of indium on the backside of Si substrate as back electrode. Current−voltage (I−V) measurements were carried out under illumination of a tungsten bulb (color temperature 3000 K and integrated power density 24.2 mW/cm2) and using different long-pass filters, which were used to separate the photoresponse from different spectral regions.

3. RESULTS AND DISCUSSION 3.1. InAs NWs Growth on Si (111). To find out the optimal growth conditions and understand the growth mechanism, the effects of Si surface conditions on the InAs NW growth were investigated. We first studied the growth of InAs NWs under identical growth conditions (prebaking in H2 at 635 °C for 10 min, followed by InAs NW growth at 550 °C for 5 min) on Si substrates with different etching times of the native oxide. The SEM images of InAs NWs grown on Si with various BOE etching times (1 s, 3 s, 30 s, and 2 min) are shown in Figures 2a−d. The DI water rinsing time is 15 s for this set of samples. As can be seen, vertical InAs NWs were observed on Si after removal of native oxide by BOE regardless of the lengths of etching time. In the case of 1 s BOE etching (Figure 2a), in addition to vertical NW growth, the presence of a large density of InAs islands and nonvertical NWs was observed as well. As the BOE etching time increases, the density of InAs 1698



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Figure 3. SEM images of InAs grown on Si(111) with 45° viewing angle. The growth was done at 550 °C for 5 min with substrate baking in H2 at 635 °C for 10 min prior to growth, unless otherwise specified. Scale bars are 1 μm. (a−d) Si substrates were cleaned, BOE etched for 1 s, and rinsed with DI water for 1 s (a), 4 min (b), and 8 min (c), and ultrasonication in DI water for 4 min (d). (e−g) substrate surface was BOE etched for 3 s (e), 20 s (f), and 30 s (g), respectively, and rinsed in running DI water for 8 min. (h) Surface treatment with 20 s BOE etching and 4 min DI water rinse, but with 10 min growth. (i) Substrate surface was BOE etched for 30 s, quickly rinsed with DI water, and rinsed with IPA for 4 min. (j−l) Si surface etched for 30 s and rinsed with DI water for 15 s, reoxidized in humid air for 12 h (j), 24 h (k), and 130 h (535 °C growth) (l), respectively.

and decreasing density of islands with DI water rinsing time. Interesting, ultrasonication in DI water (Figure 3d) showed similar effect with running DI water rinsing (Figure 4a). It appears that rinsing with running DI water for 8 min gives the

initial nucleation of InAs islands while the oxide patches hinder the formation of large InAs islands and lead to NW growth, which is in line with the proposed catalyst-free III−V NW growth on Si substrates.24 The coverage of the oxide patches strongly depends on the surface preparation methods, including BOE etching, DI water rinsing, ozone plasma treatment, and prebaking. To test this hypothesis, InAs NW growth without substrates prebaking was carried out. Interestingly, no NWs but only InAs island growth (Figure 2i and inset) was observed on the samples treated with ozone plasma and 1 s BOE etching, similar to the cases of that on native oxide (Figure 2m) and thermal oxide surface (Figure 2l), which is presumably due to the fact that 1 s BOE etching alone without H2 reduction during the prebaking step is not sufficient to remove all the native oxide and expose Si(111) surface. Even on substrate with 3 s BOE etching, it still shows high density of nonvertical NWs and islands (Figure 2j), results which are similar to that from growth with 1 s BOE etching and H2 prebaking (Figure 2e). These results clearly suggest that prebaking in H2 has an equivalent effect to BOE etching. The yield and morphology of InAs NWs on the substrate when BOE etching time is above 30 s (Figure 2k) become comparable to those with prebaking in H2 (Figure 2c). To further understand the surface treatment effects, we also studied the rinsing effect with DI water or IPA after BOE etching for different times, as well as the oxide regrowth after etching. Figures 3a−d show the SEM images of InAs grown at 550 °C for 5 min with substrate prebaking in H2 at 635 °C for 10 min. The Si substrates were cleaned, BOE etched for 1 s, and rinsed with DI water for 1 s (a), 4 min (b), and 8 min (c), and ultrasonication in DI water for 4 min (d), respectively. There is a clear trend of increasing density of vertical InAs NWs

Figure 4. (a) SEM images of InAs NWs grown for 5 min on Si(111) substrate at 75° angle view and top view (inset). Si was treated with BOE etch for 30 s and rinsed in running DI water for 8 min. (b) Column graph showing distribution of NW diameters. 1699



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water for 8 min. The InAs NWs are vertically aligned to the surface, indicating epitaxial growth along the [111] orientation, and with uniform coverage on Si substrate. The diameters of InAs NWs are in the range of 30−80 nm, and the lengths range from 1.2 to 4.5 μm, with a majority around 2−3.5 μm (Figure 4b). The InAs NWs exhibit hexagonal cross section and smooth sidewall surface. From the Si(111) cleavage, we can figure out that side facets of the NWs are {110}. The inset of Figure 4a shows the top view of the NWs. Figure 4a shows uniform diameter of NWs without measurable tapering or large base at NW/substrate interface. It is different from InAs NWs grown with Au catalysts, which sometimes show large base surrounding NW foot and are tapered when length is over the indium diffusion length (∼1 μm).8,30 The morphology of the InAs NWs is similar to those grown with selective-area MOCVD method.24,25,27 However, the selective-area method requires a partially masked template with nanoscale opening patterns, where NWs nucleate and grow without assistance of metal catalyst. The template is usually patterned by electronbeam lithography,25,31 which is a slow and expensive process and hardly scalable. Nucleation template formed by selfassembled organic coating27 and nanosphere lithography32 have been employed in selective-area growth to achieve large-area III−V NW array. The simple oxide-assisted growth reported here requires no predefined mask layer and thus can be easily scaled up. Wafer-scale InAs NW array has been successfully synthesized on 2-in. Si(111) wafers with uniform coverage, and no noticeable difference was observed on NW morphology compared to growth on small Si substrates. Note that further investigation is required to achieve precise control of the diameter, length, and location of NWs. Figure 5 illustrates the TEM study of the crystal structure of InAs NWs. The low-resolution image (Figure 5a) shows that the NWs are very uniform in diameter, without any visible tapering. However, the NW diameters vary from NW to NW. The high-resolution TEM (HRTEM) (Figure 5b) and SAED (Figure 5a inset) reveal that the NW has a zinc blende crystal structure and grows along the [111] direction, with a high-

best result regarding the vertical NW density and morphology. We thus then compared the growth on substrates with different BOE etching times (3 s in Figure 3e, 20 s in Figure 3f, and 30 s in Figure 3g) and the same rinsing time of 8 min. These results are very comparable with that of BOE etching for 1 s (Figure 3c), and there is no strong indication of etching time effecting the vertical NW growth and morphology. However, stronger contrast was observed for the NW growth on Si substrates with IPA rinsing after BOE etching, where presumably there is no regrowth of native oxide. With identical surface treatment, longer growth time resulted in correspondingly similar morphology, longer NWs and larger length variation, and higher density. Figure 3h shows the SME image of the growth with 20 s BOE etching and 4 min DI water rinse, but with 10 min growth (vs Figure 3f). These results indicated that new nucleation of new NWs occurs during the growth, leading to larger variation of the NW length and diameter, and much longer NWs. The NWs are uniform in diameters along the axial direction. Figure 3i shows the SEM image of InAs NW growth on Si substrates with surface treated by BOE etching for 30 s, a rapid DI water rinsing, and IPA rinsing for 4 min, where very few short InAs NWs are grown with formation of mainly irregular islands (in comparison with Figures 3b, 3e). Because IPA rinsing prevents formation of oxide patches, the InAs islands initially nucleated on oxide-free Si surface tend to grow into larger islands instead of NWs. We have also tested the NW growth on substrate with controlled regrowth of native oxide (with different thicknesses), where the Si wafers were first etched with BOE to remove the native oxide and exposed to humid air (85% relative humidity at room temperature) for different lengths of time. Formation of islands and nonvertical NWs was insignificant on Si reoxidized for 12 h (Figure 3j). However, as reoxidation time increased, density of islands and nonvertical NWs increases dramatically and dominates after 130 h (Figures 3k and 3l).28 These results, consistent with those reported,29 can be categorized as the following: (1) growth on Si without oxide (BOE treated with short DI water rinsing time) results in vertical NWs dominated growth with a relatively high density of nonvertical NWs and islands; (2) growth on Si with thin oxide patches (BOE treated with 8 min DI water rinsing) leads to high-yield vertical NW growth, almost free of parasitic islands and nonvertical NW growth; (3) growth on thicker oxide (regrown oxide in humid air for 130 h) causes islands and nonvertical NWs dominated growth; (4) no NW but islands grow on thermal SiO2 or native oxide. These results further demonstrate that oxide layer thickness and coverage play a critical role in the growth quality and morphology of InAs NWs and suggest an oxide-assisted NW growth. The BOE etch and prebaking can reduce the oxide thickness while humid air, ozone plasma, and DI water rinsing can reoxidize Si and form oxide patches. The key to achieve high-yield vertical InAs NW growth is to have oxide-free Si surface for NW nucleation and oxide patches to hinder formation of large InAs islands. We have identified the optimal growth condition for catalyst-free growth on Si of vertical InAs NW array with minimal density of islands and nonvertical NWs, uniform coverage, and high reproducibility. The best results were achieved on BOE treated Si surface with 4−8 min DI water rinsing. Figure 4 shows the SEM images of InAs NWs grown on Si(111) substrates prepared using the optimal surface treatment conditionswith BOE etch for 30 s and rinsed in running DI

Figure 5. Transmission electron micrographs of InAs NWs. (a) Lowresolution image of InAs NWs; the corresponding electron diffraction pattern is shown in the inset (⟨111⟩ growth orientation). (b) Highresolution image of the bottom portion of an InAs NW. (c) Highresolution image of top portion of an InAs NW. 1700



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Figure 6. Cross-sectional TEM images of InAs NWs grown for 5 min on Si(111). (a) Low-resolution TEM showing InAs embedded in PMGI polymer. (b) High-resolution TEM of the central region of InAs/Si interface. (c) High-resolution TEM of the edge of InAs/Si interface. Fast Fourier transform (FFT) of (d) region I (zinc-blende InAs with a rotational twin plane), (e) region II (zinc-blende InAs), (f) region III (overlay of InAs and Si patterns; white arrow indicates an InAs spot and red arrow indicates a Si spot), (g) region IV (Si substrate).

InAs NWs usually exhibit large base at NW root and are tapered when length is over indium diffusion length,8,30 which were not observed in our study. This result indicates the growth is not governed by VLS mechanism. This is further corroborated by in situ reflection high-energy electron diffraction (RHEED) studies reported by Hertenberger et al,41 showing InAs NWs nucleation under the absence of indium droplets and without any significant delay after introducing the precursors. The InAs NW growth is believed to obey the Volmer− Weber growth mode.42,43 Owing to the large lattice mismatch between Si and InAs (11.6%), 3D InAs islands spontaneously nucleate on the atomically flat and oxide-free Si(111) surface pretreated with BOE. In-plane InAs thin film growth is prevented because of the large interfacial energy, resulting in NW growth along the [111] orientation, so that the strain can be relaxed laterally.44−46 Only the InAs islands with sizes smaller than the critical diameter enable epitaxial NW growth.44−46 The NW density strongly depends on the coverage of oxide patches on Si surface formed during the substrate preparation process. On a completely oxide-free surface treated with BOE etch, the indium adatoms are very mobile and large InAs islands form quickly, hindering vertical NW growth. Under optimal conditions, when, after BOE etch,

density of twin planes and stacking faults, whereby the crystal structure alternates between zinc blende and wurtzite over the entire NW length. No metal droplet is observed on the NW tip (Figure 5c), differing from NWs grown by catalytic or selfcatalytic methods.33 The growth mechanisms to realize catalyst-free III−V NW growth include selective-area growth24 and self-catalyzed VLS growth.33,34 The selective-area growth is initiated by the nucleation of InAs inside predefined opening in the dielectric layer. On the contrary, in our method, vertical InAs NWs can grow on oxide-free Si(111) surface. After BOE etch, the native oxide was removed to expose the atomically flat Si surface. Simultaneously, the Si surface was passviated by hydrogen bonds, preventing the formation of new oxide at least within a few minutes.35−37 This reveals a different growth mechanism from selective-area growth. On the other hand, self-catalyzed VLS growth relies on the formation of indium or gallium droplets to initiate NW growth.22,23,38,39 In our study, no indium droplet was noticed at the apex of NW. Nontapered geometries of InAs NWs excludes the possibility of consumption and crystallization of indium droplets by excess AsH3 during postgrowth cooling, since diminishment and eventual disappearance of metal catalysts would result in tapered NWs with sharp tips.40 On the other hand, VLS grown 1701



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to the central spot than Si spots as illustrated in Figure 6f, since InAs has a larger lattice constant (6.0583 Å) than Si (5.431 Å). 3.2. Single NW Electrical Properties and InAs NW Array on Si-Based Photodetector. The electrical properties of the InAs NWs were characterized by single NW back-gate FET measurements.53,54 The Ids−Vds curves and SEM image of a typical device are shown in Figure 7a and the inset. Ohmic

the substrate is rinsed with DI water for a few minutes, SiOx patches form on the surface. The indium adatoms are immobile on Si surface with SiOx patches in contrast to that on clean oxide-free surface. The SiOx patches reduce the probability of the formation of large InAs islands, leading to higher NW density. III−V NWs typically grow preferentially alongthe [111]B direction; thus, vertical NWs form on (111)B surface of III−V substrates. Si has nonpolar nature, and there are four equivalent [111] directions on the Si(111) surface; one is along vertical direction and the other directions are 19.6° tilted with respect to the (111) surface.47 Our results show that the InAs NWs grow predominately along vertical [111] direction rather than the other three equivalent [111] directions. This is most likely due to the passivation of Si dangling bonds with As atoms when substrate surface is exposed to AsH3 prior to growth.24,48 Once As-incorporated Si has formed on surface, which mimics the (111)B surface of III−V semiconductors, only vertical NWs are allowed to grow on Si(111). The cross-sectional TEM was carried out on InAs NWs grown on Si(111) to investigate the NW/substrate interface. Figure 6a is a low-resolution TEM image, showing an InAs NW perpendicular to the Si substrate. A magnified HRTEM image of NW/substrate interface (Figure 6b) taken in the near-center region shows that InAs NW was epitaxially grown on Si(111), with an almost atomically flat interface between the InAs NW and Si substrate. Figures 6d−g show the fast Fourier transform (FFT) patterns of the selected region of the InAs/Si interface in Figure 6b. The white arrow indicates the NW growth direction. Both the HRTEM (Figure 6b) and fast Fourier transform from region II (FFT, Figure 6e) reveal a zinc-blende crystal structure at NW base, with a low density of defects. After a region of 10 nm zinc-blende InAs, rotational twinning started to appear, as indicated by the red arrow in Figure 6b. The streaking in FFT pattern from region I (Figure 6d) implies the presence of defects in this region. A high density of twin planes and stacking faults began to form after growth of an 18 nm lowdensity defect region. The defects were observed along the entire NW length, as aforementioned. The mixture of zincblende and wurtzite structures are typically observed in III−V NWs due to the small difference in the internal energy of the two structures.24,49−51 It is possible to favor one of the structures by turning the growth conditions. For instance, growth of defect-free InAs NWs with pure zinc-blende or wurtzite phase has been achieved by controlling the NW diameter and growth temperature in the case of Au-assisted VLS method.52 To our best knowledge, defect-free InAs NW grown by catalyst-free method has not been reported. Figure 6c shows the presence of a thin (1−3 nm) amorphous layer at the edge of the heterogeneous interface, which was also observed by Cantoro et al.48 This was attributed to the reoxidation of the Si surface. In contrast, no oxide was observed in the central region of NW/substrate interface (Figure 6b). This result further confirms our proposed growth mechanism that oxidefree Si surface enables the initial nucleation of InAs islands and SiOx patches hinder formation of large islands to facilitate NW growth. FFT of region III results in an overlay of the Si (region IV) and InAs (region II) patterns. Because Si substrate and zinc-blende InAs NW have similar crystal structure (the diamond structure is identical to the zinc-blende structure with the exception that each atomic side is populated by the same atom) and the same orientation, the FFTs of region IV and II look similar. However, the InAs spots are located closer

Figure 7. (a) Ids−Vds measurements of a single InAs NW FET using a bottom-gate structure; inset is a SEM image of the device. (b) Characterization of the n-InAs/p-Si heterojunction device made with an active area of ∼10 mm2 under the illumination of tungsten light with different filters. Without filter, the light power density is 24.2 mW/cm2. With long-pass filter (>1200 nm) and long-pass filter (>1900 nm), the power density is 3.18 and 0.96 mW/cm2, respectively. Inset shows the schematic diagram of the device (right) and a rectified I−V curve in dark (left).

contacts were formed between the NWs and the electrodes. The InAs NWs exhibited typical n-type FET behavior. The average resistivity was calculated to be 1.5 × 10−3 Ω·cm on seven measured devices. The contact resistance was neglected for the calculation as Fermi-level pinning above the conductionband edge of InAs enabled the formation of low-resistance ohmic contact to the InAs NWs.55 By using the commonly used single NW back-gate FET model, the average electron mobility and concentration were estimated to be around 1000 cm2/V·s and 1018−1019 cm−3, respectively.53,54 These values are comparable to those of InAs NWs grown using catalytic VLS growth.56 A photodetector based on vertical n-type InAs NWs grown on p-type Si substrate (∼1 × 1015 cm−3) was fabricated to study the optoelectronic properties of the heterostructure. The 1702



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Present Addresses

schematic of device structure is illustrated in the right inset of Figure 7b.24 The rectified I−V characteristics shown in the left inset of Figure 7b confirm the formation of p-n heterojunction between n-InAs NWs and p-Si substrate. Owing to the nature of heterostructure, this device is expected to show photosensitivity in both the visible and the infrared portions of the spectrum; i.e., both photons absorbed in Si (λ < 1200 nm) and in InAs (λ < 3500 nm) are expected to contribute to the photoresponse. The absorption near the heterojunction within the minority carrier diffusion length in InAs NWs and Si to the depletion region will contribute to the photocurrent of the heterojunction device. The current as a function of reverse bias voltage is shown in Figure 7b in logarithmic scale for different irradiation conditions: in the dark and under illumination using the full spectrum of the white light lamp (no filter), the nearmedium infrared portion with long-pass filter (>1200 nm), or just the medium infrared portion with long-pass filter (>1900 nm). Under illumination of full spectrum, a significant photoresponse was observed with ON/OFF ratio of 3 000− 100 000 at different reverse biasing voltages. The photoresponse ON/OFF ratio to light with wavelength above 1900 nm is about 3−40 and to light with wavelength above 1200 nm is about 80−3000, which shows the strong infrared response contributed from InAs. Since reflectivity and transmission losses of the long-pass filters used in the experiments were not taken into account, these ON/OFF ratios represents a lower limit for the contribution to the photocurrent from the InAs NWs. These heterojunction devices respond to a wide spectrum of light, up to 3.5 μm, on Si platforms, indicating the potential applications for broadband photodetection for image sensing and optical interconnects for Si photonics and optical computing.

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X.B.: Applied Materials, Santa Clara, CA 95054, U.S. W.W.: Department of Applied Physics and Material Science, California Institute of Technology, Pasadena, CA 91125, U.S. Ø C.L.: School of Optoelectronics, University of Electronic Science and Technology of China, 610054 Chengdu, China. ±

Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS D.W. acknowledges the Office of Naval Research (N00014-050149), the National Science Foundation (ESC-0506902, ARRA ECCS0901113, and CBET1236155), and the Department of Energy (DE-FG36-08GO18016) for financial support. D.W. also thanks Drs. R. Rao and B. Fruhberger of QI of UCSD for their unconditional support. The authors acknowledge the staff of NANO3 facilities for their timely and professional support.

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4. CONCLUSION In conclusion, a catalyst-free approach for heteroepitaxial growth of InAs NWs on Si substrates was systematically studied with the focus on varying the surface preparation and growth parameters. An optimal surface treatment and growth condition for high-quality vertical InAs NWs is developed. The growth mechanism was proposed that by BOE etch and DI water rinsing of the Si substrate, oxide patches are formed on the surface, from which InAs can nucleate at the oxide-free regions while the oxide patches hinder the formation of large InAs islands to facilitate the NW growth. The uniform InAs NWs have a zinc-blende structure with a high density of twin planes and stacking faults and grow along the ⟨111⟩ direction with no measurable tapering. Cross-sectional TEM study shows the interfere properties and reveals the epitaxial nature of the InAs NW growth on Si. Single InAs NW FETs were fabricated, and the average electron mobility and concentration were estimated to be around 1000 cm2/(V s) and 1018−1019 cm−3, respectively. The n-InAs/p-Si heterojunctions show rectified I− V characteristics, and preliminary results indicate potential applications for broadband photodetection. The findings are potentially applicable to other III/V compound semiconductor NWs for broader applications in electronics and optoelectronics.

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