Controllable Fabrication of Pyramidal Silicon Nanopore Arrays and

Article pubs.acs.org/JPCC

Controllable Fabrication of Pyramidal Silicon Nanopore Arrays and Nanoslits for Nanostencil Lithography Tao Deng,† Mengwei Li,†,‡ Jian Chen,§ Yifan Wang,† and Zewen Liu*,† †

Institute of Microelectronics, Tsinghua University, Beijing 100084, China Key Laboratory of Instrument Science & Dynamic Measurement (North University of China), Ministry of Education, Taiyuan 030051, China § South-West Institute of Technical Physics, Chengdu 610041, China ‡

S Supporting Information *

ABSTRACT: This paper presents a controllable method for the highthroughout fabrication of pyramidal silicon nanopore arrays (PSNAs). Using this method, square nanopore arrays with an average size of 60 nm, rectangular nanopores with different length−width ratios, and nanoslits with feature sizes as small as 13 nm were created. Focused ion beam (FIB) cutting experiments showed that the inner structure of the nanopore was exactly pyramidal, which offered unique ionic rectification properties. Moreover, preliminary nanostencil lithography experiments indicated that such PSNAs could be used as reusable masks to directly deposit large-scale surface patterns in both nano and micro scales, and with less time and low cost.

I. INTRODUCTION The idea of using α-hemolysin protein nanopores to characterize biological molecules inspired the fabrication and application of solid-state nanopores.1,2 Solid-state nanopores are mechanically robust and durable and allow facile integration with existing Si-based electronic and micromechanical devices.3−5 Especially, conical or pyramidal nanopores formed in semiconducting substrates such as silicon (Si) possess unique ionic rectification properties,6 which offer the possibility of voltagegated control of transmembrane ionic and molecular transport.7,8 Therefore, solid-state nanopores have grown to be a platform for biomolecular analysis.9,10 Besides the bioapplications, solid-state nanopores, especially nanopore arrays, can also be used in the nanostencil lithography11,12 area, which is a shadow-mask patterning technique that is widely used in microelectronics.13 Since the first fabrication of an artificial solid-state nanopore with true nanometer control dates to 2001,14 a lot of nanopore fabrication techniques have been reported, such as the tracketching method.15 Nowadays, the most popular techniques are ion- and electron-beam sculpting. Ion-beam sculpting was proposed by Li and co-workers.14 They developed a focused ion beam (FIB) machine that uses ions to mill a tiny hole in a silicon nitride membrane, and tuned (shrink or enlarge) the pore diameters by controlling the ion rate and temperature. Dekker’s group developed electron-beam sculpting based on electron-beam lithography followed by etching.16 They modified the pore size by exposure of the nanopore to a high-intensity wide-field illumination. After that, several other © 2014 American Chemical Society

groups reported the use of a transmission electron microscope (TEM) to drill nanopores in thin membranes without the electron-beam lithography.17−19 With these methods, nanopores with sizes down to 1 nm have been created in suspended insulating oxides and semiconductive materials, even in conductive materials such as graphene layers.20 However, these nanopore fabrication methods always require expensive equipment such as TEM or FIB, or access to heavy ion accelerators. Furthermore, their throughput is pretty low, because each nanopore can only be generated in a serial manner.21,22 To fabricate solid-state nanopore arrays on a large scale, many etching techniques have been proposed. One of the widely utilized techniques is metal-assisted chemical etching (MACE), which can be used to fabricate Si conical nanopore arrays with diameters as small as 5 nm.23−25 Another promising method is the metal-assisted plasma etching (MAPE) proposed by the Gracias group, which can be utilized to fabricate conical nanopore arrays in Si membranes and other crystals with variable pore diameters and cone angles.26 Using this method, they have created conical nanopore arrays with diameters around 20 nm, realized nanopore-based ionic switches, and demonstrated voltage-gated control over protein transport. However, it is difficult to fabricate square and rectangular nanopore arrays or other complicated nanopore-like structures Received: April 1, 2014 Revised: July 7, 2014 Published: July 11, 2014 18110

dx.doi.org/10.1021/jp503203b | J. Phys. Chem. C 2014, 118, 18110−18115

The Journal of Physical Chemistry C

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more controllable, a homemade feedback wet etching apparatus combined with a color indicator were specially designed and used, as shown in Figure 1e. During this process, the small silicon chip divided the apparatus into two chambers. The upper chamber contained the wet etching solution, while the lower one contained the color indicator (phenolphthalein). Once the nanopore array was successfully opened, the etching solution and the color indicator would meet and interact with each other, leading to the change of the solution color immediately. Thus, the nanopore opening process becomes indirectly visible. In addition, by using the feedback wet etching apparatus, the complex radius control equation (shown in our previous work27) can be significantly simplified to be

using these techniques, which limits their application in the nanostencil lithography field. In this paper, a controllable wet etching method for the highthroughout fabrication of pyramidal silicon nanopore arrays was demonstrated. Square nanopore arrays with an average size of 60 nm and rectangular nanopores with different length−width ratios, as well as nanoslits with sizes as small as 13 nm, were obtained. FIB cutting experiments were conducted to investigate the inner structure of the nanopores. Furthermore, preliminary nanostencil lithography experiments indicated that such pyramidal silicon nanopore arrays could be used as reusable nanostencils to directly fabricate massive surface patterns on any substrates in both nano and micro scales.

II. EXPERIMENTS The improved fabrication process of nanopore arrays is shown in Figure 1. First, after being cleaned, the 4 in. P-type (100)

R=

V(100) − 30 cos θ + V(111) − 30 sin θ

(t + t0)

(1)

where V(100)‑30 and V(111)‑30 are the etch rates of Si (100) and (111) planes at 30 °C in the KOH solution, θ is the included angle between the crystalline Si (100) and (111) planes, and t0 is the time delay from the opening of the nanopore array to the detection of the changed color of the indicator. Depending on the desired pore size, at a certain etching time t from the color changing event, one can terminate the etching process and remove the Si sample from the etching apparatus, then clean it with deionized water. In this way, the nanopore size can be precisely controlled. The wet etching solution was a 32% (wt) KOH solution with added isopropanol (IPA) (KOH/water/IPA = 50 g/100 mL/5 mL). The wet etching was carried out in a magnetic stirring bath, with a temperature error of ±0.1 °C. As shown in Figure S1 in the Supporting Information, the average etching rates of (100) plane of bulk silicon in 32 wt % KOH at 60 and 30 °C were 476.5 nm/min and 59.6 nm/min, respectively. Under the same conditions, the average etching rates of (111) plane were about 1 in 400 of the (100) plane etching rates. Thus, the influence of (111) plane etching in the stage of lowtemperature wet etching was trivial and negligible. The etch behavior of PDMS against KOH can be found in Table S1 and Figure S2 in the Supporting Information. After the fabrication, the nanopore samples were measured using an environmental scanning electron microscope (FEI Quanta 200 ESEM FEG) operating at a beam voltage of 15 kV in high-vacuum mode. The spatial resolution of the ESEM was 2.1 nm.

Figure 1. Schematic illustration of the nanopore array fabrication: (a) deposit mask layers; (b) lithography; (c) create inverted pyramid array using wet etching at 60 °C; (d) back-side thinning; (e) open nanopore array using wet etching at 30 °C; (f) remove the mask layers.

double-side-polished single-crystalline silicon wafer was coated with a layer of Cr (300 nm) on the top side, to form the wet etching mask, and a layer of Si3N4 (700 nm) was coated on the bottom side to provide the back-side thinning mask. Then, the wet etching windows with different sizes and different length− width ratios, and the back-side thinning windows with a size of 1500 μm, were patterned using dual side photolithographic process. Exposed Cr and Si3N4 were removed in a ceric ammonium nitrate solution and CF4/SF6 plasma, respectively. In the third step, the wafer was wet etched from the top side, at 60 °C, to generate an inverted pyramid array. Then, either inductive coupled plasma (ICP)27 or high-temperature (70−80 °C) wet etching28 was performed from the bottom side, to reduce the thickness of the wafer. After this step, the whole wafer was cut into small chips with a size of 15 mm × 15 mm. The small chip was assembled into a homemade apparatus, and low-temperature wet etching at 30 °C was performed from its bottom side to precisely etch away the silicon layer by layer, until the nanopore array was produced at the tips of the inverted pyramid array. Finally, the Cr and Si3N4 masks were removed, and the silicon nanopore array was obtained. Among these processes, the low-temperature (30 °C) wet etching plays the most important role in opening the nanopore array and determining its size. To make this process visible and

III. RESULTS AND DISCUSSION Figure 2 shows a 5 × 5 inverted pyramid array imaged from both top and bottom sides, where the pitch between every two pyramids is 5.5 μm and the bottom size of the etch pyramid is 4 μm × 4 μm. It can be seen that all of the inverted pyramids were successfully fabricated after the first wet etching at 60 °C, as shown in Figure 2a. Every white dot in Figure 2b represents a tip of an inverted pyramid, namely, a nanopore to be opened. According to the experimental experience, the brighter dots (as shown in the solid-line circle) will be opened sooner, while the darker ones (as shown in the dotted-line circle) will be opened later, in the following wet etching at 30 °C. The brightness of the white dots in Figure 2b is not very uniform, which reflects that the remaining silicon membrane after the back-side thinning is uneven and may lead to nonuniform nanopore arrays. 18111



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nonuniformity of the wet etching masks. To fabricate largescale nanopore arrays with exactly uniform size, silicon-oninsulator (SOI) wafers whose device layer (namely, the top Si layer) thickness can be very uniform, will be utilized in the near future. In addition, more precise lithography techniques such as electron-beam lithography and laser-beam lithography can be used to fabricate the lithography masks. Figure 3d demonstrates the variation of the average nanopore size with etching time. The linear fit of the experimental data indicates that the nanopore opening rate is ∼13 nm/min, a precise control of the nanopore size by determining the etching time. Besides square nanopores, rectangular naonopores with smaller feature sizes (defined as the smaller one of the length and width) were also obtained by properly designing the length−width ratio of the wet etching masks. Figure 4a shows a

Figure 2. SEM micrographs of a 5 × 5 inverted pyramid array (unopened nanopore array) imaged from (a) the top side and (b) the bottom side.

With the performance of the wet etching at 30 °C, the silicon membrane above the inverted pyramid array will be etched away layer by layer, until the nanopores at the tips of the inverted pyramid array are opened to a desired size. Figure 3a,b

Figure 4. SEM micrographs of rectangular nanopores and nanoslits: (a) a rectangular nanopore with the size of 25 nm × 50 nm; (b) a nanoslit with the size of 222 nm × 13 nm; (c) and (d) a nanoslit array and its details.

rectangular nanopore with the size of 25 nm × 50 nm. By further increasing the length−width ratio of the wet etching masks, narrower nanopores, even nanoslits, were fabricated. The feature size of the nanoslits could be down to 13 nm, as shown in Figure 4b. Figure 4c,d demonstrates a nanoslit array with a length−width ratio of 6:1 and an average feature size of 20 nm. Although rectangular nanopores and even nanoslits with feature sizes in the range of 10−20 nm can be fabricated, it is difficult to create square nanopores in the same size range. Only when the opening area (defined as length × width) of the nanopore reaches a certain number (∼2000−3000 nm2, in our experiments) can sufficient etching solution meet and react with the color indicator, resulting in the color change event and the ending of the etching. To further reduce the dimensions of such Si pyramidal nanopore arrays, a simple and reliable nanopore shrinking technique based on dry thermal oxidation has been proposed, as shown in our recent work.29 As both the shape and size of the pyramidal Si nanopores can be easily tuned using the controllable method mentioned in this paper, such nanopore arrays can be used as templates (stencils)

Figure 3. 22 × 20 square nanopore array and its details: (a) and (b) SEM micrographs of the nanopore array imaged from the top side and bottom side, respectively; (c) details of the nanopore in the center of the nanopore array; (d) plot of the variation of the average nanopore size with wet etching time.

shows an opened 22 × 20 square nanopore array imaged from the top and bottom sides, respectively. The space between every two adjacent nanopores in the array is 5.5 μm. Details of a representative nanopore (indicated in the square box of Figure 3b) in the array are shown in Figure 3c. The shape of the nanopore is a typical square, and its size (defined as the square root of the product of its width and length) is 60 nm, which is consistent with the average size of the whole nanopore array. Furthermore, the edges of the nanopore are clear and sharp, which is of importance in increasing the spatial and temporal resolution when used as biosensors. However, the relative size error of the nanopores within the 22 × 20 array is ∼13%, which is mainly due to the thickness variation of the common commercial silicon chip and the 18112



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surface nano/micro structures with less time and low cost.33,34 To verify the feasibility, preliminary nanostencil lithography experiments using the PSNAs as templates were conducted; the experimental setup is shown in Figure 6a. Activated nano-

for the nanostencil lithography, where the morphologies of the fabricated patterns are totally determined by the shape and size of the templates. After being deposited with a layer of rhotanium (10 nm), the fabricated nanopores were cut in the middle using a field emission gun, SEM/FIB (FEG-SEM/FIB, LYRA3, TESCAN, Brno, Czech Republic), to investigate the inner structure of the nanopore. Figure 5a shows a schematic illustration of how the

Figure 5. Setup of the nanopore cutting experiment and the results: (a) the schematic illustration of the experimental setup; (b) an SEM micrograph of the nanopore before FIB cutting; (c) and (d) SEM micrographs of the nanopore characteristics during the FIB cutting.

nanopore was cut by the FIB and in situ investigated using the SEM. More details of the experimental parameters of the FIB and SEM can be found in the Supporting Information. The initial morphology of the nanopore before FIB cutting is shown in Figure 5b, whose feature size is 41 nm. With the performance of the FIB cutting, the inner structure of the nanopore was revealed step and step, as shown in Figure 5b,c. Simultaneously, the feature size of the nanopore got smaller and smaller, which was mainly due to the sputtered atoms deposited on the nanopore edges. The nanopore shrinkage rate induced by the FIB cutting is shown in Figure S3 in the Supporting Information. Figure 5d demonstrates that the inner structure of the nanopore is exactly pyramidal with an included angle of 50.7°, which is a little smaller than the included angle between the crystalline Si (100) and (111) planes (54.7°), but still reasonable when the investigation angle of the SEM is taken into consideration. As mentioned in section I, conical and pyramidal Si nanopores have been found to exhibit unique ionic rectification properties due to their asymmetric geometry.6 Such nanopores can be used to develop ionic analogues of electronic devices,30 molecular sensors,31 and separation platforms.32 As mentioned in section I, one of the promising applications of the pyramidal silicon nanopore arrays (PSNAs) is to act as reusable templates for nanostencil lithography, which is a shadow-mask technique widely used in microelectronics. The technique allows fabrication of large-scale ordered arrays of

Figure 6. Nanostencil lithography with pyramidal silicon nanopore arrays (PSNAs) as reusable templates: (a) a schematic illustration of the nanostencil lithography mechanism; (b) an AFM image of a deposited Au−Pd nanocube array with an average planar size of 300 nm; (c) the height profile of the nanocubes along the dashed line indicated in (b).

particles directly deposit on a substrate though the PSNA template to fabricate desired surface patterns. The deposited material could be metallic, dielectric, and organic. As the PSNA template could contain large numbers of nanopores and nanoslits with a variety of shapes and sizes, corresponding surface patterns on wafer scale with the same shapes could be 18113



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IV. CONCLUSIONS A controllable wet etching method for the fabrication of silicon pyramidal nanopore arrays was demonstrated. Using this method, a visible nanopore opening process in real-time control was achieved. Square nanopore arrays with an average size of 60 nm and rectangular nanopores with different length− width ratios, as well as nanoslits with feature sizes as small as 13 nm, were obtained. FIB cutting experiments showed that the inner structure of the nanopore was exactly pyramidal, which was of importance in molecular sensing and separation applications. Furthermore, nanostencil lithography experiments indicated that such nanopore arrays could be used as reusable templates to directly deposit materials (metallic, dielectric, and organic) on any substrates, to fabricate massive surface patterns from nano scale to micro scale.

easily fabricated for high-throughput nanofabrication applications. Furthermore, the size of the surface patterns can be tuned by changing the distance (H) between the PSNA template and the substrate, although the shape of the pattern may be influenced to some extent. Thus, different patterns with different sizes and similar shapes can be created with the same PSNA template. In this paper, activated gold−palladium (Au−Pd) nanoparticles generated by a precision etching coating system (PECS 682, Gatan, Inc., CA) with a deposition rate of 8.5 nm/ min and a square PSNA with an average size of 300 nm were adopted to fabricate both nanocubes and microdots. Figure 6b shows an 8 × 8 Au−Pd nanocube array on a Si substrate, which was fabricated with the PSNA template placed in contact on the substrate (H = 0). The average planar size of the nanocube array is 300 nm with a relative size error of 13%, which is consistent with the average size of the PSNA. The threedimensional topography of the array indicates that the top geometry of the deposited nanocube is approximately conical rather than square. Figure 6c reveals the tapering height profiles of the nanocubes along the dashed line indicated in Figure 6b. The average height of the nanocube array is 9.7 nm with a standard deviation of 0.3 nm. By increasing the distance (H) between the PSNA template and a Cr/Si substrate to 500 μm, much larger surface patterns were created with the same PSNA template, as shown in Figure 7. It is worth noting that the shape of the deposited Au−Pt

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ASSOCIATED CONTENT

S Supporting Information *

Detailed investigation of Si etching rate and PDMS etching behavior in KOH solution, as well as further analysis of the FIB cutting induced nanopore shrinkage. This material is available free of charge via the Internet at http://pubs.acs.org.

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AUTHOR INFORMATION

Corresponding Author

*Telephone: 86-10-62789151. Cell Phone: 86-13501238562. Fax: 86-10-62771130. E-mail: [email protected]. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This research was supported by the National Natural Science Foundation of China (NSFC, Grant Nos. 91023040 and 61273061).

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REFERENCES

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Figure 7. Micropatterns fabricated using pyramidal silicon nanopore arrays as the nanostencil lithography templates: (a) 12 × 12 Au−Pd microdots deposited on a Cr/Si substrate; (b) the diameter distribution of the microdot array and its Gauss fitting curve.

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Controllable Fabrication of Pyramidal Silicon Nanopore Arrays and

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