Letter Cite This: ACS Appl. Mater. Interfaces 2018, 10, 21061−21065
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Depletion Mode MOSFET Using La-Doped BaSnO3 as a Channel Material Jin Yue,*,† Abhinav Prakash,† Matthew C. Robbins,‡ Steven J. Koester,‡ and Bharat Jalan*,† †
Department of Chemical Engineering and Materials Science and ‡Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, Minnesota 55455, United States
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ABSTRACT: The high room-temperature mobility that can be achieved in BaSnO3 has created significant excitement for its use as channel material in all-perovskite-based transistor devices such as ferroelectric field effect transistor (FET). Here, we report on the first demonstration of n-type depletion-mode FET using hybrid molecular beam epitaxy grown La-doped BaSnO3 as a channel material. The devices utilize a heterostructure metal-oxide semiconductor FET (MOSFET) design that includes an epitaxial SrTiO3 barrier layer capped with a thin layer of HfO2 used as a gate dielectric. A field-effect mobility of ∼70 cm2 V−1 s−1, a record high transconductance value of >2mS/mm at room temperature, and the on/off ratio exceeding 107 at 77 K were obtained. Using temperature- and frequency-dependent transport measurements, we quantify the impact of the conduction band offset at the BaSnO3/SrTiO3 interface as well as bulk and interface traps on device characteristics. KEYWORDS: stannates perovskite, MBE, defects, trap density, FET, high mobility
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have revealed that the highest conductivity La-doped BSO films (σ > 1 × 104 S/cm) also possess large transmittance >80% in the visible-to-near-infrared range, in addition to large conductance at THz frequencies.17 Owing to this behavior, the first realization of a visible-transparent terahertz polarizer using BSO has recently been demonstrated showing the significant potential of doped BSO for THz devices.17 For electronic devices, much work has focused on FETs using BSO as an active channel material.6,20−24 For FET operation, the band offset at the gate/channel interface, and defects in the gate dielectric or channel or at the gate/channel interface are important factors. Specifically, defects at the interface between BSO and the gate dielectric are a significant concern if there is a large lattice mismatch at the interface, or when amorphous dielectrics are used. These defects can act as trap centers leading to undesirable performance including low field-effect mobility (μFE), reduced transconductance and degraded subthreshold slope. For example, much lower μFE
ide bandgap materials with high conductivity are one of the most important materials breakthroughs in semiconductor technology over the past 20 years. The recent discovery of perovskite BaSnO3 (BSO) with wide bandgap, ∼3 eV and conductivity exceeding 104 S/cm, has created further significant excitement in this direction,1 particularly for applications as transparent conducting oxides, and in highpower electronics.2−7 Bulk BaSnO3 has a cubic perovskite structure with a lattice constant of 4.116 Å. Doped BaSnO3 single crystal has a room temperature (RT) electron mobility as high as 320 cm2 V−1 s−1 at 8 × 1019 cm−3.4 The high RT electron mobility is attributed to the small electron−phonon interaction and small electron effective mass as compared to more conventional perovskites such as SrTiO3 (STO).1,8 Thin films of BSO, on the other hand, show much smaller mobility values (≤183 cm2 V−1 s−1),4,9−13 which can be attributed to scattering from charged defects such as threading dislocations1,9,10,14 and also to electron−phonon scattering.1,8 Fundamental understanding of the dielectric, thermal and optical properties of BSO films has also improved1,12,15−19 including the study of the role of point defects on thermal conductivity and dielectric constant.12,15 Recent optical studies © 2018 American Chemical Society
Received: April 2, 2018 Accepted: June 13, 2018 Published: June 13, 2018 21061
DOI: 10.1021/acsami.8b05229 ACS Appl. Mater. Interfaces 2018, 10, 21061−21065
Letter
ACS Applied Materials & Interfaces
Figure 1. (a) Device schematic, (b) optical micrograph of the fabricated device, (c, d) IDS vs VDS characteristics of the device as a function of VGS measured at 300 and 77 K respectively, (e, f) transfer curve (IDS vs VGS) (left axis) and field effect mobility (μFE) (right axis) at 300 and 77 K respectively, (g, h) IDS1/2 vs VGS (left axis) and gm vs VGS (right axis) at 300 and 77 K, respectively.
(15−50 cm2 V−1 s−1) and high trap density (1013 cm−2 eV−1) were obtained in BSO FET with amorphous gate oxides including Al2O3,20 HfO2,22 and parylene,25 whereas superior μFE (∼90 cm2 V−1 s−1) was obtained in BSO-channel FETs, when nearly lattice-matched epitaxial LaInO3 was used as the gate dielectric.21 To put these results in context, the doped SrTiO3 FET with HfO2 gate dielectric shows FE electron mobility up to only 4.2 cm2 V−1 s−1 at RT.26 However, despite these trends, the detailed role of misfit dislocations and interface states in BSO heterostructure MOSFETs remains unclear. In an attempt to understand these issues in more detail, we have fabricated MOSFETs using La-doped BSO as the channel material and epitaxial SrTiO3 capped with thin HfO2 as the gate dielectric stack. The large lattice mismatch of ∼5% in STO (tensile strain) on relaxed La-doped BSO channel results in lattice relaxation accompanied by misfit dislocation formation in the STO film.27 A thin HfO2 capping layer on STO was used to reduce gate leakage current. Temperatureand frequency-dependent transport measurements have been conducted to understand the effect of interface and bulk traps, as well as the band offset on the carrier dynamics. An epitaxial La-doped BSO film (16 nm) was grown as the channel material on a 64 nm-thick undoped BSO (buffer) grown on SrTiO3 (001) substrate (Crystec GmbH) using hybrid molecular beam epitaxy (MBE) approach described elsewhere.1,9,27 An epitaxial STO film (71 nm) was grown on top of the channel as a gate dielectric followed by annealing at 900 °C for 2 min in excess oxygen using rapid thermal annealing (RTA). The cation stoichiometry for these films was ensured using high-resolution X-ray diffraction and the Rutherford Backscattering spectrometry (RBS). For the device fabrication, mesas were patterned to isolate the BSO channel using conventional photolithography and ion milling. Subsequent to this step, oxygen annealing was repeated to decrease possible contributions from oxygen vacancies that may have
been introduced during the ion milling process. It is noted that the as-grown undoped BSO films were insulating, suggesting no measurable oxygen vacancies.1 Next, source and drain contacts were patterned and recess-etched down to the BSO layer, followed by sputter-deposition and lift off a 20 nm Al/20 nm Ti/200 nm Au (top) metal stack. Finally, HfO2 (17 nm) was deposited using atomic layer deposition (ALD) to create the gate insulator on top of the STO barrier layer. The reactants for the HfO2 ALD deposition were tetrakis(dimethylamido)hafnium(IV) (TDMAH) and water vapor. Finally, the gate electrode was patterned and lifted-off using 20 nm Al/20 nm Ti/200 nm Au (top). The channel length and width of the device were 100 and 200 μm respectively, as shown in the optical micrograph in Figure 1b. It is noted that HfO2 was necessary to reduce gate leakage current given the small band offset of ∼0.4 eV between STO and BSO.6,16 Frequency- and temperature-dependent transport measurements were carried out using a semiconductor device parameter analyzer (Agilent B1500A) and a cryogenic probe station (Lakeshore CPX-VF). A depletion-mode MOSFET structure was fabricated in this study as it is a normally “on” switch when the gate-to-source voltage is zero (VGS = 0 V). Depletion-mode devices are useful for applications such as constant current sources, power converter start-up circuits, bilateral switches and other power applications where maximizing on-state current drive is needed and negative gate voltages can be tolerated. Figures 1c, f show output characteristics of the device, drain current (ID) vs drain-to-source bias (VDS), as a function of gate voltage (VGS) at 300 and 77 K, respectively. For both temperatures, the device shows a typical n-type depletion mode FET behavior, i.e. ID is reduced with more negative VGS, and a linear behavior followed by a saturation (pinch-off) behavior of ID was observed with increasing VDS. Figures 1d, g show transfer characteristics (IDS vs VGS) at 300 and 77 K, respectively, at a fixed VDS = 0.5 V (which corresponds to the 21062
DOI: 10.1021/acsami.8b05229 ACS Appl. Mater. Interfaces 2018, 10, 21061−21065
Letter
ACS Applied Materials & Interfaces
Figure 2. Frequency-dependent C−VGS characteristics of the device measured at (a) 300 K and (b) 77 K. Insets show semilog plots for clarity. Dotted lines correspond to the calculated capacitance per unit area using single HfO2 layer (red) and HfO2/SrTiO3 stack (green) as gate dielectrics.
Figure 3. (a, b) C−1/2(dC/dV)1/2 vs C at different frequencies at 300 and 77 K respectively. Inset to panel a shows extracted value of Cox as a function of frequency.
linear mode of operation). VGS was varied from 0 to −8 V at 77 K, whereas the range was limited to VGS = 0 to −6 V at 300 K due to increased gate leakage current (see Figure S1). The measurements at RT revealed a hysteretic behavior with a poor on/off ratio (Ion/Ioff) of ∼2, whereas at 77 K, a significantly larger Ion/Ioff exceeding 1 × 107 was observed with much smaller hysteresis. These results suggest the presence of traps in the devices at RT that may freeze out at lower temperature. We will discuss this result and the possible origin of traps later using frequency-dependent C−V measurements. From the transfer characteristics, μFE can be calculated using the following equation: ij yz ∂IDS L zz μFE = jjj j COxWVDS zz ∂VGS k {
where L, W, Cox, and
∂IDS ∂VGS
VDS
at 300 and 77 K (Figures 1d, g respectively). A maximum value of ∼70 cm2 V−1 s−1 was obtained. It is noted that roughly the same peak value of μFE was measured at 300 and 77 K, suggesting that the dominant scattering mechanism is not phonon scattering and could be related to defect scattering, which is consistent with our previous study of scattering mechanisms in doped BSO.1 An obvious drop in μFE was observed at −8 V < VGS < −4 V (i.e., with decreasing carrier density) for 77 K suggesting scattering is likely due to charged defects, in agreement with our prior results.1 It is noted that Cox is a critical parameter in accurately determining μFE and that the conventional method of measuring Cox in the accumulation regime may not yield a correct value when a large number of traps are present. We will come back to this point later. Figures 1e, h show gm measured at 300 and 77 K, respectively. The maximum value of gm (normalized to the channel width of 200 μm) was found to exceed 2 mS/mm, which is to-date the highest reported value for BSO-based FETs.20,22−25 Furthermore, using linear extrapolation of IDS1/2 − VGS curves (as illustrated in Figures 1e, h), we calculated the
(1)
are the channel length, channel VDS
width, gate oxide capacitance per unit area, and transconductance (gm) respectively. Using eq 1, we calculated μFE 21063
DOI: 10.1021/acsami.8b05229 ACS Appl. Mater. Interfaces 2018, 10, 21061−21065
Letter
ACS Applied Materials & Interfaces threshold voltage (VTH) at 300 and 77 K to be −8.7 V and −6.7 V, respectively. We now turn to the discussion of Cox and the role of misfit dislocations as traps. To this end, we performed frequencydependent measurements of capacitance (C) vs VGS at 300 and 77 K as shown in Figures 2a, b. Insets show the semilog plot for clarity. As an upper limit to Cox, the capacitances corresponding to only HfO2 (17 nm), and HfO2 (17 nm)/ SrTiO3 (71 nm) stack were calculated (assuming dielectric constant of 20 for HfO2 and 300 for SrTiO3) and are shown as dotted lines in the insets. At both temperatures, strong frequency dispersion was observed in the accumulation regime (VGS > 0 V) with capacitance exceeding even the highest value expected when on the HfO2 gate dielectric is considered. These results suggest the presence of a significant density of traps in the gate stack, which makes determination of Cox nontrivial. To put the later in the larger context, we recall conventional Si/SiO2-based MOSFETs, where Cox can be estimated to be the capacitance in the accumulation regime where measured capacitance saturates. However, in our case, the capacitance showed no sign of saturation in the accumulation regime making this conventional method of estimating Cox non applicable. It is noted that the applied VGS was limited to
