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Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers Dong Li, Mingyuan Chen, Qijun Zong, and Zengxing Zhang Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.7b03140 • Publication Date (Web): 28 Sep 2017 Downloaded from http://pubs.acs.org on September 30, 2017

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Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers Dong Li, Mingyuan Chen, Qijun Zong and Zengxing Zhang* Shanghai Key Laboratory of Special Artificial Microstructure Materials and Technology, School of Physics Science and Engineering, Tongji University, Shanghai 200092, China.

ABSTRACT: The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/hBN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. Based on these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

KEYWORDS: black phosphorus; graphene; memory; Schottky junction; two-dimensional materials

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As the oldest practical semiconductor device, the Schottky junction is one of the most elementary building blocks in electronics and optoelectronics for diodes, rectifiers, transistors, photodetectors, and photovoltaics. The Schottky junction is a type of metal–semiconductor contact in which the semiconductor is often formed by atomic doping that would destroy the crystal structure and degrade the electrical properties upon miniaturization. This is not beneficial for the flexible design of circuits and hinders their further application. Recent studies have suggested that two-dimensional (2D) materials such as graphene and transition-metal dichalcogenides (TMDs) show promise for next-generation integrated circuits1–7. This development has fueled the proliferation of studies of 2D crystals for use as Schottky junctions, in which the semimetal graphene is often used to contact the 2D semiconducting layers via van der Waals forces8–10. Schottky junctions with this type of heterostructure exhibit excellent properties and have been used in photodetectors11–13, memories11, logic transistors14, field-effect Schottky barrier transistors (FESBTs)15–21, and other applications22,23. Of the numerous layered semiconductors, particular attention has been attracted by ambipolar 2D crystals such as black phosphorus (BP) and WSe2, in which the majority charge carriers can be dynamically modulated by the electrical field24–29. These materials would complement conventional semiconductors, enabling the design of p–n junctions by coupling multiple splitting gates30–34 and the development of novel devices for logic electronics and logic optoelectronics35. Via trapping/erasing charge carriers in the floating gate, floating-gate field-effect transistors (FGFETs) are often used for nonvolatile memories36–39. Recently, programmable nonvolatile storable p–n junctions were successfully fabricated using the semi–floating gate field-effect transistor (SFG-FET) device structure and ambipolar 2D crystals, which should lead to possible applications in next-generation electronics and optoelectronics40. Here we report the fabrication


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of a graphene-BP programmable nonvolatile ambipolar Schottky junction memory based on a floating-gate field-effect Schottky barrier transistor (FG-FESBT) configuration using all-2D layers of the graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) heterostructure. The resulting Schottky junction shows unique diode properties, and the rectification direction can be tuned by the voltage pulse. With the introduction of a graphene charge-trapping layer, the device exhibits nonvolatile storability characteristics and can be applied to dual-mode Schottky junction memories, memory inverter circuits, and logic rectifiers. Figure 1a shows a schematic plan of the FG-FESBT configuration, in which the grapheneBP/h-BN/graphene heterostructure is on an Si wafer covered with a 300-nm-thick SiO2 film. In this device, the graphene-BP heterostructure serves as the transport channel, the bottom graphene under the h-BN is the floating gate, the Si is the control gate, and the h-BN and SiO2 are the dielectrics. Figure 1b shows a scanning electron microscopy (SEM) image of a typical fabricated device. To systematically investigate the FG-FESBT, the architecture was designed to include three different devices: the graphene/h-BN/graphene FG-FET (corresponding to electrodes E1 and E2), the BP/h-BN/graphene FG-FET (E3–E4), and the graphene-BP/h-BN/graphene FGFESBT (E2–E3). The first two FG-FET devices are often used for nonvolatile memories (Figure S1)36–39 and were included for comparison with our FG-FESBT. Atomic force microscopy (AFM) in a tapping mode was applied to characterize the structure, indicating that the bottom graphene, h-BN, top graphene, and BP layers have thicknesses of 1.8, 14.5, 5.5, and 9 nm, respectively (Figure S2). Previous studies have indicated that the monolayer graphene can make good contact with the BP flake due to the flexible tunability of its Fermi level41. Here we used multilayer graphene to connect the BP for the Schottky junction because its Fermi level is less sensitive to the modulation of the electrical field. The Raman spectra of the BP, graphene, h-BN,


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and the heterojunction region are plotted in Figure 1c. The typical Raman signatures of BP (Ag1 peak at 365 cm−1, B2g peak at 440 cm−1, and Ag2 peak at 470 cm−1)26, h-BN (E2g peak at 1365 cm−1)42, and graphene (G peak at 1581 cm−1 and 2D peak at 2723 cm−1)43 can be clearly observed in the Raman spectra. The device architecture indicates that the heterostructures on the SiO2 can serve as field-effect transistors (FETs) if the bottom graphene and h-BN are used as the gate electrode and dielectric, respectively. Figure 2a shows the transfer characteristic curves of the graphene/h-BN/graphene FET (E1–E2), in which the conductive channel is the top graphene multilayer connected to the BP and the gate voltage (VF-Gr) is applied to the bottom graphene. When the VF-Gr was tuned from −5 to +5 V, the graphene FET exhibits a fairly low on/off ratio of around 1.5 with a sheet resistance of ~400 Ω (at VF-Gr = 0 V). Both the low on/off ratio and high sheet resistance demonstrate that the graphene multilayer is a semimetal with a barely tunable Fermi level. However, BP is a semiconductor with a considerable bandgap25. As shown in Figure 2c, the on/off ratio of the BP FET (E3–E4) reaches up to 2×103 at the drain voltage of 0.5 V. When the VF-Gr is swept from −5 to +5 V, the current first decreases and then increases gradually, with the Dirac point at VF-Gr around +2.5 V, indicating that the BP is intrinsically p-doped and can be modulated as p-type or n-type by the gate voltage. In other words, the BP is ambipolar. Further investigation reveals that the BP possesses a hole mobility of 41.7 cm2/V·s at the drain voltage of 0.5 V (the detailed calculation method is described in Figure S3). The output characteristics (ID vs VDS) of the graphene- and BP-based FETs are presented in Figures 2b and 2d, respectively. The results reveal that the currents in the two FETs were almost linearly and symmetrically dependent on the bias voltages at different gate voltages, indicating that the metal electrodes form ohmic contacts to both the BP and graphene. Therefore, the following discussed rectifying behaviors of the


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graphene-BP FESBT (E2–E3) are dominated by the graphene-BP interface rather than by the other interfaces. Figure 2e shows the transfer characteristics (ID–VF-Gr) of the graphene-BP FESBT at drain voltages (VDS) of ±0.5 V, in which the drain electrode is connected to the BP, the source is connected to the top graphene, and the gate voltage (VF-Gr) is applied to the bottom graphene. The results reveal that the device exhibits a high on/off ratio exceeding 1×104 with a hole mobility of 40.5 cm2/V·s at the VDS of +0.5 V. The on/off ratio of the graphene-BP is even higher than that of the pure BP-based FET shown in Figure 2c at the same VDS of +0.5 V without obviously reducing the mobility, illustrating that the resulting FESBTs may be more promising for application in logic circuits. This result also suggests that stacking 2D crystals could be a feasible way to obtain excellent new artificial materials by combining the advantageous properties of each component. It is worth noting that the transfer curves with VDS values of ±0.5 V show distinct paths, which is not the case of conventional FETs. As shown in Figure 2e, when the gate voltage is less than ~2 V, the current for the VDS of +0.5 V is greater than that for the VDS of −0.5 V. However, when the gate voltage is over ~2 V, the current for the VDS of +0.5 V is lower, demonstrating that the current is dependent on the direction of the VDS and that the device exhibits ambipolar behavior. To determine the origin of the ambipolar properties of the graphene-BP FESBT, the transfer curves of the BP FET in Figure 2c should be re-examined. When the gate voltage is less than ~2 V, the BP is dominated by holes. In this case, the graphene-BP acts as a graphene-p-BP Schottky junction (see the energy band diagram in Figure S4b), and the positive VDS on the BP is the forward bias. This is clearly demonstrated by the output characteristic curves in Figure 2f at the gate voltages of −3, −4, and −5 V. However, when the gate voltage exceeds ~2 V, the BP


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becomes dominated by electrons, and the graphene-BP acts as a graphene-n-BP Schottky junction (see the energy band diagram in Figure S4c). This is also confirmed by the output curves in Figure 2f, in which the negative VDS is the forward bias with the gate voltages of +3, +4, and +5 V. Therefore, the working principle of the VDS direction-dependent rectifying behavior of the graphene-BP FESBT has been clearly demonstrated; this behavior is intrinsically due to the ambipolar modulation on the graphene-BP heterojunction by the gate voltage. At gate voltages under ~2 V, the device acts as a graphene-p-BP diode and VDS = +0.5 V is the forward bias, leading to a greater current than at −0.5 V. At gate voltages over ~2 V, the device acts as a graphene-n-BP diode, and the current at +0.5 V is lower than that at −0.5 V. For Schottky diodes, the electrical transport can be fitted by the Shockley equation extended to include the series resistance RS, =

exp (

) − ,32, 44

where I0 is the reverse saturation current, VT=kBT/e is the thermal voltage at the temperature T, kB is the Boltzmann constant, e is the electron charge, W is the Lambert W function, and n is the ideality factor. The ideality factor n typically varies from 1 to 2 (although it can in some cases be higher), depending on the fabrication process, interface, and semiconductor material, and is equal to 1 for the case of an “ideal” diode. The ideality factor is often used to characterize imperfect junctions as observed in real transistors and accounts for carrier recombination behavior as the charge carriers cross the depletion region. By fitting the ID–VDS curves (see Figure S5), we obtain n = 1.2 and RS = 2.5 MΩ with a VF-Gr of +5 V and n = 1.2 and RS = 200 kΩ with a VF-Gr of −5 V. This means that the ideality factor is close to 1. We can thus conclude that the carriers across the


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graphene-BP Schottky junction are mainly dominated by diffusion rather than recombination processes44. We now study the electrical properties of the graphene-BP/h-BN/graphene FG-FESBT, in which the bottom graphene is the floating gate and the Si is the control gate. Figure 3a shows the ID–VDS curves across the graphene-BP with different positive voltage pulses applied to the Si control gate, which demonstrate a similar rectifying behavior to that observed in Figure 2e with negative voltages on the bottom graphene. These results indicate that the positive voltage pulse causes the graphene-BP to act as a graphene-p-BP Schottky junction. When negative voltage pulses are applied to the control gate, the graphene-BP exhibits a reverse rectification behavior to the positive voltages, which is similar to that observed in Figure 2e using the positive voltages, indicating that the heterojunction behaves as a graphene-n-BP diode. Moreover, such characteristics are storable and could be retained well over 10 years (Figure S6). However, when the bottom graphene is grounded, the graphene-BP is recovered and reverts to the same state as before application of the pulses (Figures S7 and S8). Therefore, we can conclude that the retained rectifying behavior is strongly dependent on the bottom graphene floating gate. Based on the device structure of the graphene-BP/h-BN/graphene FG-FESBT (Figure 1a) and the above discussion, the ambipolar Schottky junction storability behavior can be easily understood. As shown in Figure 3c, when a positive voltage is applied to the Si control gate, electrons accumulate in the graphene-BP channel because of the electrical field effect. At the same time, a positive electrical potential is formed between the bottom graphene and the channel, which makes the accumulated electrons tunnel from the channel to the bottom graphene. After the control gate voltage is removed, the accumulated electrons in the channel disappear. However, the tunneled electrons are still trapped in the graphene floating gate due to the


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potential barrier from the h-BN. The tunneled electrons should produce mirror-image holes in the part of the channel over the bottom graphene floating gate, just as when a negative voltage is applied to the bottom graphene. In this case, the graphene-BP is retained as the graphene-p-BP Schottky junction (see the bottom part of Figure 3c), leading to the positive VDS forward rectifying behavior in Figure 3a. By a similar mechanism, after the negative voltage is removed from the Si, mirror-image electrons will be induced in the channel and cause the graphene-BP to act as a graphene-n-BP diode (Figure 3d), resulting in the negative VDS forward rectifying behavior shown in Figure 3b. It can be seen that the charges trapped in the graphene floating gate play an important role in the formation of the storable ambipolar Schottky junctions. This is the reason behind the recovery of the electrical transport when the bottom graphene is grounded, as under such circumstances the trapped charges are able to flow away. Figure 4a shows the transfer characteristics of the graphene-BP/h-BN/graphene FG-FESBT with forward and reverse control gate voltage (between −20 and +20 V) scanning on the Si, which exhibits significant hysteresis (25 V) due to the aforementioned charge injection and trapping in the graphene floating gate, indicating that this device can be developed for nonvolatile memories. In contrast to conventional FG-FET-based memories, the FG-FESBT device exhibits unusual features. Over the same scanning range, the positive VDS (+0.2 V) leads to a much higher on/off ratio than the negative VDS (−0.2 V). The former reaches up to 104 and the latter is only approximately 50. For conventional FG-FET memories, the on/off ratio should be similar regardless of the VDS direction. Such VDS direction-dependent memory behavior is ascribed to the use of the graphene-BP Schottky junction transport channel instead of the uniform semiconductor used in conventional FG-FET devices. With a positive voltage pulse, the graphene-BP acts as a graphene-p-BP diode.


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In this case, VDS = +0.2 V is the forward bias and VDS = −0.2 V is the reverse bias, leading to a greater current for VDS = +0.2 V than for VDS = −0.2 V. When a negative voltage pulse is applied, the graphene-BP is transformed to a graphene-n-BP diode. Then, VDS = +0.2 V becomes the reverse bias and VDS = −0.2 V the forward bias, resulting in a smaller current for VDS = +0.2 V than for VDS = −0.2 V. Through this mechanism, VDS = +0.2 V results in a much higher on/off ratio than VDS = −0.2 V. Therefore, the reading of such FG-FESBT memory is dependent not only on the voltage pulse applied to the control gate but also on the bias voltage direction of the drain electrode. This means that there are two modes for reading the memory, namely, the reverse (negative) and forward (positive) bias voltage modes (see Figures 4b to 4d), which should be beneficial for the flexible design of the memory in electronic circuits. For nonvolatile memories, the retention performance is crucial for applications. As shown in Figure 4b, after application of a negative voltage pulse (−20 V, pulse width 300 ms) to the Si control gate, the device acts as a graphene-n-BP junction and is in the program (“off”) state, whereas a positive voltage pulse (+20 V, pulse width 300 ms) causes it to act as a graphene-p-BP diode in the erase (“on”) state. The device exhibits on/off ratios of ~50 for VDS = −0.2 V and ~104 for VDS = +0.2 V. After 1200 s, there were no significant variations of the currents. Further investigation indicates that 50% of the trapped charges would disappear after 10 years (Figure S6), suggesting that the FG-FESBT-based memory should demonstrate fairly good retention behavior. Figures 4c and 4d show the dynamic performances of the device via the periodic memory cycles of program–read–erase–read with VDS = −0.2 V and VDS = +0.2 V, respectively. The results demonstrate that the device can be switched well between the erase and program states by applying the negative and positive voltage pulses to the control gate at both the negative and positive VDS.


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The ambipolar properties of the developed FG-FESBT can also be exploited for memory inverter circuits. The inset in Figure 5b shows the circuit diagram, in which a 1-MΩ resistor is chosen as the external load. Figure 5a shows the voltage transfer characteristic curves (VOut vs VIn) with an applied VDD of +0.2 V. Upon scanning the VIn forwards and backwards, a large hysteresis is observed, which is consistent with that shown in Figure 4a. Figure 5b shows the dynamic performance of the circuit. It can be seen that when a −20 V input voltage pulse (pulse width, 300 ms) is applied, an inverted voltage of approximately +0.2 V is outputted. In contrast, the application of an input voltage pulse of +20 V (pulse width, 300 ms) causes the circuit to rapidly switch to the off state. This switching behavior could be repeated well for tens of cycles, indicating that the device shows good performance as a nonvolatile memory inverter circuit. Furthermore, the graphene-BP/h-BN/graphene FG-FESBT can also be exploited for logic rectifiers35,40,45. The inset in Figure 5c shows the diagram of the rectifier circuit, in which a 1MΩ resistor is connected to the FG-FESBT as the external load. As shown in Figure 5c, when a voltage pulse of −20 V is applied to the Si control gate, the FG-FESBT performs as a graphenen-BP Schottky junction diode. In this case, the negative VDS is the forward bias for the diode, causing the positive input voltage to be almost entirely filtered, whereas the negative input voltage passes through. When a voltage pulse of +20 V is applied to the control gate, the device turns into a graphene-p-BP junction diode. It can be seen from Figure 2a that the reverse current of the graphene-p-BP diode is fairly large. This means that the effective resistance of the graphene-p-BP is quite small, which causes the partial voltage on the diode to be fairly small. Therefore, both negative and positive voltages are allowed to pass through. As such, the circuit acts to logically switch on/off the rectifying behavior, indicating that it can be used for logic rectifiers.


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In summary, by using the various unique properties of 2D crystals, we have designed and fabricated a FG-FESBT device by stacking 2D layers of BP, graphene, and h-BN. By manipulating the voltage pulse to the control gate, charge carriers could be stored and erased in the graphene floating gate. In this way, a programmable nonvolatile ambipolar graphene-BP Schottky junction memory was successfully achieved, which could be tuned to act as graphenep-BP or graphene-n-BP diodes by the control gate voltage pulse and exhibited retention of more than 10 years. Based on its ambipolar characteristics and programmable storability properties, the graphene-BP/h-BN/graphene FG-FESBT was exploited for dual-mode nonvolatile Schottky junction memories, nonvolatile memory inverter circuits, and logic rectifiers. The developed programmable nonvolatile Schottky junction memory may enable further innovation in the electronic and optoelectronic fields, permitting the design of the next generation of flexible transparent semiconductor circuits and opening up some new applications. It may also serve to demonstrate that 2D-crystal–based van der Waals heterostructures are a promising configuration for the design of new devices with amazing functions. Fabrication of FG-FESBTs based on a graphene-BP/h-BN/graphene heterostructure. The graphene-BP/h-BN/graphene heterostructures were obtained with the use of a previously described dry-transfer technique46. The BP, graphene, and h-BN flakes were all produced using a mechanical exfoliation approach from bulk crystals. In a typical process, the graphene flake was first exfoliated onto a silicon wafer covered with a 300-nm-thick thermal oxide (SiO2) film. The h-BN flake was then exfoliated onto a transparent polydimethylsiloxane (PDMS) film by Scotch tape and aligned on the graphene flake with the aid of an optical microscope. With a slight press, the h-BN separated from the PDMS film and transferred onto the graphene. The top graphene and BP layers were aligned and transferred onto the h-BN by a similar method, as indicated in


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Figure 1a, resulting in the formation of the graphene-BP/h-BN/graphene van der Waals heterostructures. Standard e-beam lithography (EBL) and thermal evaporation methods were finally used to define Au/Cr electrodes on the heterostructures. Characterization. The morphology of the graphene-BP/h-BN/graphene heterostructures was characterized by SEM and AFM in a tapping mode. Raman spectroscopy was performed under atmospheric conditions using a Horiba Jobin Yvon LabRAM HR system with a 514-nm laser. The electrical properties were measured in a probe station under a vacuum of 10−4 Pa and recorded with a Keithley 4200 SCS semiconductor analyzer system. ACCOCIATED CONTENT Supporting Information The Supporting Information is available free of charge on the ACS Publication website. Details of performance of pure graphene- and pure BP-based nonvolatile memories (S1), AFM characterization (S2), mobility calculation (S3), energy band diagram (S4), Schottky diode fitting (S5), charge retention (S6), ID-VDS curve without any gate voltage applied (S7) and electrical transport characterization of the Schottky junction device (S8).

AUTHOR INFORMATION Corresponding Author *E-mail: [email protected] Notes The authors declare no competing financial interest.


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ACKNOLODGEMENTS The work was supported by Natural Science Foundation of Shanghai (16ZR1439400, 17ZR1447700), and Fundamental Research Funds for the Central Universities. The authors thank Prof. Baowen Li and Prof. Xiangfan Xu for devices fabrication and AFM characterization.

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A. Nature Nanotech. 2013, 8, 826-830. 12. De Fazio, D.; Goykhman, I.; Yoon, D.; Bruna, M.; Eiden, A.; Milana, S.; Sassi, U.; Barbone, M.; Dumcenco, D.; Marinov, K.; Kis, A.; Ferrari, A. C. ACS Nano 2016, 10, 8252-8262. 13. Lee, K. H.; Kim, T.-H.; Shin, H.-J.; Kim, S.-W. Adv. Mater. 2016, 28, 1793-1798. 14. Yu, W. J.; Li, Z.; Zhou, H.; Chen, Y.; Wang, Y.; Huang, Y.; Duan, X. Nature Mater. 2013, 12, 246-252. 15. Shih, C.-J.; Wang, Q. H.; Son, Y.; Jin, Z.; Blankschtein, D.; Strano, M. S. ACS Nano 2014, 8, 5790-5798. 16. Rathi, S.; Lee, I.; Lim, D.; Wang, J.; Ochiai, Y.; Aoki, N.; Watanabe, K.; Taniguchi, T.; Lee, G.-H.; Yu, Y.-J.; Kim, P.; Kim, G.-H. Nano Lett. 2015, 15, 5017-5024. 17. Kwak, J. Y.; Hwang, J.; Calderon, B.; Alsalman, H.; Munoz, N.; Schutter, B.; Spencer, M. G. Nano Lett. 2014, 14, 4511-4516. 18. Jeong, H.; Oh, H. M.; Bang, S.; Jeong, H. J.; An, S.-J.; Han, G. H.; Kim, H.; Yun, S. J.; Kim, K. K.; Park, J. C.; Lee, Y. H.; Lerondel, G.; Jeong, M. S. Nano Lett. 2016, 16, 1858-1862. 19. Georgiou, T.; Jalil, R.; Belle, B. D.; Britnell, L.; Gorbachev, R. V.; Morozov, S. V.; Kim, Y.J.; Gholinia, A.; Haigh, S. J.; Makarovsky, O.; Eaves, L.; Ponomarenko, L. A.; Geim, A. K.; Novoselov, K. S.; Mishchenko, A. Nature Nanotech. 2013, 8, 100-103. 20. Shim, J.; Kim, H. S.; Shim, Y. S.; Kang, D.-H.; Park, H.-Y.; Lee, J.; Jeon, J.; Jung, S. J.; Song, Y. J.; Jung, W.-S.; Lee, J.; Park, S.; Kim, J.; Lee, S.; Kim, Y.-H.; Park, J.-H. Adv. Mater. 2016, 28, 5293-5299. 21. Tian, H.; Tan, Z.; Wu, C.; Wang, X. M.; Mohammad, M. A.; Xie, D.; Yang, Y.; Wang, J.; Li, L. J.; Xu, J.; Ren, T. L. Sci. Rep. 2014, 4, 5951. 22. Gao, A.; Liu, E.; Long, M.; Zhou, W.; Wang, Y.; Xia, T.; Hu, W.; Wang, B.; Miao, F. Appl.


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Figure 1. (a) Schematic plan of the device configuration, which is based on a graphene-BP/hBN/graphene heterostructure with an FG-FESBT architecture. (b) False-colored SEM image of a typical fabricated graphene-BP/h-BN/graphene device. (c) Raman spectra of the graphene, BP, hBN, and the heterojunction region.


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Figure 2. (a) Transfer and (b) output characteristic curves of the graphene-based FET with the bottom graphene (GrB) as the gate electrode and the h-BN as the gate dielectric. (c) Transfer and (d) output characteristic curves of the BP-based FET. (e) Transfer characteristic curves of the graphene-BP heterojunction device with VDS values of ±0.5 V. (f) ID–VDS curves of the grapheneBP device on a logarithmic scale with different gate voltages.


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Figure 3. (a) ID–VDS curves across the graphene-BP with positive voltage pulses applied to the Si control gate. (b) ID–VDS curves across the graphene-BP with negative voltage pulses applied to the Si control gate. (c) Operating mechanism of the FG-FESBT device with a positive control gate voltage and after removal of the voltage. (d) Operating mechanism of the FG-FESBT device with a negative control gate voltage and after removal of the voltage.


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Figure 4. (a) Transfer characteristic (ID–VCG) curves of the FG-FESBT with VDS values of ±0.2 V. (b) Retention performance of the FG-FESBT with a ±20 V voltage pulse applied to the control gate at VDS values of ±0.2 V. (c) Switching behavior between the erase (“on”) and program (“off”) states with a VDS of +0.2 V upon applying an alternating VCG-Pulse of ±20 V. (d) Switching behavior between the erase (“on”) and program (“off”) states with a VDS of −0.2 V upon applying an alternating VCG-Pulse of ±20 V.


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Figure 5. (a) Voltage transfer characteristic curves of the nonvolatile memory inverter circuit upon scanning various input voltages on the control gate. (b) Switching behavior of the memory inverter circuit upon applying alternating voltage pulses (±20 V, 300 ms) to the control gate. Inset: schematic of the memory inverter circuit with a 1-MΩ resistor as the load. VDD = 0.2 V. (c) Characterization of the FG-FESBT for logic rectifier circuits. Inset: diagrams of the logic rectifier at different states.


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