Letter pubs.acs.org/NanoLett
Vertical Nanowire Heterojunction Devices Based on a Clean Si/Ge Interface Lin Chen, Wayne Y. Fung, and Wei Lu* Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan 48109, United States S Supporting Information *
ABSTRACT: Different vertical nanowire heterojunction devices were fabricated and tested based on vertical Ge nanowires grown epitaxially at low temperatures on (111) Si substrates with a sharp and clean Si/Ge interface. The nearly ideal Si/Ge heterojuctions with controlled and abrupt doping profiles were verified through material analysis and electrical characterizations. In the nSi/pGe heterojunction diode, an ideality factor of 1.16, subpicoampere reverse saturation current, and rectifying ratio of 106 were obtained, while the n+Si/p+Ge structure leads to Esaki tunnel diodes with a high peak tunneling current of 4.57 kA/ cm2 and negative differential resistance at room temperature. The large valence band discontinuity between the Ge and Si in the nanowire heterojunctions was further verified in the p+Si/pGe structure, which shows a rectifying behavior instead of an Ohmic contact and raises an important issue in making Ohmic contacts to heterogeneously integrated materials. A raised Si/Ge structure was further developed using a self-aligned etch process, allowing greater freedom in device design for applications such as the tunneling field-effect transistor (TFET). All measurement data can be well-explained and fitted with theoretical models with known bulk properties, suggesting that the Si/Ge nanowire system offers a very clean heterojunction interface with low defect density, and holds great potential as a platform for future high-density and high-performance electronics. KEYWORDS: Heterostructure, nanowire, silicon/germanium, vapor−liquid−solid, vertical device, tunneling
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Si is challenging due to the 4% lattice mismatch, which puts a severe limit on the thickness of the dislocation-free Ge film that can be grown on Si substrate and limits the practical application of Ge. To this end, the nanowire approach offers an attractive solution since Ge nanowires grown on Si can effectively relax the strain along the radial direction, making it possible to produce defect-free Si/Ge heterostructures.6−8 Additionally, the nanowire geometry makes it natural to adopt a surrounding gate structure, which provides the most optimal gate control to compete short channel effects.9 Finally, the nanowires are grown vertically on a Si substrate, enabling vertical transistors and efficient 3-D device integration that allows even higher integration density and drive current/speed.10−12 To date, there have been a number of studies on the topic of Ge nanowire devices.13−16 Particularly, the Si/Ge heterostructure has attracted much attention thanks to its type II band alignment, which leads to the formation of high mobility hole
here is a fast growing demand for the development of new classes of electronic devices as the scaling of traditional Si transistor technology begins to face fundamental and technical bottlenecks. To sustain the desired performance scaling, hybrid integration of devices based on novel architectures (e.g., multigate structure), unconventional channel materials (Ge, III−V, or graphene), and unconventional transport mechanisms (e.g., tunnel transistor, impact ionization transistor) are being extensively studied for higher speed, higher packing density, and lower power.1 Ge has long been regarded as a promising material for transistor channel replacement due to its inherent low effective mass and high mobility (3900 Vs/cm2 for electrons and 1900 Vs/cm2 for holes, at room temperature).2 With a smaller band gap (0.66 eV at room temperature, compared to 1.12 eV of Si) and lower effective mass, Ge is also extensively studied for tunneling field-effect transistors (TFETs) as it promises 2 orders of magnitude higher Ion at the same electric field than Sibased TFETs.3−5 Ge has already been introduced to the semiconductor industry in the form of SixGe1−x as one of the technology boosters in 2004.1 Its full CMOS compatibility gives Ge another advantage over other potential contenders such as III−V materials. However, direct integration of Ge with © 2013 American Chemical Society
Received: August 19, 2013 Revised: October 8, 2013 Published: October 17, 2013 5521
dx.doi.org/10.1021/nl403112a | Nano Lett. 2013, 13, 5521−5527
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Figure 1. Epitaxial growth of Ge nanowires on Si. (a) SEM image of vertically grown Ge nanowires on a (111) Si substrate. (b) Enlarged SEM image from 45° tilted angle. (c) HRTEM image of the nanowire heterostructure showing the Si/Ge interface. Inset is a low-resolution TEM image of the same sample. (d) STEM EDX line scan data showing Si and Ge concentration vs position acquired from the Si/Ge heterojunction.
An important figure of merit for the heterojunction is the junction abruptness, which defines how sharp the transition is from one material to another. Junction abruptness is important for device applications such as TFET where the field profile dictates the device performance.3 To estimate the junction sharpness, we performed elemental mapping using scanning transmission-electron microscopy (STEM) (AEM, JEOL 2010F). Figure 1d shows the EDX line scans for Ge and Si across the Si/Ge heterojunction. A transition width from Si to Ge of about 10−15 nm was obtained, which is on the order of but somewhat smaller than the nanowire diameter. The finite transition width is likely due to the reservoir effect23 commonly observed in heterostructure nanowire growth since Si has to be depleted from the Au−Si−Ge catalyst alloy before switching to Ge nanowire growth. Although our growth process does not feature a Si nanowire growth step used in earlier studies,23 a liquid Au−Si eutectic is likely still formed during the nucleation step due to the similarity between the eutectic temperatures of Au−Si (370 °C) and Au−Ge (356 °C),24 considering that Au is a type A catalyst for the Au/Si system with 19% Si in the Au/Si alloy at the eutectic point.24 The reservoir effect would cause a trailing edge in the Si composition curve along the nanowire elongation direction, as evidenced in Figure 1d. To further reduce the transition region width and achieve atomic abruptness, either Vapor−Solid−Solid (VSS) growth23 or catalysts with low Si solubility can be used.25 Doping profile is another important parameter for heterojunction devices. For example, previous simulation studies have shown that a doping gradient of 4 nm/decade can degrade the Ion in TFET for almost an order of magnitude from the ideal junction case.5 At the low growth temperatures we used, the diffusion of impurities from Si to Ge is estimated to be negligible.26 Since the doping in Ge nanowire is a result of the surface effect27 instead of physically present dopants in the bulk, dopant diffusion from Ge to Si can also be neglected. As a
gas in the Ge/Si core/shell structure.17 A number of papers also reported the use of Ge or SixGe1−x in TFET to achieve higher Ion.18−20 Here, we demonstrate that the epitaxial growth of vertical Ge nanowires on (111) Si substrates leads to abrupt Ge/Si heterojunctions with a nearly ideal interface. Furthermore, by independently tuning the doping levels in the Ge and Si regions, different carrier injection mechanisms can be obtained, leading to several desirable properties in these vertical nanowire devices. The Ge nanowires were epitaxially grown by the vapor− liquid−solid (VLS) method on a (111) Si substrate.21,22 The growth was catalyzed by 20 nm Au nanoparticles (Ted Pella Inc.), which were dispensed on to the hydrophobic silicon surface treated with 1 M HF prior to growth. The nucleation was carried out at 360 °C at a total pressure of 45 Torr (0.9% GeH4 in H2) for 1 min, followed by nanowire elongation at 300 °C and 30 Torr for with the same gas composition. The growth conditions were optimized to ensure best nucleation and vertical yield.21 Figure 1a/b shows a scanning electron microscopy (SEM) image (Hitachi, SU8000) of the as-grown Ge nanowires from different viewing angles. These nanowires showed a high vertical yield of >70% with a diameter of about 23 nm, consistent with the size of the catalyst used. The interface quality of the Si/Ge heterojunction is critical for any device application. Figure 1c shows a representative high-resolution transmission electron microscopy (TEM) image (HRTEM, JEOL 3011) of the Si/Ge nanowire heterojunction. The epitaxial relationship between Si (brighter region) and Ge (darker region) is evident, and the Ge nanowire clearly inherits the (111) direction from the Si substrate during growth. No obvious dislocations were observed at the interface, despite the 4% difference in lattice constants between Si and Ge. These findings are consistent with earlier studies which show that the nanowire geometry can coherently relax the strain and allow efficient heterogeneous integration.6−8 5522
dx.doi.org/10.1021/nl403112a | Nano Lett. 2013, 13, 5521−5527
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Figure 2. Vertical Si/Ge nanowire heterojunction devices. (a) SEM image of a completed vertical nanowire device covered with Ni top contact. Inset shows the electrode design. (b−d) Representative room temperature I−V characteristics for three different Si/Ge junctions, namely, (b) nSi/pGe diode, (c) n+Si/p+Ge Esaki diode, and (d) p+Si/pGe rectifying diode. The insets show corresponding device schematics.
can be consistently obtained at each doping configuration. Below we present a detailed analysis for each type of the devices. The first configuration features an n-Si substrate with moderate doping concentration (resistivity ∼0.10−0.16 Ω·cm, which corresponds to a doping level of 4 × 1016 cm−3) and an epitaxially grown p-Ge nanowire. A selective area phosphor diffusion was performed prior to nanowire growth to enhance the local doping concentration at the electrode contact area to ensure Ohmic contact from the electrode to the Si substrate. The band diagram for the n-Si/p-Ge structure is shown in Figure 3a, from which we can see that the band discontinuities, ΔEC and ΔEV add to the built-in potential for the carriers. The moderate doping on the Si and Ge sides suggests regular p−n
result, the doping gradient of the Si/Ge heterojunction is projected to be in line with the Si/Ge abruptness, from which 0.5 V), the current starts to be dominated by series resistance as in conventional diodes, and the I−V curve starts to deviate from the ideal exponential behavior. Based on the measurement results, the saturation current Isat and the diode ideality factor n can be extracted using the well-known p−n diode current equation.2 I = Isat(eqV / nkT − 1)
(1)
Figure 3c plots the extracted ideality factors versus temperature. This device has an ideality factor of 1.16 at room temperature which is very close to the ideal diode condition (n = 1) and further verifies the high quality of the Si/ Ge heterojunction and the lack of interface defects at the interface. In classical semiconductor devices, the ideality factor reflects the quality of the device as a higher generation− recombination current component (e.g., mediated by trap states) will result in a deteriorated larger ideality factor. The fact that our device shows an ideality factor very close to 1 indicates that generation−recombination current is insignificant compared to thermionic emission current, which can be translated to a very clean Si/Ge interface with low midgap trap density. Additionally, the ideality factor n increases as the temperature decreases, since the thermionic emission current scales with n2i , while the generation−recombination current scales with ni. As the temperature becomes lower and ni becomes smaller, the generation−recombination current will play an increasingly larger contribution in the overall current, leading to an increased ideality factor at lower temperatures, as has been observed earlier on p−n diodes.29 We note the Ge/Si p−n devices offer a very low Isat (
