Gold Contamination in VLS-Grown Si Nanowires - American Chemical

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Gold Contamination in VLS-Grown Si Nanowires: Multiwavelength Anomalous Diffraction Investigations Ludovic Dupré,*,† Denis Buttard,†,‡ Cédric Leclere,§ Hubert Renevier,§ and Pascal Gentile† †

SiNaPS Lab. - SP2M, UMR-E CEA/UJF-Grenoble 1, CEA/INAC, 17 avenue des Martyrs 38054 Grenoble, France Université Joseph Fourier/IUT-1, 17 Quai C. Bernard, 38000 Grenoble, France § LMGP, Grenoble INP - Minatec, 3 Parvis Louis Néel, 38016 Grenoble, France ‡

ABSTRACT: Silicon nanowires were grown by gold-catalyzed chemical vapor deposition in the vapor liquid solid mode. In this paper, we use grazing incidence X-ray diffraction and multiwavelength anomalous diffraction to investigate the presence of gold and its effects on silicon nanowire strain after different chemical and physical treatments. We especially focus on the efficiency of the “thermal oxidation−oxide etching” cycle to remove the gold contamination. Analysis reveals a decrease of the contamination and a “core−shell like” spatial distribution of gold, but also shows that this technique is not efficient enough to remove all traces of gold from the nanowires. KEYWORDS: silicon nanowire, vapor−liquid−solid, catalyst removal, gold contamination, grazing-incidence X-ray diffraction, multiwavelength anomalous diffraction

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INTRODUCTION

In this work, we study the mechanical influence and location of gold in silicon nanowires grown by gold-catalyzed CVD in VLS mode after three different chemical and/or physical treatments to remove gold: (i) no treatment; (ii) wet etching of gold; and (iii) wet etching of gold, followed by a thermal oxidation and subsequent deoxidation to isotropically etch the surface of the wires. For each treatment, we report measurements of the internal strain of the silicon nanowires using grazing-incidence X-ray diffraction (GIXD) and investigate the presence and location of catalyst residues in the wires by multiwavelength anomalous diffraction (MAD). The advantage of such techniques using X-ray radiation is the more general and averaged probing of all the wires on the surface of the sample, contrary to TEM measurements, which can only focus on single nanowires. Scanning electron microscopy (SEM) is also used to visually characterize the surface of the wires.

Semiconductor nanowires are now widely studied and integrated in new devices,1−4 with two techniques being mainly used for their production: top-down by reactive-ion etching5,6 or metal-assisted wet etching7,8 of a silicon wafer, and bottomup by growing the nanowires from the decomposition of a gas precursor on a catalyst.9−11 Although the most commonly used bottom-up process is gold-catalyzed chemical vapor deposition (CVD) in vapor liquid solid (VLS) mode,9,12 there are still only a few studies on the catalyst and its effects, such as its influence on the internal strains of the nanowires.13 Furthermore, gold, being a strong contaminant that degrades the electronic properties of silicon by introducing recombinant levels in the middle of the gap,14 the knowledge of gold contamination in silicon nanowires is of great interest to understand their electrical behavior. Studies of this contamination have been made by atom probe tomography15 or high-angle annular darkfield scanning transmission electron microscopy (HAADF STEM),15,16 showing that gold is mainly present on the surface of as-grown nanowires, but also in the core of the structures at the elemental level. Attempts to remove the catalyst residues were also performed, but are not totally efficient, according to electrical measurements.17 © 2012 American Chemical Society

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EXPERIMENTAL SECTION

Silicon nanowires are grown in a commercial hot wall CVD reactor in VLS mode, using gold as a growth catalyst and silane (SiH4) as a Received: June 5, 2012 Revised: November 6, 2012 Published: November 8, 2012 4511

dx.doi.org/10.1021/cm301739n | Chem. Mater. 2012, 24, 4511−4516

Chemistry of Materials

Article

silicon gas precursor. Growth substrates are prepared by cleaning ptype, (111) oriented, silicon wafers with acetone and isopropyl alcohol in ultrasonic bath, followed by a dip in 1% HF to get a smooth Hterminated deoxided surface. A thin layer of gold (2 nm) is then deposited on the substrates via physical vapor deposition and the samples are introduced in the CVD reactor. Prior to growth, an annealing is performed in situ at T = 850 °C for 10 min under a hydrogen gas (H2) flow in order to dewet the gold layer and create a network of catalyst droplets adsorbed on the surface of the samples. The size distribution of the catalyst droplets ranges from 30 nm up to 300 nm, centered on 100 nm, and the spatial distribution is homogeneous throughout the entire area of the sample. Silicon nanowire growth is then performed at T = 650 °C under a total pressure of 20 mbar with 20 sccm of silane carried by a H2 flow, according to the VLS mechanism.9 The resulting silicon nanowires are all ∼3 μm long and have diameters corresponding to the size of the initial gold droplets. After growth, samples are divided into three groups: A, B, and C (see Table 1). Group A, which is used as a control sample, is kept as grown with the catalyst droplet left on top of the wires. Group B is dipped into an I−KI solution for 2 min, to remove the gold catalyst by chemical etching, followed by liquid HF etching (1% solution) in order to remove the chemical silicon dioxide (SiO2) that was formed during the I−KI step. Group C undergo the same steps as group B and is subsequently thermally oxidized at T = 1000 °C for 20 min under O2 at atmospheric pressure. The 40-nm-thick silicon thermal oxide created on the wires is then etched by liquid HF. Given the dilatation coefficient between SiO2 and Si (a = 2.27), this process results in the etching of a layer of 18 nm of silicon on the sides of the wires. This lateral etching is expected to remove the surfacic gold contamination of the wires.17

Table 2. Equivalence between the Cubic and Hexagonal Lattice Representation of a Silicon Crystal (Diamond Structure)

as-grown

B

I−KI gold chemical etching

C

I−KI gold chemical etching thermal oxidation HF deoxidation

hexagonal

a b c α β γ

5.432 Å 5.432 Å 5.432 Å 90° 90° 90°

3.841 Å 3.841 Å 9.408 Å 90° 90° 120°

Figure 1. GIXD experimental setup: the grazing-incidence X-ray beam is diffracted by the (hk0)hex planes of the nanowires.

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process

A

cubic

Because of the intense light and multiwavelength requirements, Xray measurements were performed at the European Synchrotron Radiation Facility (ESRF) at Grenoble, France, at the BM2-D2AM beamline. The experimental setup (Figure 1) was composed of a seven-circle goniometer operating at room temperature and under atmospheric pressure. Scanning electron microscopy (SEM) was performed using a Zeiss Ultra 55 equipped with a field-effect gun.

Table 1. Division of Samples into Three Groups before Chemical and/or Physical Treatment To Remove Gold Contamination group

lattice parameter

RESULTS AND DISCUSSION Figure 2 shows typical GIXD diffraction patterns along the [100] direction close to the (300) reflection at different incidence angles α of the X-ray beam. The diffractograms show two distinct peaks that behave differently versus α. At low incidence, only one peak is clearly contributing to the diffraction signal, and with increasing α, a second peak at H = 3 appears and becomes dominant. This difference allows one to distinguish the nanowires and substrate peaks. At smaller incidence (smaller than the critical angle αc(11.926 keV) = 0.17°), the X-ray beam undergoes a total reflection on the

GIXD experiments are then carried out on the three groups of nanowires and compared to previously reported results,13 allowing determination of the lattice parameter mismatch between the wires and the substrate. Computations were realized using the parameters of Pearson7 functions calculated to fit the diffraction patterns. MAD is also used to study the presence and location of gold in the silicon crystalline matrix of the wires (at both substitutional and interstitial positions, without distinction) after each treatment. For this purpose, GIXD patterns were acquired at 11 different energies between 11.726 keV and 12.126 keV around the gold LIII absorption threshold at E = 11.926 keV (λ = 0.10402 nm), followed by a numerical analysis carried out using NanoMAD software.18 The preferential growth direction of silicon nanowires being [111], they are normal to the (111) surface of the substrates and the entire crystallographic system presents a hexagonal symmetry. Therefore, in order to simplify the notations, we choose to work in the hexagonal representation of the diamond lattice of silicon, instead of the cubic one (see Table 2). As a consequence, the [111]cubic direction becomes [001]hexagonal and all crystallographic directions are given in this system in the following discussion. Thus, in the GIXD geometry, all the diffracted planes are (hk0) type, perpendicular to the substrate and parallel to the growth axis of the wires.

Figure 2. Grazing-incidence X-ray diffraction (GIXD) patterns at different X-ray incidence angles α along the [100] direction for a sample of group B. The intensity of the substrate peak at H = 3 is increasing for greater values of α. 4512



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Figure 3. (a) GIXD pattern along the [100] direction for a sample of group B, the fitting functions (dashed line) and fitting result (solid line) are also shown. (b) Calculated dilation of the silicon lattice parameter in the nanowires of group B along the [100] direction for different incident X-ray angles.

Figure 4. (a) GIXD pattern along the [100] direction for a sample of group C, the fitting functions (dashed line) and fitting result (solid line) are also shown. (b) Calculated dilation of the silicon lattice parameter in the nanowires of group C along the [11̅0] direction for different incident X-ray angles.

compute the relative shift in their lattice parameter. The evolution of this strain is then plotted in Figure 3b, versus the incidence angle of the X-rays, allowing a probing of the strain at different locations along the wires: as the incident angle decreases, the probed part goes from the bottom to the top of the wires. This phenomenon was studied and explained for nanodots.20−22 When the incident angle decreases, the maximum of the optical function in GIXD geometry shifts to higher z values above the sample. For groups A and B, results are in agreement with previously reported ones.13 Wires are relaxed at their top, with a slight dilatation of the silicon crystalline matrix, and more strained to the bulk silicon lattice parameter at their bottom. We also confirm that, for group B, the removal of gold with I−KI etching induces a decrease of the dilatation of the lattice parameter. For group C, however, the shape of the diffraction pattern is distorted (Figure 4a), revealing two different peaks for the nanowires. This observation is confirmed by the good fit of the experimental data with three distinct functions: one very narrow, corresponding to the substrate at H = 3, and two other ones being wider, corresponding to the nanowires at H < 3. These two different diffraction peaks for the nanowires can be interpretated as the signature of two differently strained regions within the nanowires, resulting from the thermal oxidation−HF etching cycle. The first peak, at lower H, is labeled peak “S” and is attributed to the volume near the surface of the nanowires. The other peak, corresponding to the region highly strained to the silicon substrate, is labeled peak “C” and is attributed to the center of the nanowires. Studies of silicon nanowires oxidation23 help to understand the possible origin of this segregation. During the thermal oxidation, gold clusters diffuse

substrate, resulting in a diffraction signal mainly composed of the nanowires contribution. When α increases, the beam gradually enters the substrate, enhancing its contribution to the total diffraction signal. Based on the evolution of the different GIXD patterns shown in Figure 2, it is therefore clear that the diffraction peak at H = 3 corresponds to the substrate while the nanowires one is located at a lower H value. This difference in the scattering vector of the two peaks reveals a slight dilatation of the silicon lattice parameter in the nanowires. Indeed, the lattice mismatch, expressed as Δa/a = (aSiNWs − aSub)/aSub can be related to the shift of the scattering vector using Bragg’s law (2d sin(θ) = mλ) and the definition of the scattering vector q (q = 4π sin(θ)/λ): q − qSiNWs Δa = Sub a qSiNWs

One also may notice the narrow shape of the substrate peak, attesting to its very good crystallinity and long-range periodicity, whereas the nanowires peak is wider, indicating the finite size of the objects. Based on the full width at halfmaximum (fwhm) of the nanowires’ peak, the Scherrer formula19 allows to compute an estimated nanowire diameter of 89 nm. This value being slightly underestimated, because of the additional broadening of the peaks by the instrumental resolution, it can be stated that, among all the nanowires on the sample, the X-ray analysis will be mostly relevant to those having a diameter of ∼100 nm. Figure 3a displays an example of a GIXD pattern of sample B fitted with two Pearson7 functions in order to determine the exact position of the nanowires and substrate peaks, and 4513



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Figure 5. SEM micrographs of gold-catalyzed VLS grown silicon nanowires: (a) after simple chemical removal of the gold catalyst by I−KI etching and (b) after supplementary side etching by thermal oxidation−HF etching.

on the surface and through the silicon nanowire to reach the interface between Si and SiO2, resulting in a shell of gold-rich silicon while the center of the nanowire is partially emptied of it. In our case, after the HF etching step of group C, the nanowires should then display this gold-rich periphery and gold-depleted center, resulting in a strongly dilated periphery,13 revealed by the peak S, and a bulk silicon-like center, revealed by the peak C. The evolution of these two peaks versus the incidence angle (Figure 4b) shows different behaviors. The center of the nanowires presents a smaller lattice dilatation than before lateral etching (Figure 3), the strain is indeed divided by two, from 4 × 10−4 to 2 × 10−4. Its evolution along the length of the nanowires is consistent with previous results:13 the nanowire center is more strained to the silicon lattice parameter at its bottom than at its apex. This behavior is a strong signature that the thermal oxidation−HF etching step resulted in a decrease of gold contamination in the silicon nanowire center. Indeed, its lattice parameter remaining slightly strained, one can assume a residual gold contamination. However, the strain of the surface remains high and constant along the length of the nanowire, which could be explained by the presence of gold in this region of the structure at a similar level of contamination than for groups A and B. In order to verify the efficiency of the thermal oxidation−HF etching cycle to remove any traces of gold,17 MAD measurements were performed in the [100] direction to detect its presence in the nanowires and study its possible locations. Figures 5a and 5b respectively show SEM micrographs of silicon nanowires before (group B) and after (group C) lateral etching. It is clear that a single chemical etching is not efficient, since one can easily notice the presence of gold clusters on the sides of the wire in Figure 5a. However, in Figure 5b, SEM analysis does not detect the presence of any gold; all of the nanowires seem clean, with a smooth surface free from gold pollution. Figure 6 displays the results of MAD measurements performed on the three groups of samples A, B, and C, along with sketches illustrating the possible spatial distribution of the gold contamination that we propose. Analysis of the diffraction intensity variation before and after the gold LIII absorption threshold allows computation of the contribution of anomal atoms in the total diffraction signal.24 It is then possible to distinguish between the two different structure factor moduli involved in the diffraction: FN, which corresponds to normal atoms (Si), and FA, which corresponds to anomal atoms (Au), given within a scaling factor. The total structure factor modulus (FT, defined as normal + anomal) is also displayed for comparison with GIXD, where the latter is an image of the first. The positions of the peaks of the FT signal are indeed consistent with the fitted peaks of the GIXD experiments (see

Figure 6. MAD analysis along the [100] direction (plots) and proposed corresponding physical state of silicon nanowires (illustration sketches): (a) as-grown nanowires of group A; (b) nanowires after chemical gold etching of group B (the FT peak related to GIXD is indicated by the dashed line); and (c) thermally treated nanowires of group C (peaks C and S of FT are emphasized by the vertical dashed lines).

Figures 3a and 4a): one peak is found at the same H value (H ≃ 2.9988) for sample B, and two peaks are visible for sample C close to those found in GIXD near H ≃ 2.9982 and H ≃ 2.9995. For as-grown wires of group A, Figure 6a clearly shows that gold is present in the crystalline matrix of the wires and contributes to the diffraction signal, as revealed by the great amplitude of the anomal part FA. A closer look at the MAD 4514



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of two-dimensional (2D) devices. Besides the diffusion of gold toward the Si/SiO2 interface,23 a possible explanation for this lack of efficiency can be found in the atomic diffusion of gold through the silicon matrix during the thermal oxidation step. Indeed, based on the diffusion coefficient of gold in silicon (DAu(1000 °C) = 5 × 10−8 cm2 s−1)26 and the oxidation time (t = 20 min), gold can diffuse through l = (Dt)1/2 = 77 μm, which is long enough to diffuse through the nanowire and contaminate the entire structure.

signals reveals that the maximum of the anomal signal (peak A) is located at a smaller H value (larger lattice parameter) than the normal signal corresponding to the nanowires (peak N). We conclude that the regions where gold is present are more dilated than the regions where it is absent, which is consistent with previously reported results.13 Since the analysis of GIXD (Figure 4a) led us to assume that the dilatation strain is increasing from the center of the wire up to its surface, it can be deduced that gold is mainly located on the sides of the nanowires.16,25 After standard chemical gold removal by I−KI, the MAD analysis of group B (Figure 6b) also reveals a strong anomal signal. Its intensity is still important and has the same features than the one with as-grown wires: its maximum (peak A) is located at a lower H than the maximum of FN (peak N). However, even if the total signal is similar to that of sample A, the distance between peaks A and N in the reciprocal space is increasing, with the normal signal shifting toward H = 3. This can be interpreted as the signature of the decrease of the dilatation strain of the silicon matrix, probably due to the change in surface states before and after gold etching. This result implies that, even if gold has been roughly removed from the external surface of the wires by chemical etching, there is still some contamination as diluted atoms in the silicon matrix of the nanowires. In conclusion, I−KI wet etching is efficient to remove superficial gold on CVD-VLS grown silicon nanowires but is ineffective to thoroughly remove all traces of catalyst from the entire structure, which, therefore, remains contaminated. To further clean the gold from the group C wires, an 18-nmthick layer of silicon was etched from their surface by successive thermal oxidation and HF etching. Figure 4a showed that this treatment led to a strongly dilated periphery and a bulk siliconlike center, probably because of a diffusion of gold from the center toward the surface of the nanowires. Figure 6c confirms this analysis, since the two different peaks (C and S in Figure 4) are found again in the FT signal at the same position in the reciprocal space. We easily distinguish two separate peaks N1 and N2 in the normal signal, and we clearly see an anomal contribution A1 and A2 for each of them, attesting that there is still some gold remaining in the whole nanowires. Nevertheless, the anomal signal is weak, hardly out of the noise, meaning that the thermal oxidation−HF etching cycle managed to remove slightly more of the remaining gold after chemical etching. In order to compare the contribution of gold in both the center and periphery of the nanowires, the ratio r = FA/FN between the anomal (Au) and normal (Si) signal is calculated at the corresponding H values of peaks 1 and 2. Table 3 shows that r is smaller in the case of peak 2 than that for peak 1, attesting to the fact that gold contamination is less important in the center of the nanowires than in the vicinity of their surface. The

peak 1

peak 2

0.70

0.48

CONCLUSION

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AUTHOR INFORMATION

We showed that standard wet chemical etching of the gold catalyst of silicon nanowires grown by chemical vapor deposition in vapor liquid solid mode is not efficient enough to clean all traces of gold; the nanowires remain strained and contaminated by catalyst residues. The sequence of thermal oxidation followed by HF deoxidation also is not efficient enough to totally remove the contamination; gold is still present in the wires, probably because of its strong diffusion during the thermal oxidation step. These chemical and physical treatments create a “core−shell like” structure in the nanowires, featuring a center which is less strained and contaminated than the periphery. One interesting follow-up investigation will be to physically etch the surface of the nanowires in isotropic mode and at low temperature, to prevent any gold diffusion during the etching.

Corresponding Author

*E-mail: [email protected]. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This research was carried out at the European Synchrotron Radiation Facility in Grenoble, France. Special thanks go to the BM2-D2AM beamline staff for the technical support during the experiment time. The authors acknowledge financial support from the French Ministère de la DéfenseDirection Générale de l’Armement.

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REFERENCES

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Table 3. Ratio between the Intensity of the Anomal and Normal Signal of Group C for Both Peaks 1 and 2 r = FA(Au)/FN(Si)

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etching process, consisting of a thermal oxidation followed by an HF etching, is therefore not totally efficient, and leaves some traces of gold contamination in the silicon nanowires. This failure could explain why the electrical performances of the nanowire-based photovoltaic devices studied in ref 17 improved after this treatment but still remained not quite as good as those 4515



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Gold Contamination in VLS-Grown Si Nanowires - American Chemical

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