Growth of InP Layers on Nanometer-Scale Patterned Si Substrates Piester,†
Andrey Bakin,* Dirk Ingo Behrens, Hergo-Heinrich Wehmann, Erwin Peiner, Alexey Ivanov,‡ Detlef Fehly,§ and Andreas Schlachetzki
CRYSTAL GROWTH & DESIGN 2003 VOL. 3, NO. 1 89-93
Institute of Semiconductor Technology, Technical University at Braunschweig, Hans-Sommer-Strasse 66, D-38106 Braunschweig, Germany Received July 26, 2002;
Revised Manuscript Received November 3, 2002
ABSTRACT: For industrial applications of III/V on Si heteroepitaxial structures on exactly oriented (001)Si substrates are a prerequisite. An approach for high-quality InP on (001)Si is the growth on a patterned substrate. We employed nanometer-scale patterning of Si substrates and discuss the results in the present paper. We used self-assembled nanometer-scale three-dimensional InP islands as a mask for further Si substrate patterning. InP islands were grown by metal-organic vapor-phase epitaxy at 400 °C and in some cases afterward transformed during annealing at 640 °C. The samples were etched at different temperatures and durations in KOH- and NaOH-based etchants. We also used maskless nanometer-scale patterning of the substrates by applying boiling water or steps of cleaning procedures. Atomic-force microscopy was used to determine the morphology of the samples and to evaluate the dimensions of the etched structures. It is shown that to grow antiphase-domain-free and high quality InP layers on exactly oriented Si substrates it is necessary to pattern the surface of the substrates at nanometer scale. Introduction Fiber-to-the-home and local area networks are the main application areas where the telecommunication industry will face its next major advancesthe introduction of optical fibers into the subscriber domain. The biggest challenges for further progress are the modules converting the optical signals into their electronic form and vice versa. These converters have to be suitable for the fiber-optical wavelengths from 1.3 to 1.55 µm, also in view of bidirectional communication. They have to be available in large quantities at low cost. Heterostructures of direct band-gap material, as InP, on silicon as widely used substrate are of great interest for this new generation of optoelectronic devices. Such monolithic integration with silicon microelectronics is at the same time a possible candidate for solving the interconnect bottleneck on Si chips.1 Moreover, InP has also the potential for high-frequency applications as was shown recently by a 40 Gb/s InP-heterobipolar transistor photoreceiver in medium-scale integration.2 Today optical, optoelectronic, and electronic components are integrated employing hybrid technology,3 flip-chip4 mounting, or epitaxial lift-off.5,6 Optical technologies require tight alignment tolerances between components. Because of their sensitivity to misalignment and temperature change, hybrid integration or flip-chip bonding still remain complicated and timeconsuming with the corresponding costs consequences. Implementation of wafer direct bonding is aggravated by the mismatch in thermal expansion coefficient limit* Corresponding author. Dr. Andrey Bakin, Institute of Semiconductor Technology (IHT), Technical University at Braunschweig, Hans-Sommer-Strasse 66, D-38106 Braunschweig, Germany. E-mail:
[email protected]. † Physicalisch-Technische Bundesanstalt, Bundesallee 100, 38116 Braunschweig, Germany. ‡ IV. Physikalisches Institute, Universita ¨t Stuttgart, Postfach 106037, 70049 Stuttgart, Germany. § IVM Automotive Wolfsburg GmbH, Wolfsburger Landstrasse 22, 38442 Wolfsburg, Germany.
ing the temperature to which a bonded Si-III/V pair can be exposed.5 It was reported that the wafers debond if heated above 160 °C (for Si/GaAs).6 If a GaAs film is lifted off its original substrate and transferred to a processed silicon chip, the direct bonding is hampered due to a lack in planarity of the processed chip.7 The most convincing solution for a low-cost mass production of optoelectronic converters is the monolithic integration of III/V heterostructures with silicon microelectronics employing growth of the compound semiconductor layer on the Si wafer. Severe obstacles arise from the large mismatch in lattice parameter and thermal expansion coefficient between III/V layer and Si substrate which lead to the formation of lattice defects and residual stress. Various approaches were employed to implement the growth of high quality InP on Si with its 8% in lattice mismatch. These are thermal annealing of the layer in intermediate stages of growth and after growth, defect binding layer (for instance precipitates of dopants or intrinsic components), growth on patterned substrates up to thin free-standing structures, or use of special buffer layers (thick buffer, graded buffer, misfit grainlets), liquid interface, strained layer superlattices, and area-selective growth. Recently, it was shown that GaAs can be deposited on Si by employing an intermediate thin strontium-titanate layer.8 However, this compliant-substrate-based approach does not fit InP on Si growth with twice the misfit. It is known that GaAs is prone to rapid degradation.9 InPbased laser diodes on Si substrate seem to be more resistant in this respect. Rapid degradation at room-temperature operation does not occur in these diodes, despite the higher lattice mismatch.10 For the cases of growth with large mismatch (for instance GaN on sapphire etc.) selective nucleation followed by lateral epitaxial overgrowth, conformal growth,11 or pendeoepitaxy12 has proven to be successful in decreasing defect density by localizing the disturbed area to certain
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regions of the wafer that are not used in further device fabrication. In most of the above approaches off-oriented substrates are employed where the surface serves as a source of steps for nucleation of the layer. The reduced width of the terraces between these steps prevents the formation of defects, especially of antiphase domains. Such an approach was described for InP conformal growth on (2°-4°)-off Si substrate13 or even for SiC on 8°-off SiC substrate growth.14 For applications of heteroepitaxial structures on Si monolithically integrated with silicon microelectronics, it is necessary to develop the growth of these structures on exactly oriented (001) substrates since it is the basis of all industrial processes of involved silicon microelectronics production. Substrate patterning was used as a method to obtain large area layers in highly mismatched systems on exactly oriented substrates. Growth of GaAs and GaP layers on patterned Si substrates even at room temperatures resulted in monocrystalline layer formation.15 Instead of the growth temperature, the planarity of the substrate and the features of the substrate patterns were found to be the most critical points. A new approach in this direction is nanoheteroepitaxy.16 Stateof-the-art lithography is used to pattern substrates on the nanoscale level prior to growth. Selective-area epitaxial growth is then carried out and the epitaxial layer nucleates as an array of nanoscale islands. In contrast to planar epitaxy, a nano-island consisting of a substrate hillock covered by a selectively grown epitaxial material can deform both vertically and laterally. Thus, the mismatch strain is distributed in three dimensions and additionally between substrate and layer leading to a further reduction of strain in the layer. Furthermore, if mismatch dislocations are formed in the island they can glide or climb to an island edge. Such a mechanism is practically impossible for planar epitaxy. However, nanoscale lithography is a complicated and expensive step. As an alternative, we employed a maskless process to prepare Si substrates by use of a NaOH-based solution. However, the InP growth on the resulting micrometer-scale islands led to poor quality layers. A reduction of the pattern scale was achieved using either a nanometer-scale mask or maskless etching. These novel approaches to nanometer-scale patterning of Si substrates are described in the present paper. InP layers have been grown on these wafers. The samples were investigated using atomic-force microscopy (AFM), scanning electron microscopy (SEM), transmission electron microscopy (TEM), and defect etching. Experimental Results and Discussion Figure 1 schematically maps our experiments. Initially, we employed maskless etching of (001) Si substrates in a NaOH-based etchant resulting in micrometerscale pyramids faceted by {111} planes which is a standard process in solar-cell production17 (cf. Figure 1a,c,d, approach nr.1 “µm”). The patterning was carried out at 90 °C for 45 min in 4.5% NaOH to which we added 5 vol % of 2-propanol. Pyramids with base dimensions of some micrometers were observed using AFM and SEM (cf. Figure 1c). InP layers were grown on the patterned Si substrates using metal-organic
Bakin et al.
Figure 1. Schematic description of our experiments in InPon-Si growth.
Figure 2. TEM image of the cross-section of InP-patterned Si interface: (a) twins and dislocations originating in the planes of pyramids; (b) dislocations originating in the sides of pyramids are bending and attracted to the twins near the Si surface leaving areas between the boundaries of APDs and twins free of dislocations.
vapor-phase epitaxy (MOVPE). The growth was performed in the horizontal IR-heated MOVPE machine at low pressure (20-100 hPa) under a total hydrogen flow of 8 L/min. Prior to the growth the wet-chemically cleaned Si substrates were thermally treated at 950 °C for 15 min in a hydrogen atmosphere to remove the native oxide. Arsin (AsH3) was introduced during the cooling phase and then growth was started.18 AsH3 was used since it is stable only up to 700 °C, whereas for phosphine (PH3) this temperature is about 800 °C.19 Thus, AsH3 decomposes more readily under identical conditions setting free a greater number of group V components to enhance growth by forming doublelayer steps and more stable Si-As bonds.20,21 For characterization, we used optical microscopy with Nomarski contrast conjointly with defect etching revealing dislocations and TEM (Figure 2). We find a high density of antiphase domains (APDs) and twin lamellae. The areas between the antiphase boundaries and the lamellae are essentially free of dislocations. TEM investigations (Figure 2a) show that most of the twins originate on the planes of the initial pyramids on the Si surface, thus supporting our results on the formation mechanism of twin lamellae in InP grown on Si and on GaAs covering
Growth of InP Layers on Si Substrates
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Figure 3. AFM image (2 × 2 µm2) of as-grown InP dots on Si after 4 s of growth. Table 1. Statistical Data of InP Islands on (001)Si as-grown growth av duration height variance (s) (nm) (nm2) 2 3 4 8 15
29 14.5 9 9.2 14
4 0.36 0.526 0.64 0.25
after annealing average density (cm-2)
5 × 109 1.5 × 1010 2.5 × 1010 2.5 × 1010 3 × 1010
av height variance (nm) (nm2) 12.9 7 7
1.21 1.0 1.4
average density (cm-2) 5 × 109 1.8 × 1010 1 × 1010 1.5 × 1010
Si.22 Dislocations originating on the sides of pyramids are bending and are attracted to the twins near the surface of the Si substrate (Figure 2b). Further improvements of the quality of the InP layer grown on a structured substrate are possible if smaller size patterning and also pyramids faceted by other than (111)-planes could be employed. We developed a new approach to nanometer-scale patterning of the Si substrates by taking advantage of self-assembled nanometer-scale three-dimensional InP islands as a mask for further Si substrate structuring. InP islands were grown at 400 °C (cf. Figure 1b). Figure 3 shows an AFM topograph of the surface obtained for a growth duration of 4 s. The average density of these self-organized islands increases with the growth duration and reaches a value of 2.5 × 1010 cm-2 for growth durations above 4 s (Table 1). Typical heights of the pyramids are from 9 to 29 nm. High densities of islands are explained by the fact that the InP/Si heterostructure is highly strained due to the lattice mismatch of about 8%. The strain is partially relieved by the formation of islands which are elastically strained relative to the substrate. Such coherently strained island formation was also observed for SiGe/Si23 or InAs/Si24 heterostructures. The latter ones are utilized in quantum dot lasers.25 To examine the influence of surface migration on the distribution and properties of the islands we annealed selected samples under PH3 flow. This was also performed in the MOVPE reactor by heating the system up to 640 °C and cooling immediately after reaching the temperature. We note that the mean island height decreased, the height distribution broadened and the island density reduced by the annealing step (columns 5, 6, and 7 of Table 1).26 The samples with InP dots of different dimensions were etched at various temperatures and durations in 30% KOH at 60 °C and in NaOH-based etchant described above at 90 °C (cf. Figure 1; approach nr. 2 “100 nm”). AFM was used to determine the surface topography of the samples and to evaluate the dimensions of the etched pyramids (Figure 4). From these measurements, we found the facets of the pyramids etched in NaOH to be {111} (Figure 4 a,b), whereas the structures etched in KOH are actually conical (Figure 4 c,d). As it
Figure 4. AFM images of patterned substrates using InP dots as a mask: (a, c) 1 × 1 µm2; (b, d) 0.5 × 0.5 µm2; (a, b) after etching in 4.5% NaOH with 5 vol % of 2-propanol at 90 °C for 45 min; (c, d) after etching in 30% KOH at 60 °C for 60 min.
is clear from the results obtained Si substrates have been patterned at nanometer-scale using self-organized InP dots as a mask. Trial experiments led to very inhomogeneous layer growth. Optimization is needed to improve the uniformity of patterning to use such surfaces for further epitaxial growth. Further decrease of the scale of patterning as well as improvement of the uniformity of patterning have been achieved using maskless processing of Si substrates (approach nr. 3 “nm”, Figure 1a,c,d). We investigated nanometer-scale patterning in the first case by boiling Si substrates in deionized water for 10-40 min27 and in the second case by employing oxidation (thickness of oxide about 0.5-1 µm), removal of the oxide layer and a final standard pre-epi cleaning (5 min etching in H2SO4/H2O2/H2O ) 5:1:1 and 30 s etching in HF). The results are shown as AFM topographs in Figure 5 a,b, respectively, and compared with the standard pre-epi cleaning process of epi-ready substrates (5 min etching in H2SO4/H2O2/H2O ) 5:1:1 and 30 s etching in HF) prior to InP/Si growth (Figure 5c). A significant roughening of the substrate surface was observed after both procedures with clear differences for the different suppliers. Root-mean-square (RMS) values of the substrate roughness after different processing steps are given in Table 2. We performed InP growth experiments on unpatterned and nanometer-scale patterned (001)Si substrates. The relation between Si substrate roughness and APD formation in InP layers is shown in Table 2. All layers described in the Table 2 are 1.5 µm thick. As follows from the analysis of the data in Table 2, there is an optimum range of Si wafer roughness that provides APD-free InP layer growth. Optical microscopy images of the layers are shown in Figure 6. As clearly seen (cf. Figure 6a), the growth on properly nanometer-scale patterned substrates is antiphase domains free, whereas on the unpatterned substrate (cf. Figure 6b) the irregularly shaped structures of domains appeared. We expect that the influence of nanoscale patterning is related to double-atomic or monoatomic steps formation.
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Figure 5. AFM images (0.5 × 0.5 µm2) of Si substrates patterned during different stages of processing: (a) boiling in deionized water; (b) complete standard pre-epi cleaning including oxidation; (c) only standard pre-epi cleaning.
Figure 6. Optical microscopy images of 1.5-µm-thick InP layers grown on exactly (001) oriented Si substrate: (a) nanometer-scale patterned substrate; (b) unpatterned substrate.
Table 2. Relation between Si Substrate Roughness and APD Formation in InP Layera Si-processing As supplied (only pre-epi cleaning) oxidation and pre-epi cleaning As supplied (only pre-epi cleaning) oxidation and pre-epi cleaning 40 min boiling in H2O 40 min boiling in H2O a
RMS, Si substrate nm APDs supplier 0.2 0.34 0.45 0.48 0.57 0.70
++ + ++
A A B B A B
++ ) many APDs; + ) some APDs; - ) no APDs.
Moreover, if nanopatterns are formed on the Si surface, the crystalline defects will merge during epitaxy and cancel each other out. Too high a value of roughness of the substrate surface on the other hand leads to APD formation (cf. Table 2). Beyond the suppression of APD formation the nanostructure of the Si surface results in a decrease in layer strain at early stages of the InP growth. At the beginning, the epitaxial growth is area-selective since the epilayer nucleates as an array of nanoscale islands. In contrast to planar epitaxy, a nano-island consisting of a patterned substrate selectively covered by epitaxial material can deform both the growing island and the patterned substrate, so that the mismatch strain is effectively distributed in three dimensions. Additionally, if mismatch dislocations are generated in the separate islands they can glide or climb to an island edge. An example of a scanning electron microscopy image of etch pits density (EPD) of the 1.5-µm-thick layer grown on nanometer scale patterned exactly oriented Si substrate is shown in Figure 7. EPD investigations have shown that nearly all dislocations are associated with twins. We also investigated the layers by X-ray diffraction (XRD). An example of X-ray diffraction (004) peak of a 2-µm-thick layer grown on nanometer-scale patterned exactly oriented Si substrate is shown in Figure 8. The InP layers grown on nanometer-scale-patterned Si
Figure 7. Scanning electron microscopy image of EPD of the 1.5-µm-thick layer grown on nanometer-scale patterned exactly oriented Si substrate.
Figure 8. X-ray diffraction (004) peak of the 2-µm-thick layer grown on nanometer-scale patterned exactly oriented Si substrate.
wafers show very narrow rocking curves with a slight decrease of the full width at half maximum (FWHM) from 90 to 75 arcsec with increased InP layer thickness from 2 to 4 µm, respectively. Summary Si substrates have been patterned at micrometerscale using maskless etching of the substrates. Further decreasing of the pattern scale has been achieved using a nanometer-scale mask or maskless etching. Si substrates have been patterned at nanometer-scale using
Growth of InP Layers on Si Substrates
self-organized InP dots as a mask. However, optimization is needed to improve the uniformity of patterning. A further decrease of the scale of patterning was achieved using maskless processing of Si substrates. High quality InP layers with XRD peaks of 75 arcsec FWHM were grown on these substrates. Our investigations with InP on Si as an example show that for the growth of heteroepitaxial lattice-mismatched layers on exactly oriented (001)Si substrates it is necessary to realize an optimized nanometer-scale patterning of the surface of the substrates to avoid APD formation and to reduce layer strain. This conclusion can be further transferred to defect elimination in other heteroepitaxial systems on exactly oriented substrates. Acknowledgment. This work was partly funded by the Deutsche Forschungs Gemeinschaft (DFG) and by EU (Project IST-2001-32358 “QUDOS”). Patterning of Si wafers on micrometer-level at the Institute of Solar Energy, Prof. R. Hezel is greatly acknowledged. References (1) http://public.itrs.net. (2) Huber, A.; Huber, D.; Morf, T.; Ja¨ckel, H.; Bergamaschi, C.; Hurm, V.; Ludwig, M.; Schlechtweg, M. Electron. Lett. 1999, 35, 897-898. (3) Ahadian, J. F.; Fonstad, C. G. Opt. Eng. 1998, 37, 3161-3174. (4) Hinton, H. S. IEEE J. Select. Top. Quantum Electron. 1996, 2, 14-23. (5) Plo¨ssl, A.; Kra¨uter, G. Mater. Sci. Eng. 1999, R25, 1-88. (6) Lehmann, V.; Mitani, K.; Stengl, R.; Mii, T.; Go¨sele, U. Jpn. J. Appl. Phys. 1989, 28, L2141-L2143. (7) Ersen, A.; Schnitzer, I.; Yablonovitch, E.; Gmitter, V. Sol.St. Electron. 1993, 36, 1731-1739. (8) Telford, M. III-Vs Rev. 2002, 15, No. 1, 44-46. (9) Van der Ziel, J. P.; Dupuis, R. D.; Logan, R. A.; Pinzone, C. Appl. Phys. Lett. 1987, 51, 89-91. (10) Sasaki, T.; Mori, H.; Tachikawa, M.; Yamada, T. J. Appl. Phys. 1998, 84, 6725-6728.
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