Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium

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Letter pubs.acs.org/NanoLett

Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits Bingyan Chen,† Panpan Zhang,† Li Ding,† Jie Han,§ Song Qiu,§ Qingwen Li,§ Zhiyong Zhang,*,† and Lian-Mao Peng*,† †

Key Laboratory for the Physics and Chemistry of Nanodevices and Department of electronics, Peking University, Beijing 100871, China § Key Laboratory of Nanodevices and Applications, Suzhou Institute of Nanotech and Nano-bionics, Chinese Academy of Science, Suzhou, 215123,China S Supporting Information *

ABSTRACT: Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V. KEYWORDS: Carbon nanotube, medium scale integrated circuit, field-effect transistor, threshold voltage variation

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from low yield, nonideal logical output level, need high supply voltage or even multiple voltages, and can only conduct simple functions. In general, these questions about integrated density and performance in CNT ICs mainly originate from the nonuniformity of CNT FETs, which were always fabricated with low yield and large performance variations owing to reasons from materials and fabrication process. Fabrication of CNT FETs with high yield and high uniformity is necessary for designing and constructing complicated ICs. However, most researches on CNT electronics concentrated on device performance rather than uniformity, which obviously hinders the development of CNT ICs. In this work, we fabricated top-gated p-FETs based on CNT network thin films prepared using solution processed CNTs, and these transistors present high yield and highly uniform performance, in particular with small threshold voltage variation. Through carefully selecting the supply voltage of CNT FETs in ICs, CNT FETs can work under a proper working regime, and the reliability of CNT FETs is significantly improved. Taking advantage of transistors with well-controlled

arbon nanotubes (CNTs) have been considered as an excellent channel material to build field-effect transistors (FETs) for future applications in integrated circuits (ICs) with such exciting advantages as high speed, low power dissipation, and potential applications in flexible or transient electronics.1,2 In the past 15 years, extensive investigations have been carried out on CNT FETs based nanoelectronics,3−8 and these studies were mainly focused on two major directions. One is on device explorations, that is, exploring new devices and device physics, fabrication, and structure/performance optimization. As a result, CNT FETs were shown to present huge potential on performance that outperforms Si CMOS FETs especially at sub-10 nm technology nodes.7,8 The other direction is on ICs, that is, exploring all kinds of simple ICs using CNT FETs as building blocks. Various kinds of ICs based on CNT FETs, including fundamental logic gates,9−13 ring oscillators,14−17 4bit decoder,18 flip-flop,19 full-adder, d-latch,20 8-bits BUS system,21 and even a computer22 have been fabricated to demonstrate the application possibility of CNT electronics. However, those published CNT ICs usually met obvious obstacle of low integration density, for example, and few CNT ICs that consist of more than 100 transistors have been realized in experiments. It is well-known that low integration density must limit the function and performance of ICs and then limit their practical applications. In addition, CNT ICs usually suffer © XXXX American Chemical Society

Received: May 19, 2016 Revised: July 16, 2016

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DOI: 10.1021/acs.nanolett.6b02046 Nano Lett. XXXX, XXX, XXX−XXX

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Figure 1. Structure and properties of top-gated FETs based on CNT films. (a) SEM image of deposited CNT network on Si/SiO2 substrate. Inset: SEM image of an as fabricated top-gate device. The three yellow regions from top to bottom represent the source, gate, and drain metal, respectively. The black dot area is the gate oxide and the blue dot area is the channel. The scale bar is 2 μm. (b) Transfer characteristics of a typical top-gate FET, the voltage bias Vds = −1 V. (c) Output curves of the FET as in (b). (d) Transfer curves of 120 devices.

uniformity and insulativity was fabricated on the CNT film as gate dielectric, and palladium was used as the contact to form good p-type contact in CNT FETs. Inset in Figure 1a shows the SEM image of an as-fabricated CNT FET, where the three yellow regions from top to bottom represent the source, gate, and drain, respectively. Considering improvement of uniformity and density, the dimension of FETs was designed to have channel length Lc = 7 μm, channel width W = 5 μm, and gate length Lg = 5 μm. Further scaling the dimension of FETs can improve the performance and density but must lead to degraded uniformity and occasionally low on−off ratio owing to the limitation from semiconducting purity and density of CNT network film. If quality of CNT material is further improved, the corresponding CNT FETs could be further scaled down while maintaining high uniformity for construction of ICs. Transfer and output curves of a typical CNT FET are shown in Figure 1b,c, indicating that the FET presents typical p-type behavior and excellent output characteristics including linear I−V at low bias and saturation at high bias. It is worth mentioning that Y2O3 thin film was used here as gate dielectric for CNT thin film FETs. Usually high quality and uniform HfO2 or Al2O3 films grown through atomic layer deposition (ALD) were used as gate dielectric for top-gated CNT thin film FETs.40 Because only the delocalized π-bond exists on the surface of CNTs, the growth of uniform thin highκ film directly on the surface of CNTs via ALD is very difficult. As a result, thick HfO2 film should be grown on substrate by ALD-grown to bury CNTs to avoid gate leakage, which limits the gate efficiency.10,21,22,41 Yttrium film has excellent wetting with CNTs through electron-beam evaporation and can be oxidized to form uniform Y2O3 film on CNT film. Y2O3 insulator can provide high gate efficiency for CNT thin film FETs42 and thus contributes to improve uniformity of devices. As basic building blocks for ICs, FETs should be fabricated with high yield and performance uniformity. To estimate the yield and performance uniformity of CNT FETs, 120 individual

yield and high uniformity, various logical and arithmetical gates, shifters, and d-latch circuits were demonstrated with rail-to-rail output. Particularly ICs with medium scale and complicated functions such as a 4-bit adder and a 2-bit multiplier have been realized for the first time, and these medium scale ICs are powered by a single low supply voltage of 2 V. Preparation of uniform CNT materials on insulating substrate is the precondition to realize uniform CNT FETs and then the selection of CNT materials should be carefully considered. Typical FETs based on single CNTs exhibited intrinsic high performance but suffered from low uniformity and yield as well as weak stability.23−25 Aligned CNTs are ideal materials for high-performance CNT circuits.26 However, it remains a big challenge to realize pure semiconducting CNT arrays with high density27 and even one metallic CNT left in the device will cause the transistor to short-circuit and invalidate the whole ICs. Compared with the first two kinds of CNT materials, network thin films prepared from CNT solution are more suitable to construct FETs with high uniformity and in wafer scale,28 because the electrical properties are determined by average effect of massive CNTs, which have a much better tolerance of metallic CNTs.29−34 Furthermore, the separation and purification of semiconducting CNTs is already a relative mature technology and the ratio of semiconducting CNTs can be improved to higher than 99%.35−38 Although the advantages of CNTs, such as high carrier mobility, are sacrificed owing to the tunneling of carrier between junctions, CNT network thin film can provide good uniformity to construct highly uniform FETs potentially, which is a must for building large-scale CNT ICs able to work properly. The FETs were fabricated on network thin films prepared from CNT solution with semiconducting purity higher than 99%,39 and a scanning electron microscope (SEM) image of as deposited CNT film on silicon wafer covered with 500 nm SiO2 is shown in Figure 1a. Yttrium oxide (Y2O3) film with excellent B

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Figure 2. Statistics of key performances for 120 CNT TFTs with different measurement conditions. (a) Transfer curves of 120 devices at working voltage Vds = −1 and −2 V respectively. Statistic distribution histograms of (b) on-state current Ion, defined as current at Vgs = Vds = −VDD; (c) Ion/ Ioff, where Ion is defined as current at Vds = −VDD, and Ioff defined as current at Vgs= 0 V; (d) SS; (e) Vth, where the average value is −0.7 V and the standard deviation σ = 34 mV. (f) Transfer curves of a typical CNT FETs measured at Vds = −2 V while with different sweeping Vgs directions. Inset: statistic distribution histogram of hysteresis voltage value of these 120 CNT FETs.

will analyze the main performance parameters statistically. Figure 2b,c shows the statistic distribution of extracted on-state current Ion (at Vgs = Vds = −VDD) and current on/off ratio (Ion/ Ioff), respectively. CNT FETs presented much higher Ion values (about 3 μA/um) at VDD = 2 V than these (about 0.6 μA/um) at VDD = 1 V owing to the larger bias and overdriven Vgs. In addition, the current on/off ratio at VDD = 1 V is only around 2.5 decades, which is much lower than the value of about 3−3.5 decades at VDD = 2 V. Higher Ion and Ion/Ioff of FETs should lead to higher speed and lower power dissipation of ICs respectively, which also proves the validity of setting VDD to 2 V in this work, and hereafter we only focus on key parameters distribution at VDD = 2 V. The subthreshold swing (SS) shown in Figure 2d is ranged from 130 to 230 mV/Dec with an average value of 170 mV/Dec, which is similar to most published SS values for FETs based on CNT network thin films.18−20,44 Compared with other parameters of FETs, uniformity on Vth is much more important for ICs.45,46 As shown in Figure 2e, Vth of 120 CNT FETs ranges from −0.6 V to −0.8 V, which complies with normal distribution with small standard deviation of σ = 34 mV. As a reference, the typical standard deviation of Vth in Si MOS FETs with 0.30 μm channel length is about 10.8 mV,47 and the value in 65 nm technology node Si CMOS is about 25.58 mV.48 The standard

FETs were fabricated and measured (optical image shown in Figure S1a in Supporting Information) and the transfer curves are shown in Figure 1d. The measured FETs exhibited 100% yield and a sharp distribution of transfer curves. It should be noted that all of the CNT thin film FETs are enhanced p-FETs, which is important for IC applications with low power and single power supply. In addition, all of FETs in Figure 1d exhibited the minimum current at around 0 Vg, indicating the CNT film remains intrinsic even after the complex fabrication processes. It is well-known that transistors in ICs should work at a fixed supply voltage VDD, and we should define VDD before estimating performance of any transistor. In conventional ICs based on metal−oxide−semiconductor (MOS) FETs, the supply voltage VDD is preferred to be set as 3 threshold voltage (Vth) to balance performance and leakage current.43 Because the as-fabricated CNT FETs here are with Vth of about −0.65 V as shown in Figure 1d, ICs based on these CNT FETs should be supplied with VDD = 2 V according to the 3 Vth rule. Therefore, we remeasured the transfer curves of 120 CNT thin film FETs at VDD = 2 V, that is, sweeping Vgs from −2 to 0 V with fixed Vds = −2 V, and the measured results are shown in Figure 2a in which transfer curves with VDD = 1 V are also given as a reference. Before using these FETs to construct ICs, we C

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Figure 3. (a) Circuit design (left) and SEM image (right) of a CNT inverter, the scale bar is 5 μm. (b) A typical VTC and gain characteristics of an inverter. Inset: VTC (solid green line) and its mirrored curve (dotted red line). The shaded area “eye” represents the noise margin of the inverter. (c) VTCs and (d) statistic distribution histogram of the inverter gain for 25 devices. (e) Circuit diagram and SEM image of a 21-stage ring oscillator. (f) The inverse of frequency versus stage number diagram for different ring oscillators. The propagation delay of the 7, 11, and 21 stage ring oscillator is 2.11, 2.27, and 2.80 μs, respectively. Inset: output waveform of the 21-stage ring oscillator.

curve (dotted red line). The shaded area “eye” represents the noise margin of the inverter. The large area of the “eye” figure indicates high noise margin of the inverter, which allows for constructing complex circuit with more transistors and deeper logical depth. Twenty-five inverters were fabricated to test the performance distribution. As shown in Figure 3c, the 25 inverters show a good voltage transfer behavior and uniformity under VDD = 2 V. Figure 3d shows the statistic distribution of the inverters’ voltage gain, which is around 90 and some can reach 100. It is worth noting that the inverters can also work at a lower voltage such as VDD = 1 V with a voltage gain ∼45 (see Figure S2 in Supporting Information). Constructing ring oscillator using inverters is an effective and reliable way to test yield, uniformity and speed of transistors, and then ring oscillators with different stage numbers as 7, 11, and 21 have been fabricated based on CNT inverters. Figure 3e shows the circuit diagram and SEM image of a 21-stage ring oscillator. The output of ring oscillators were measured at VDD = 2 V as shown in Figure S3 (see Supporting Information), and we summarize the relation between oscillation frequency f and stage number n for different ring oscillators in Figure 3f, indicating the total delay 1/f is linearly dependent on the gate stage n. More specifically the propagation delay values of CNT inverter retrieved from 7, 11, and 21 stage ring oscillators are

deviation of 34 mV is still larger than that in commercial ICs but is a much smaller value compared to the selected supply voltage of 2 V. Moreover hysteresis-free Vth is the necessary condition for FETs which can work stably in ICs. It is obviously that the CNT FETs present very small Vth hysteresis (ΔVth) at VDD = 2 V as shown in Figure 2f, and 90% of FETs exhibit ΔVth smaller than 50 mV. Although the performance of our FETs with average SS of about 170 mV/Dec and average mobility of about 18 cm2/V·s (see Figure 2d and Figure S1b in Supporting Information) is not outstanding compared to other published results, the high uniformity in Vth and negligible Vth hysteresis are more important for constructing ICs with large scale and complicated functions. Also, we now consider constructing ICs by using these uniform CNT FETs. First, the simplest IC, the inverter, also known as NOT gate, was constructed based on our p-FET with pure p-FET logic style. Figure 3a shows the circuit design diagram and SEM image of the inverter in which the bottom p-type transistor acts as active load with its gate connected to the output terminal. A typical voltage transfer characteristic (VTC) of the fabricated inverter is shown in Figure 3b, which exhibits almost rail-to-rail output and very high voltage gain (∼85) at VDD = 2 V. Figure 3b inset shows the VTC (solid green line) and its mirrored D

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Figure 4. (a) Circuit diagrams (upper) of NAND, NOR and XOR gates, and optical image (lower) of a XOR gate. The AND, OR, and XNOR gates are realized by adding an inverter after the output terminal of the NAND, NOR, and XOR gates, respectively. (b) Output waveforms for the six logic gates: AND, NAND, OR, NOR, XOR, and XNOR and the corresponding A, B inputs. (c) Input and output waveforms of the shifter conducting two kinds of function: pass through (setting (H1, H2, H3) as (1, 0, 0) or (0, 0, 1)) and shift (setting (H1, H2, H3) as (0, 1, 0)). (d) Circuit design (top) and optical image (bottom) of a D-LATCH. (e) Input and output waveforms of a D-LATCH.

2.11, 2.27, and 2.80 μs, respectively. The consistency of propagation delay per gate among ring oscillators with different stage numbers strongly reflects the good performance uniformity and high yield of the transistors. In addition, the propagation delay per gate of 2.2 μs is almost the fastest ring oscillators based on CNT networks at a low supply voltage of VDD = 2 V, and the gate delay can be further lowered through scaling down the dimension of the CNT FETs or improving the supply voltage. Bitwise operation, as the most common function in ICs, counts on logic gates as basic circuit units, including NOT (inverter), NAND, AND, NOR, OR, XOR, and XNOR. We fabricated all of these basic logic gates based on p-type FETs, and circuit diagrams of NAND, NOR, and XOR are shown in Figure 4a, where A and B present the inputs and Y presents the output. In particular, XOR gate is a combinational logic circuit, consisting of 3 NAND gates and 2 NOT gates (total of 13 transistors), and the optical image of a fabricated XOR is shown in the lower part of Figure 4a. AND, OR, and XNOR gates are realized by cascading an inverter to the output terminal of NAND, NOR, and XOR gates, respectively. All of these six kinds of basic logic gates were measured at VDD = 2 V and their output waveforms are showed in Figure 4b. It should be noted that all of these gates exhibited almost perfect high and low

logic level output, that is, rail-to-rail output, which is attributed to the use of highly uniform FETs and well-designed supply voltage in this work. Besides, the logic gates can also work at a lower voltage. For example, the XNOR gate, consisting of 15 pFETs, can work well under VDD = 1 V (see Figure S4 in Supporting Information) with slight high-level degradation. However, the performance uniformity of basic logic gates at VDD = 1 V are not good enough for constructing more complex circuits. Bit shift is also a fundamental operation frequently used for data processing in digital ICs but has rarely been realized in CNT-based ICs. Here, we demonstrated a 2-bit circular shifter using pass-transistor logic, and its circuit diagram and optical image are shown Figure S5 (see Supporting Information) in which (A, B) and (Y1, Y2) are 2-bit input and output, respectively, and (H1, H2, H3) are control signals. Typical functions including pass through and shift were demonstrated as shown in Figure 4c, which indicates that a high-performance 2-bit shifter has been realized based on CNT for the first time. Latch is a kind of important function for digital IC applications because it plays an essential role for data storage in sequence circuit. A D-latch was designed based on p-FETs and was fabricated as shown in Figure 4d in which D, CLK, Q, and Q′ are input, clock, output, and complementary output E

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Figure 5. Carbon nanotube integrated circuits. (a) A schematic diagram of the fabricated carbon nanotube integrated circuit. (b) Circuit design (top) and optical image (bottom) of a full adder. (c) Input and output waveforms for the full-adder. (d) Circuit design (top) and optical image (bottom) of the 4-bit adder. (e) Output voltage levels of 15 kinds of addition combination of the 4-bit adder.

block in the arithmetic logic unit (ALU). However, full adders based on CNT FETs have seldom been realized owing to its large logical depth, which requires highly uniformity and good output voltage of each components. Figure 5b shows the circuit design diagram of a 1-bit full-adder and its optical image after fabrication. The 1-bit full-adder is composed of 3 NAND gates and 2 XOR gates for a total of 35 p-FETs. For input terminals, A and B are inputs to be added and C is the carry from previous addition. For output terminals, S is the output sum and and Ci is the carry for next addition. The functional test results of the 1-bit full adder are shown in Figure 5c, which shows all correct full adder functions with small output voltage loss of less than 10% (compared to VDD = 2 V). The high performance of the 1-

data, respectively. Figure 4e shows the measured input and output waveform of the fabricated D-Latch at VDD = 2 V. Q follows D at high CLK period (during 80−120 ms) whereas it remains unchanged at low CLK period (during 40−60 and 140−160 ms). The output Q′ is the complementary signal of Q. It is obvious that both of Q and Q′ exhibit right logic level of D-latch function with little voltage loss. Because the basic logical gates or sequence circuits demonstrated above present high-performance owing to the high yield and good uniformity of transistors, ICs that are more complex are thus constructed based on these CNT p-type FETs as shown in Figure 5a. Full adder is an important combinational circuit for arithmetic operation, usually used as a basic building F

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supply voltage

number of transistors

logical depth

transistor scale (L × W)

ref 18

4-bit decoder

−5 V

88

2

ref 19

flip-flop

−5 V

28

5

∼100 μm × 500 μm 100 μm × 100 μm

ref 22

2-bit adder

3 V and −5 V

96

15

∼1 μm × 130 μm

ref 49

finite-state machine (2-bit adder) 4-bit adder

2.3 V (operating) ± 8 V (programing) 2V

180

n/a

n/a

140

12

7 μm × 5 μm

this work

scale ∼14.6 mm × 8.0 mm ∼2.3 mm × 1.0 mm ∼1.3 mm × 0.7 mm ∼0.2 mm × 0.03 mm ∼0.30 mm × 0.17 mm

material CNT network CNT network CNT array Ge/Si nanowire CNT network

Figure 6. Carbon nanotube multiplier. (a) Circuit design and (b) optical image of a 2-bit multiplier. (c) Input and output waveforms for the 2-bit multiplier.

bit full adder indicates the possibility of constructing lager scale ICs based on these CNT FETs. To demonstrate the high uniformity and performance of our CNT FETs, we further fabricated a 4-bit adder, which is a medium scale integrated circuit and has not been realized based on CNTs. The circuit design diagram and optical image are given in Figure 5d, showing the area of the fabricated 4-bit fulladder is totally about 300 μm × 170 μm. The 4-bit adder is made up by four 1-bit full-adders in parallel and consists of 140 transistors with 12 stages logical depth. We tested the output voltage level of 15 kinds of addition combination (A3 A2 A1 A0, B3 B2 B1 B0), including (0000, 0000), (1111, 1111), (1001, 1010), (0110, 0101), (1101, 1010), (0010, 0101), (1101, 1110), (0010, 0001), (1010, 0011), (1001, 0101), (0110, 1010), (1101, 0101), (0010, 1010), (1101, 0001), and (0010, 1110), and the measured results are shown in Figure 5e, illustrating that the 4-bit full-adder exhibits right logical function. Although some complicated ICs based on CNT networks or arrays have been demonstrated, it is the first time to realize 4-bit adder. Table 1 compared our 4-bit adder with other published complicated ICs based on CNTs and other nanomaterials through using some key metrics reflecting integrated density and complexity. Compared to other published CNT ICs with complicated functions, the 4-bit

full-adder in this work presents more transistors, smaller total area, and lower supply voltage, which means higher density and lower dissipation. The successful demonstration of such a complicated IC is mainly benefitted from high uniformity and yield of CNT FETs, especially the suitable Vth with small variation, and also indicates the FETs based on CNT network are ready for constructing medium scale ICs. In addition, we tried to realize multiplication, which is a more complex operation and has not been realized in CNT ICs yet. A 2-bit multiplier is designed using basic logic gates as shown in Figure 6a, and the fabricated IC based on CNT p-FETs is shown in Figure 6b. The inputs are two 2-bit numbers (A1 A0) and (B1 B0), and the output is a 4-bit number (F3 F2 F1 F0). The sequence test results shown in Figure 6c demonstrates the full function of a multiplication operation with little logical level loss. It should be noted that the output voltage loss of the 4-bit adder is larger than that of other simpler circuits, which indicates that ICs consisting of several hundreds of FETs reached the fabrication limit at current uniformity level of FETs. Construction of larger scale ICs requires more uniform CNT FETs and other developed processes including interconnect technology. In fact, the performance uniformity of CNT FETs can be further improved from several aspects. G

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generated by signal generator (Agilent MXG N5181A). The output was measured by an oscilloscope (Agilent DSO7054A).

First, the uniformity can be improved through increasing the number of CNTs in channel since more CNTs will lead to less variation on number. The number of CNTs in channel can be improved by increasing CNT density or the channel area of FETs. Moreover optimization of the fabricating process is also helpful for improving the uniformity of CNT FETs. The fabrication process used in this work is shown to be less mature than that used in standard Si CMOS foundry, but we trust there is plenty of room for the improvement of CNT ICs. In conclusion, we present a systematic investigation from transistors to ICs based on carbon nanotube networks thin film and demonstrated how to fabricate ICs according to the property of FETs. Top-gated p-type CNT transistors were batch fabricated with high yield and uniform performance with small threshold voltage variation and hysteresis. Taking advantage of transistors with high yield, good uniformity, and carefully selected supply voltage, various logical and arithmetical gates, shifters, and d-latch circuits were demonstrated with rail-to-rail output. Particularly, ICs with medium scale and complicated functions such as a 4-bit adder and a 2-bit multiplier have been realized for the first time, and all of the CNT ICs are powered by a single low supply voltage of 2 V. These results show that CNT FETs technology is ready for constructing medium scale ICs.

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ASSOCIATED CONTENT

S Supporting Information *

Additional figures. The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/ acs.nanolett.6b02046. (PDF)

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AUTHOR INFORMATION

Corresponding Authors

*E-mail: (Z.Y.Z.) [email protected]. *E-mail: (L.M.P.) [email protected]. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This work was supported by the National Key Research & Development Program (Grants 2016YFA0201901 and 2016YFA0201902), the National Natural Science Foundation of China (Grants 61322105, 61321001, 61390504, and 61427901), and Beijing Municipal Science and Technology Commission (Grants D151100003315004 and Z151100003315009).

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METHODS Preparation of Carbon Nanotube Solution. Raw arcdischarged SWCNTs were purchased from Carbon Solution Inc. The dispersant 9-(1-octylonoyl)-9H-carbazole-2,7-diyl (PCz) were prepared by Suzuki polycondensation.39 PCz (200 mg) and 100 mg of SWCNTs were mixed in 100 mL of toluene. The solutions were ultrasonicated with a top-tip dispergator (Sonics VC500) for 30 min at an amplitude level of 50% and then were centrifuged at 20000g for 1 h (Allegra X22R centrifuge) to remove most of the bundles and insoluble materials. The supernatant was collected and centifugated at 50000g for 2 h. Fianally, the supernatants were collected for fabrication of TFTs. Preparation of Carbon Nanotube Thin Film. The uniform s-SWCNT films were fabricated by the dip-coating method. The as-prepared s-SWCNT solution was diluted five times with toluene in which the concentration of s-SWCNT was estimated to be 50 μg/mL by absorption spectra. The substrate was immersed in the diluted solution for 20 h. The substrate was then taken out of the solution and purged with 99.999% N2. Finally, it was baked at 120 °C for 30 min at atmosphere. Circuit Fabrication and Measurement. The channel was first defined by an electron beam lithography followed by oxygen plasma etching. The gate window was then patterned through electron beam lithography, followed by evaporating 3 nm Y film with a standard lift-off process and thermal oxidation under 240 °C in air. This process was repeated once to finally form an Y2O3 layer of about 10 nm. Source, drain, gate, and lower interconnect were patterned, followed by evaporating 40 nm Pd film and a standard lift-off process. Interlayer dielectric was formed using PMMA 200 K via electron beam lithography with dose 10 000 μC/cm2. Finally the pads and upper interconnect were patterned by electron beam lithography with 10/60 nm Ti/Au metal deposited by electron beam evaporation and a standard lift-off process. The circuits in this paper were measured using a probe station with a semiconductor analyzer (Keithley 4200). The input signal was

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REFERENCES

(1) Tulevski, G. S.; Franklin, A. D.; Frank, D.; Lobez, J. M.; Cao, Q.; Park, H.; Afzali, A.; Han, S.-J.; Hannon, J. B.; Haensch, W. ACS Nano 2014, 8, 8730−8745. (2) Peng, L.-M.; Zhang, Z.; Wang, S. Mater. Today 2014, 17, 433− 442. (3) Tans, S. J.; Verschueren, A. R. M.; Dekker, C. Nature 1998, 393, 49−52. (4) Javey, A.; Guo, J.; Wang, Q.; Lundstrom, M.; Dai, H. Nature 2003, 424, 654−657. (5) Zhang, Z.; Liang, X.; Wang, S.; Yao, K.; Hu, Y.; Zhu, Y.; Chen, Q.; Zhou, W.; Li, Y.; Yao, Y.; Zhang, J.; Peng, L.-M. Nano Lett. 2007, 7, 3603−3607. (6) Seidel, R. V.; Graham, A. P.; Kretz, J.; Rajasekharan, B.; Duesberg, G. S.; Liebau, M.; Unger, E.; Kreupl, F.; Hoenlein, W. Nano Lett. 2005, 5, 147−150. (7) Franklin, A. D.; Chen, Z. Nat. Nanotechnol. 2010, 5, 858−862. (8) Franklin, A. D.; Luisier, M.; Han, S.-J.; Tulevski, G.; Breslin, C. M.; Gignac, L.; Lundstrom, M. S.; Haensch, W. Nano Lett. 2012, 12, 758−762. (9) Wang, C.; Zhang, J.; Zhou, C. ACS Nano 2010, 4, 7123−7132. (10) Lee, S. Y.; Lee, S. W.; Kim, S. M.; Yu, W. J.; Jo, Y. W.; Lee, Y. H. ACS Nano 2011, 5, 2369−2375. (11) Wang, C.; Chien, J.-C.; Takei, K.; Takahashi, T.; Nah, J.; Niknejad, A. M.; Javey, A. Nano Lett. 2012, 12, 1527−1533. (12) Gao, P.; Zhang, Q. Nanotechnology 2014, 25, 065301. (13) Xu, W.; Liu, Z.; Zhao, J.; Xu, W.; Gu, W.; Zhang, X.; Qian, L.; Cui, Z. Nanoscale 2014, 6, 14891−14897. (14) Chen, Z.; Appenzeller, J.; Lin, Y.-M.; Sippel-Oakley, J.; Rinzler, A. G.; Tang, J.; Wind, S. J.; Solomon, P. M.; Avouris, P. Science 2006, 311, 1735−1735. (15) Noh, J.; Jung, M.; Jung, K.; Lee, G.; Lim, S.; Kim, D.; Kim, S.; Tour, J. M.; Cho, G. Org. Electron. 2011, 12, 2185−2191. (16) Sun, D.-M.; Timmermans, M. Y.; Kaskela, A.; Nasibulin, A. G.; Kishimoto, S.; Mizutani, T.; Kauppinen, E. I.; Ohno, Y. Nat. Commun. 2013, 4, 2302. (17) Chen, H.; Cao, Y.; Zhang, J.; Zhou, C. Nat. Commun. 2014, 5, 4097. H

DOI: 10.1021/acs.nanolett.6b02046 Nano Lett. XXXX, XXX, XXX−XXX

Letter

Nano Letters (18) Cao, Q.; Kim, H.-s.; Pimparkar, N.; Kulkarni, J. P.; Wang, C.; Shim, M.; Roy, K.; Alam, M. A.; Rogers, J. A. Nature 2008, 454, 495− 500. (19) Sun, D.-M.; Timmermans, M. Y.; Tian, Y.; Nasibulin, A. G.; Kauppinen, E. I.; Kishimoto, S.; Mizutani, T.; Ohno, Y. Nat. Nanotechnol. 2011, 6, 156−161. (20) Ding, L.; Zhang, Z.; Liang, S.; Pei, T.; Wang, S.; Li, Y.; Zhou, W.; Liu, J.; Peng, L.-M. Nat. Commun. 2012, 3, 677. (21) Pei, T.; Zhang, P.; Zhang, Z.; Qiu, C.; Liang, S.; Yang, Y.; Wang, S.; Peng, L.-M. Nano Lett. 2014, 14, 3102−3109. (22) Shulaker, M. M.; Hills, G.; Patil, N.; Wei, H.; Chen, H.-Y.; Wong, H. S. P.; Mitra, S. Nature 2013, 501, 526−530. (23) Kang, D.; Park, N.; Ko, J.h.; Bae, E.; Park, W. Nanotechnology 2005, 16, 1048. (24) Kim, W.; Javey, A.; Vermesh, O.; Wang, Q.; Li, Y.; Dai, H. Nano Lett. 2003, 3, 193−198. (25) Franklin, A. D.; Tulevski, G. S.; Han, S.-J.; Shahrjerdi, D.; Cao, Q.; Chen, H.-Y.; Wong, H. S. P.; Haensch, W. ACS Nano 2012, 6, 1109−1115. (26) Kang, S. J.; Kocabas, C.; Ozel, T.; Shim, M.; Pimparkar, N.; Alam, M. A.; Rotkin, S. V.; Rogers, J. A. Nat. Nanotechnol. 2007, 2, 230−236. (27) Collins, P. G.; Arnold, M. S.; Avouris, P. Science 2001, 292, 706−709. (28) Snow, E. S.; Novak, J. P.; Campbell, P. M.; Park, D. Appl. Phys. Lett. 2003, 82, 2145−2147. (29) Fuhrer, M. S.; Nygård, J.; Shih, L.; Forero, M.; Yoon, Y.-G.; Mazzoni, M. S. C.; Choi, H. J.; Ihm, J.; Louie, S. G.; Zettl, A.; McEuen, P. L. Science 2000, 288, 494−497. (30) Nirmalraj, P. N.; Lyons, P. E.; De, S.; Coleman, J. N.; Boland, J. J. Nano Lett. 2009, 9, 3890−3895. (31) Kim, D.-H.; Huang, J.; Shin, H.-K.; Roy, S.; Choi, W. Nano Lett. 2006, 6, 2821−2825. (32) Lee, E. J. H.; Balasubramanian, K.; Burghard, M.; Kern, K. Adv. Mater. 2009, 21, 2720−2724. (33) Kumar, S.; Pimparkar, N.; Murthy, J. Y.; Alam, M. A. Appl. Phys. Lett. 2006, 88, 123505. (34) Unalan, H. E.; Fanchini, G.; Kanwal, A.; Du Pasquier, A.; Chhowalla, M. Nano Lett. 2006, 6, 677−682. (35) Arnold, M. S.; Green, A. A.; Hulvat, J. F.; Stupp, S. I.; Hersam, M. C. Nat. Nanotechnol. 2006, 1, 60−65. (36) Engel, M.; Small, J. P.; Steiner, M.; Freitag, M.; Green, A. A.; Hersam, M. C.; Avouris, P. ACS Nano 2008, 2, 2445−2452. (37) Asada, Y.; Miyata, Y.; Ohno, Y.; Kitaura, R.; Sugai, T.; Mizutani, T.; Shinohara, H. Adv. Mater. 2010, 22, 2698−2701. (38) Wang, H.; Mei, J.; Liu, P.; Schmidt, K.; Jiménez-Osés, G.; Osuna, S.; Fang, L.; Tassone, C. J.; Zoombelt, A. P.; Sokolov, A. N.; Houk, K. N.; Toney, M. F.; Bao, Z. ACS Nano 2013, 7, 2659−2668. (39) Gu, J.; Han, J.; Liu, D.; Yu, X.; Kang, L.; Qiu, S.; Jin, H.; Li, H.; Li, Q.; Zhang, J. Small 2016, DOI: 10.1002/smll.201600398. (40) Leskelä, M.; Ritala, M. Thin Solid Films 2002, 409, 138−146. (41) Lu, Y.; Bangsaruntip, S.; Wang, X.; Zhang, L.; Nishi, Y.; Dai, H. J. Am. Chem. Soc. 2006, 128, 3518−3519. (42) Wang, Z.; Xu, H.; Zhang, Z.; Wang, S.; Ding, L.; Zeng, Q.; Yang, L.; Pei, T.; Liang, X.; Gao, M.; Peng, L.-M. Nano Lett. 2010, 10, 2024− 2030. (43) Chau, R.; Datta, S.; Doczy, M.; Jin, B.; Kavalieros, J.; Majumdar, A.; Metz, M.; Radosavljevic, M. IEEE Trans. Nanotechnol. 2005, 4, 153−158. (44) Geier, M. L.; McMorrow, J. J.; Xu, W.; Zhu, J.; Kim, C. H.; Marks, T. J.; Hersam, M. C. Nat. Nanotechnol. 2015, 10, 944−949. (45) Ortiz-Conde, A.; Sanchez, F. J. G.; Liou, J. J.; Cerdeira, A.; Estrada, M.; Yue, Y. Microelectron. Reliab. 2002, 42, 583−596. (46) Alam, M. Microelectron. Reliab. 2008, 48, 1114−1122. (47) Mizuno, T.; Okamura, J.-i.; Toriumi, A. IEEE Trans. Electron Devices 1994, 41, 2216−2221. (48) Bernstein, K.; Frank, D. J.; Gattiker, A. E.; Haensch, W.; Ji, B. L.; Nassif, S. R.; Nowak, E. J.; Pearson, D. J.; Rohrer, N. J. IBM J. Res. Dev. 2006, 50, 433−449.

(49) Yao, J.; Yan, H.; Das, S.; Klemic, J. F.; Ellenbogen, J. C.; Lieber, C. M. Proc. Natl. Acad. Sci. U. S. A. 2014, 111, 2431−2435.

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DOI: 10.1021/acs.nanolett.6b02046 Nano Lett. XXXX, XXX, XXX−XXX