Inorganic Complementary

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Sub-2V, Transfer-Stamped Organic/Inorganic Complementary Inverters Based on Electrolyte-Gated Transistors Kyung Gook Cho, Hyun Je Kim, Hae Min Yang, Kyoung Hwan Seol, Seung Ju Lee, and Keun Hyung Lee ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b13140 • Publication Date (Web): 02 Oct 2018 Downloaded from http://pubs.acs.org on October 2, 2018

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ACS Applied Materials & Interfaces

Sub-2V, Transfer-Stamped Organic/Inorganic Complementary Inverters Based on Electrolyte-Gated Transistors Kyung Gook Cho,† Hyun Je Kim,† Hae Min Yang, Kyoung Hwan Seol, Seung Ju Lee and Keun Hyung Lee* Department of Chemistry and Chemical Engineering Inha University Incheon 22212 Republic of Korea *E-mail: [email protected]

ACS Paragon Plus Environment

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ABSTRACT Organic/inorganic hybrid complementary inverters operating at low voltages (1 V or less) were fabricated by transfer-stamping organic p-type poly(3-hexylthiophene) (P3HT) and inorganic n-type zinc oxide (ZnO) electrolyte-gated transistors (EGTs). A semicrystalline homopolymer-based gel electrolyte, or an ionogel, was also transfer-stamped on the semiconductors for use as a high-capacitance gate insulator. For the ionogel stamping, the thermoreversible crystallization of phase-separated homopolymer crystals, which act as network cross-links, was employed to improve the contact between the gel and the semiconductor channel. The homopolymer ionogel-gated P3HT transistor exhibited a high hole mobility of 2.81 cm2/Vs, and the ionogel-gated n-type ZnO transistors also showed a high electron mobility of 2.06 cm2/Vs. The transfer-stamped hybrid complementary inverter based on the P3HT and ZnO EGTs showed a low-voltage operation with appropriate inversion characteristics including a high voltage gain of ~18. These results demonstrate that the transfer stamping strategy provides a facile and reliable processing route for fabricating electrolyte-gated transistors and logic circuits.

KEYWORDS: transfer stamping, complementary inverter, electrolyte-gated transistor, ionogel, low-voltage operation


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Introduction Over the past few years, electrolyte-gated transistors (EGTs) or electric double layer transistors (EDLTs) have gained immense attention as promising switching devices because of their lowcost solution processability, low-voltage operations, and excellent device performance.1-4 Various organic and inorganic semiconductors have been employed for fabricating EGTs.5-11 In EGTs, polymer gel electrolytes, known as ionogels, can serve as a high capacitance gate insulating layer to modulate the charge density of the semiconductor. The high capacitance of these gel electrolytes originates from the charged ions packed in the proximity of the conductor/semiconductor of interest to counterbalance the external electric field.12 When an external voltage is applied to the gate electrode of a transistor, the ions in the gel electrolyte migrate under the electric field and appropriate ions accumulate at the gate-electrode/electrolyte and electrolyte/semiconductor interfaces, which leads to the generation of an equal number of electrons or holes at the semiconductor channel.13 These layers with balanced electric charges and counter ions are referred to as electric double layers (EDLs). The EDLs for gel electrolytes are typically a few nanometers thick and exhibit very large specific capacitances (>1 µF/cm2), and hence induce huge charge carrier densities (>1014/cm2) in the semiconductor.1 Polymeric

ionogels

have

been

generated

by

chemically

polymerizing

monomers/macromonomers in ionic liquids14-17 or physically generating temporary cross-links by lyophobic phase separation, hydrogen bonding, and crystallization.18-23 Recently, Lee and coworkers reported that a semicrystalline homopolymer can generate rubbery ionogels by interconnecting phase-separated homopolymer crystals in an ionic liquid.24 This crystallizationinduced physical ionogel can melt at temperatures higher than the melting temperature of the network crystals.24 This phenomenon is advantageous in gel processing because reversible


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crystallization enables the gels to be processed in a melt-state and re-gelled for solid-state use of the material. In addition, ionogels possess high ionic conductivities and wide electrochemical stability windows. Therefore, they are promising solid-state electrolyte materials for a wide variety of electrochemical devices such as thin-film transistors, supercapacitors, and sensors.511,25-33

The most promising advantage of the EGTs is that they can be fabricated by low-cost large-area

solution

processes,

thus

avoiding

multistep

vacuum

processes

such

as

photolithography. Various processing techniques including aerosol-jet printing,34 ink-jet printing,35 and electrohydrodynamic-jet printing36 have been successfully applied to fabricate the high performance EGTs. However, in order to widen the range of practical applications of the EGTs, it is imperative to develop alternative solution processes for their fabrication. Transfer stamping is an attractive candidate because it enables a wide range of target inks to be deposited at high yield and accuracy on virtually any types of substrates including flexible, transparent, and soft materials.37,38 To further realize advanced logic circuitry for low-cost, large-area printed electronics, it is desirable to directly transfer all the active components of the circuit elements including hole transporting (p-type) and electron conducting (n-type) semiconductors, a gate dielectric, and a conducting electrode. However, realization of unit transistors and complementary circuits fabricated by transfer printing all the active layers of the logic circuitry has not been demonstrated before; even if expanded to all printed complementary electronics, the relevant reports are still sparse to date. In this present study, we prepared low voltage p-and n-type transistors and complementary circuitry by directly transfer printing hole and electron transporting semiconductors, a high capacitance ionogel dielectric, and a conducting electrode. The ionogel


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used in this study consisted of 5 wt% semicrystalline homopolymer poly(vinylidene fluoride) (PVDF)

in

95

wt%

room-temperature

ionic

liquid

1-ethyl-3-methylimidazolium

bis(trifluoromethyl sulfonyl)imide ([EMI][TFSI]). The solid ionogel obtained by blending very few host polymers (ca. 5 wt%) exhibited very high ionic conductivity and specific capacitance. In the transfer printing of an ionogel dielectric, reversible crystallization of homopolymer network provides much higher transferring efficiency than the lyophobic phase-separation-based block copolymer network because delicate block length engineering and comprehensive synthesis are not required in the homopolymer-based ionogels. In addition, reversible crystallization of the homopolymer crystals suggests that the type of homopolymer host is not limited in the transfer printing, and that other semicrystalline homopolymer-based ionogels are suitable for the transfer-printed complementary logic devices. Using this ionically conductive electron insulator as a high-capacitance gate dielectric, organic/inorganic EGTs were fabricated by transfer stamping all the active layers: p-type P3HT and n-type ZnO semiconductor, an ionogel gate dielectric, and a gate electrode. The EGTs turned on completely at small applied voltages and showed high carrier motilities (higher than 1 cm2/Vs). By combining these transferstamped and ionogel-gated p- and n-type EGTs in series, organic/inorganic complementary inverters operating at low voltages with reasonably high voltage gain were successfully realized. These results suggest that the transfer stamping provides an attractive and facile option to deposit functional layers including p- and n-type semiconductors, a gate dielectric, and a conducting electrode for the realization of high performance electrochemical transistors and their logic circuitry.


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Experimental Methods Materials: PVDF homopolymer with an average molecular weight (Mw) of 530,000 g/mol, acetone, and chloroform were purchased from Sigma-Aldrich. [EMI][TFSI] (electronic grade) was purchased from Merck. Regioregular P3HT (Rieke Metals, 4002-EE) and poly(3,4ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS) (Heraeus, Clevios PH 1000) were used to form the organic p-type semiconductor and gate electrode, respectively. ZnO (99.99%, Sigma Aldrich) and ammonium hydroxide (Alfa Aesar, 25% NH3) were used to generate an inorganic n-type semiconductor. Ionogel preparation and characterization: PVDF was dissolved in acetone at a hotplate temperature of 70 °C. After obtaining a homogeneous PVDF/acetone solution, [EMI][TFSI] was added to it. The PVDF concentration in the ionogel was maintained at 5% by weight. The low fraction of the host polymer rendered the gel a solid-like mechanical strength while maintaining its electrical properties, especially the ionic conductivity and specific capacitance, at values close to those of the neat ionic liquid. The average thickness of the ionogel was ∼10 µm. Differential scanning calorimetry (DSC) data were collected during the 2nd heating and cooling scans using a JADE calorimeter (Perkin Elmer) at a scan rate of 10 °C/min. Electrical impedance measurements were performed by an AUTOLAB spectrometer (Echem-Technology). Transistor fabrication and characterization: The source and drain electrodes were generated by thermally evaporating 5-nm thick Cr and 45-nm thick Au using a patterned stainless steel stencil mask. The channel width and length of the source and drain contacts were 1000 and 100 µm, respectively. The patterned substrates were sequentially sonicated in acetone, isopropyl alcohol, and methyl alcohol for 5 min, washed with methyl alcohol, and then dried with compressed nitrogen prior to the stamping of the active layers. To fabricate p-type EGTs, P3HT (3 mg/mL in


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chloroform) was first spin-coated on an elastomeric polydimethylsiloxane (PDMS) stamp at 2000 rpm for 60 s. The inked stamp was manually cut with a razor blade and placed on a source/drain channel and then heated at 80 °C for 60 s to improve the conformal contact between P3HT and the acceptor substrate. P3HT was transferred on a transistor channel by slowly detaching the PDMS stamp from the substrate. The average thickness of the P3HT was ~40 nm. Transfer stamping of the thermoreversible ionogel and PEDOT:PSS were carried out by following almost the same procedure as that for the P3HT semiconductor. The homopolymer ionogel was directly spin-coated on an UV/O3-treated PDMS stamp from the acetone solution at 1000 rpm for 60 s, placed on top of P3HT, heated at 110 °C for 15 s, and then cooled at room temperature for 15 s. The ionogel was transferred on P3HT by slowly detaching PDMS. For the gate electrode, a PEDOT:PSS aqueous solution was inked on an UV/O3-treated PDMS stamp by drop casting and was then transferred on top of the ionogel. For the n-type ZnO transistor, the ZnO precursor (0.14 mmol ZnO in 1 mL ammonium hydroxide) was first spin-coated on an UV/O3-treated PDMS stamp at 1500 rpm for 60 s, placed on the source/drain electrode, manually pressurized and heated at 100 °C for 30 s, and then transferred by detaching the PDMS stamp. The transferred ZnO was then thermally annealed at 350 °C for 1 h. The average thickness of the ZnO was ~45 nm. The ionogel gate dielectric and the PEDOT:PSS gate electrode were sequentially prepared by the same methods described previously. The P3HT/ZnO complementary inverters were fabricated by connecting each EGT in series. The atomic force microscopy (AFM) images of P3HT and ZnO semiconductors were collected using a NanoFocus n-Tracer AFM. Device measurements were performed using a probe station (MSTECH, MST 5500B) connected to a Keithley 4200-SCS semiconductor parameter analyzer. All the electronic measurements were carried out at a voltage sweep rate of 17 mV/s under ambient conditions.


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Results and Discussion Figure 1 shows the schematic for the fabrication of transfer-stamped ionogel-gated EGTs on a target substrate. First, the source and drain electrodes were prepared by thermally depositing 5 nm Cr and 45 nm Au on a substrate using a patterned stencil mask. Top-gated bottom-contact EGTs were produced by sequentially stacking the semiconductor, the ionogel gate dielectric, and the PEDOT:PSS gate electrode on the source/drain electrodes using PDMS donor stamps. Solution casting methods (spin coating or drop casting) were used to deposit the functional inks on PDMS stamps: P3HT, ZnO, and the ionogel were spin-coated and PEDOT:PSS was drop-cast on PDMSs. The inked stamps were manually cut to the desired size using a razor blade and then placed on the surface of the receiving substrates. The assemblies were heated at elevated temperatures to provide conformal contact between the ink and the receiving substrate. Transfer of the functional layer occurred when the stamp was manually removed from the substrate. The three-dimensional chemical structures of the ionogel components and the schematic of the gel formation are shown in Figure 2a.The DSC results shown in Figures 2b and S1 (Supporting Information) support the presence and thermoreversible characteristics of the polymer crystals that served as network cross-links in the homopolymer-based physical ionogel.24 The gel exhibited definite endothermic peaks at about −10 and 110 °C attributing to the liquid structure of [EMI][TFSI] and the melting transition of the PVDF crystals, respectively.24 The PVDF melting temperature in the ionogel decreased significantly and the peak intensity was lower than that for pristine PVDF, indicating a decrease in the amount of the crystals and their size. The enthalpy of fusion of the gel (∆Hf, gel) obtained from the area under the PVDF melting peak was 1.47 J/g. The crystallinity of the gel (% crystallinity) was calculated by equation 1:


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%Crystallinity = ∆Hf, gel / ∆Hf, 100% crystal ×100

(1)

where ∆Hf, 100% crystal denotes the heat of fusion of 100% crystalline PVDF and had a value of 104.7 J/g.39 The crystallinity of the gel calculated from the enthalpy of PVDF melting was ~1.4%. For successful stamping, the gel was heated to 110 °C, the peak temperature of PVDF melting transition, to partially liquefy the gel, and thus improve the wetting of the gel to the acceptor surfaces. By incorporating a small amount of network polymers (ca. 5 wt%), gels with electrical properties (ionic conductivity and specific capacitance) similar to those of pure ionic liquids can be obtained while getting mechanical strength.40 The specific capacitance (C’) of the thermoreversible homopolymer ionogel was measured by impedance spectroscopy using sandwich-type SUS/ionogel/SUS capacitors as a function of the excitation frequency, and the results are shown in Figure 2c. C’ at the gel/electrode interface was extracted from the imaginary impedance (Z”) as follows: C’ = −1/πƒZ”A, where f is the excitation frequency and A is the gel area in contact with the SUS electrodes. The representative Nyquist and phase angle versus frequency plots are shown in Figure S2 (Supporting Information). The average capacitance of the gel at the electrode interface was as large as 31 µF/cm2 at 1 Hz and maintained its value at above 2 µF/cm2 at a high frequency of 105 Hz, which is slightly larger than or comparable to that observed for other polymeric ionogels based on block copolymers and random copolymers.6,13 As explained previously, the huge capacitance values of the ionogel can be attributed to the formation of nanometer-thick electric double layers at the gel/electrode interfaces. The capacitance value decreases as the external frequency increases because of the interactions between the ions in gel electrolytes and electric charges in solid electrodes.41-43 This phenomenon suggests that the ions in gel electrolytes cannot respond readily to an external


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stimulus at high frequencies, leading to less effective formation of electric double layers, i.e. low specific capacitance. High capacitance values (higher than 1 µF/cm2) imply that the ionogel is an appropriate dielectric for charge carrier modulation in thin-film transistors because the gel allows a high carrier density Q’ in a semiconductor channel at a given gate voltage (Q’ = C’×(VG−Vth), where VG is the gate voltage and Vth is the threshold voltage). The room-temperature ionic conductivity for the ionogel, calculated from the real part of the impedance at a high frequency plateau, was 9.1± 0.5 mS/cm, the highest noted for polymer gel electrolytes, which makes the gel a promising solid-state electrolyte for electrochemical devices where fast ion transport is important. Note that the ionic conductivity of pure [EMI][TFSI] is 9.8 mS/cm at 27 °C.44,45 The high conductivity of the ionogel can be attributed to the low concentration (5 wt%) and glass transition temperature (Tg, PVDF = −32 °C) of the network polymer.46 Figure 3 shows the p- and n-type EGT characteristics of the transfer-stamped P3HT and ZnO transistors. The EGTs were fabricated by sequentially transferring the semiconductor, the ionogel gate dielectric, and the PEDOT:PSS gate electrode using PDMS stamps, as explained previously. Figure 3a shows the output (ID−VD) characteristics of the transfer-stamped p-type P3HT EGTs at different VGs, where ID is the channel current and VD is the voltage applied between the source and drain electrodes. A very high saturation current of ~0.7 mA was obtained at very small voltages of VD = VG = −0.5 V owing to the large capacitance of the ionogel gate dielectric. It should be noted that when using a traditional SiO2 gate dielectric, P3HT transistors typically exhibit lower output currents (~10 µA) even at a very high operating voltage of 100 V.47 The increase in the ID values with the increasing gate voltages in the output curves implies that the transfer-stamped ionogel functioned well as a capacitor to accumulate appropriate charge carriers in the P3HT film (hole carriers in this case). More specifically, upon application of the


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negative gate bias in the PEDOT:PSS gate electrode, the cations in the ionogel approached the gate electrode and effectively screened the electrode potential, leading to the accumulation of anions at the semiconductor side and the subsequent formation of a large number of hole carriers (or high transistor channel current) in the P3HT transistor.48 Figure 3b shows the transfer (ID−VG) curve for the P3HT EGTs acquired in the linear regime (VD = −0.1 V). From the transfer curve, it is evident that the EGTs operated at low voltages (lower than 1 V) with a reasonable on-to-off current ratio of ~105. Note that homopolymer ionogels with other polymer concentrations can also be transferred and the transferred ionogel-gated P3HT EGTs exhibit similar device performance (Supporting Information Figure S3). The low-voltage operation of the transistor can be attributed to the large specific capacitance of the ionogel. In addition, the transfer curve measured at the higher drain voltage of VD = −0.5 V (i.e. the saturation regime), shown in Figure 3c, shows the expected linear correlation between ID1/2 and VD. Figure 3d shows the ID−VD curves of the transfer-stamped n-type ZnO EGTs at different VGs. The output curves confirm that the ZnO EGTs also exhibited high saturation currents (higher than 0.1 mA) at small applied voltages (less than 2 V). This can be attributed to the large capacitance of the ionogel electrolyte dielectric. The output curves also confirm that the transferstamped ionogel worked well as a capacitor to induce electrons in the n-type ZnO semiconductor. In n-type EGTs, the application of a positive gate bias in the PEDOT:PSS gate electrode causes the accumulation of anions at the gate electrode/ionogel interface, which results in the accumulation of cations at the ZnO surface and the subsequent generation of a large number of electrons (or high device current) in ZnO EGTs. Figure 3e shows the ID−VG curve obtained for the ZnO EGTs in the linear regime of VD = 0.1 V. The ID−VG curve shows that the n-type EGT


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turned on and off at low voltages (lower than 2 V) with a reasonable on-to-off current ratio (larger than 104). This low-voltage n-type EGT operation can be attributed to the large capacitance of the ionogel. In addition, the transfer curve measured at the saturation regime of VD = 0.5 V showed linear correlation between ID1/2 and VD (Figure 3f). The device characteristics including the mobility, on-to-off current ratio, and Vth values of the transfer-stamped EGTs were investigated and the results are shown in Figure 4. For comparison, we also fabricated P3HT and ZnO EGTs by using the conventional spin-coating technique. To determine the carrier mobility of the semiconductor films, their induced carrier densities (p) were determined by using the following equation:

p=

∫I

G

dV G

(2)

e rV A

where IG is the gate current, e is the unit charge, rV is the VG sweeping rate, and A is the area of the gate electrode.49 Large carrier density values of 8.02 × 1014 and 1.39 × 1014 /cm2 were obtained for the P3HT and ZnO semiconductors, respectively. Using these carrier densities, the carrier mobility (µ) of each semiconductor was calculated in the linear region as follows:

µ=

L ID W epVD

(3)

The average charge mobility values for the P3HT and ZnO semiconductors were 2.14 and 1.82 cm2/Vs, respectively (Figure 4a). These mobility values are slightly than or comparable to those obtained for the same semiconductors generated by the spin-coating method. The hole and electron motilities for the spin-coated P3HT and ZnO were 2.12 and 1.74 cm2/Vs, respectively. The carrier mobility values for the P3HT and ZnO EGTs in the saturation regime were 2.81 ± 0.41 and 2.06 ± 0.18 cm2/Vs, respectively. The on/off current ratio and Vth values were also


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similar for both the cases (Figures 4b–4c). AFM images were collected from the spin-coated and transfer-stamped semiconductors (Figures 4d–4g). Although the transfer-stamped P3HT and ZnO semiconductors were smoother that the spin-cast samples, the transistor characteristics were found to be invariant to the surface morphology and both the devices showed almost similar performance. The rms roughness values of the transfer-stamped P3HT and ZnO films were 2.44 nm and 2.85 nm, respectively, and those of the spin-coated P3HT and ZnO were 6.96 nm and 8.18 nm, respectively. It is noteworthy that calculation of carrier mobility of organic semiconductors in electrolyte gating experiments is very difficult due to the ion penetration into the ion permeable semiconductors, which leads 3D conduction channel.1 Therefore, using the 2D carrier density to calculate the carrier mobility of 3D conductive channel can only provide rough estimation of the mobility. In the actual operation of logic circuits, although the primary figure of merit is not the carrier mobility but the current level that each EGT can produce, accurate calculation of carrier mobility should be done much rigorously. We believe that precise calculation of carrier mobility in EGTs will become more important and systematic researches should be carried out, as it is an important issue in organic field effect transistors (OFETs). Reproducibility and reliability of the transfer stamping technique were also confirmed by the statistical studies on the transfer curve, on/off current ratio, carrier mobility, and turn-on voltage (Von) of the P3HT EGTs (Figure S4). Von is the characteristic voltage at which ID of the forward sweep passes through the off current of the reverse sweep. The ID-VG curves and other characteristics obtained from 30 transistors behaved similarly. These results confirm the versatility and applicability of the transfer stamping technique to fabricate high-performance EGTs that operate at low voltages.


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We fabricated low-voltage organic/inorganic hybrid complementary inverters using the transfer stamping technique by connecting the p-type P3HT and n-type ZnO EGTs in series. The inverter characteristics are shown in Figure 5. The circuit diagram of the hybrid inverter is shown in the inset of Figure 5a. The hybrid inverter exhibited appropriate voltage transfer performance at three different supply voltages (VDDs) of 0.5, 0.75, and 1 V (Figure 5a). When the input voltage (Vin) was small (logic “0”) the circuit output voltage (Vout) was close to VDD (logic “1”), whereas at high Vin (logic “1”), Vout approached 0 V (logic “0”), indicating the proper logic inversion. In particular, when VDD was set to 1 V, a high gain value (∂Vout/∂Vin) as large as ~18 was obtained (Figure 5b). This value is substantially larger than those reported for electrolytegated complementary inverters operating at low supply voltages (VDD < 2 V).50-52 Therefore, these results confirm that transfer-stamped EGTs gated with solid polymer electrolyte ionogels can serve as basic units in electronic circuits including logic gates and amplifiers. Figure S5 (Supporting Information) shows the operational stabilities of the transferstamped ionogel-gated P3HT EGTs under repetitive mechanical bending, bias, and time stresses, separately. All the measurements were conducted under ambient conditions. For the bending tests, flexible EGTs fabricated on poly(ethylene terephthalate) (PET) substrates were exposed to 5000 repeated bends at a bending radius of r = 1 mm, corresponding to 5% tensile strain (ε = t/2r, where t is the PET thickness of 100 µm).53 Figures S5a and S5b show the ID−VG transfer curves for the bending experiments and the resulting changes in the on-current ID (ID,

ON)

and Vth

extracted from the ID−VG curves, respectively. The ID−VG curves were obtained in the linear regime of VD = −0.1 V. The ID−VG curves were nearly identical and the decrease in the ID, ON value under mechanical stress was less than 3%. The shift in Vth (∆Vth) was negligible (∆Vth was only 0.006 V). For the bias stress test, transient ID and IG data were recorded over a period of


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3600 s at the continuous bias of VD = VG = −0.5 V (Figure S5c). The on-current ID from the transistors increased and saturated to ~0.85 mA, which is consistent with the ID levels shown in Figure 4.54 The change in IG shown in the inset of Figure S5c indicates the capacitive charging of EGTs. For the time stress tests, the transfer curves shown in Figure S5d exhibit excellent time stability for the transfer-stamped ionogel-gated EGTs.55 The decrease in ID, ON over a period of 20 days was 30% and ∆Vth was 0.037 V (Figure S5e). The reduction in ID, ON and negative shift in Vth was probably because of the absorption of H2O and O2 molecules by the P3HT semiconductor, which generates hole puddles in the semiconductor channel. The device hysteresis extracted from the difference between Vth in the forward and reverse sweeps of the transfer curves in Figure S5d increased slightly by 0.055 V (Figure S5f).

Conclusions We successfully prepared ionogel-gated p- and n-type EGTs and complementary inverters operating at low voltages by soft-lithographic transfer stamping. Both the EGTs turned on and off at small applied voltages of 104. The average carrier mobility values of the P3HT and ZnO EGTs were 2.81 and 2.06 cm2/Vs, respectively in the saturation regime. The device performance statistics (transfer curve, carrier mobility, turn on voltage, and on/off ratio) clearly demonstrated the excellent reliability of the stamping method for the realization of advanced electronic circuits. Finally, organic/inorganic hybrid complementary inverters with a very high voltage gain of ~18 were successfully realized by using transfer-stamped P3HT and ZnO EGTs as the p- and n-type transistors, respectively. Overall, the results showed that the transfer stamping strategy provides a facile and versatile route to fabricate high performance ionogel-gated transistors and


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complementary logic circuitry. We believe that the electrochemical transistors and the logic circuits demonstrated in this work can be applied directly for the development of emerging applications such as biosensors, artificial synapses, and photodetectors.


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FIGURES

Figure 1. Schematic of the fabrication of a transfer-stamped transistor array. Source and drain electrodes were thermally evaporated on a target substrate using a stainless steel shadow mask. P3HT or ZnO semiconductor was deposited on PDMS by spin casting and then transferred on source/drain channels. Ionogel and PEDOT:PSS were sequentially stamped on the semiconductor to fabricate top-gated transistors. Ionogel was inked on PDMS by spin casting, whereas drop casting was used to prepare the PEDOT:PSS layer on PDMS.


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Figure 2. (a) Three-dimensional chemical structures of the PVDF host polymer and the [EMI][TFSI] ionic liquid (left) and schematic of the crystallization-induced formation of the homopolymer ionogel (right). (b) DSC curves for the homopolymer ionogel and the PVDF host polymer. Curves have been vertically shifted for clarity. (c) Specific capacitance versus frequency plot obtained for the metal/homopolymer-ionogel/metal capacitors. Weight ratio between the PVDF polymer and [EMI][TFSI] was maintained at 1:19.


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Figure 3. (a) ID−VD output curves obtained at six different VGs, (b) the ID−VG transfer curve obtained in the linear regime of VD = −0.1 V (Inset shows the cross-sectional schematic of the transfer-stamped ionogel-gated EGT), and (c) ID0.5 versus VG curve obtained at the saturation regime of VD = −0.5 V for the p-type organic P3HT EGTs. (d) The ID−VD curves, (e) the ID−VG curve measured at VD = 0.1 V, and (f) the ID0.5 versus VG curve obtained at VD = 0.5 V for the ntype inorganic ZnO EGTs.


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Figure 4. (a) Hole and electron mobility, (b) on/off current ratio, and (c) Vth values for the P3HT and ZnO EGTs generated by transfer stamping and spin-coating. AFM images for the (d) spincoated and (e) transfer-stamped P3HTs. AFM images for the (f) spin-coated and (g) transferstamped ZnOs.


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Figure 5. (a) Vin versus Vout characteristics of the transfer-stamped organic/inorganic complementary inverter based on the p-type P3HT and n-type ZnO EGTs at three different supply voltages (inset shows the equivalent circuit diagram of the complementary inverter) and (b) the corresponding voltage gain curves. The maximum gain value of ~18 was obtained at the supply voltage of 1 V.


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ASSOCIATED CONTENT Supporting Information. DSC cooling curves for the PVDF host polymer and the homopolymer ionogel. Nyquist and phase angle versus frequency plots obtained from impedance spectroscopy. Statistical results for the P3HT EGTs. Operational stability results for the P3HT EGTs. The Supporting Information is available free of charge on the ACS Publication website at DOI:

AUTHOR INFORMATION Corresponding Author *E-mail: [email protected] Author Contribution †

These authors contributed equally to this work.

Notes The authors declare no competing financial interest.

ACKNOWLEDGMENT This work was supported by a research grant from INHA UNIVERSITY (INHA-54739).


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TOC


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Inorganic Complementary

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