Interface Electrode Morphology Effect on Carrier Concentration and

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Interface electrode morphology effect on carrier concentration and trap defect density in an organic photovoltaic device Arul Varman Kesavan, Arun Dhumal Rao, and Praveen Chandrashekarapura Ramamurthy ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b03953 • Publication Date (Web): 27 Jul 2017 Downloaded from http://pubs.acs.org on July 28, 2017

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ACS Applied Materials & Interfaces

Interface

electrode

morphology effect on carrier

concentration and trap defect density in an organic photovoltaic device Arul Varman Kesavan, Arun D Rao and Praveen C Ramamurthy Department of Materials Engineering, Indian Institute of Science, Bangalore-560012 E-mail: [email protected]

ABSTRACT:

Formation of Schottky barrier contact (SBC) leads reconstruction of charges at the

metal/semiconductor (MS) interface because of the wave function overlap between semiconductor and metal contact.

The Schottky barrier contact formation is not only a signature of material's work

function but it also sensitive to the interface trap states, the crystal orientation of the interacting materials and other interface properties.

In this work, the effect of aluminum cathode morphology

on the polymer Schottky diode and bulk heterojunction (BHJ) photovoltaic device performance is studied.

The electron collecting contacts in Schottky

diode and bulk-hetero junction photovoltaic

(BHJ) device have been deposited using aluminium in pellet and nanoparticle form.

Devices

fabricated by using Al nanoparticle showed improvement in dark as well as photocurrent density. Significant enhancement in JSC leads to overall improved power conversion efficiency (PCE). Enhanced performance in Schottky structured diode and OPV device have been correlated with electrode microstructure and its interface properties like improved electrically active contact and enhanced charge transport.

Electrical conductivity is discussed based on enhanced electrical

coherence across organic semiconductor and electrode interface. Therefore, the contribution of electrical enhancement leads to improvement in short-circuit current density (JSC) in BHJ solar cell

ACS Paragon Plus Environment


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which is due to reduced trap density. Further, PCE was correlated with the density of interface trap states studied by drive level capacitance profiling technique (DLCP).

KEYWORDS Organic solar cell, bulk hetero-junction solar cells, impedance spectroscopy, capacitance, nanoparticles, traps states.

1. Introduction Bulk heterojunction (BHJ) solar cell research finds wide interest over the past decade due to possible low fabrication cost and easy fabrication steps 1 . device performance of the BHJ solar cell.

Various methods were adopted to improve the

The BHJ consists of two electrodes active layer

sandwiched in between two electrodes, an electrode with high work function (WF) acts as an ohmic contact and low work function electrode serves as Schottky contact 2 . In this configuration of the photovoltaic cell, at least one of the electrodes should be transparent such that it provides the path to the photons to reach the photoactive layer to generate exciton (electron-hole pair).

Since the

dielectric constant of the organic semiconductor is low (2-5). These excitons generated tend to recombine unless there is a driving force for them to separate. In this case, driving force can be provided by built-in potential offset created by choosing appropriate metal contacts.3,4 . Practically, it is impossible to collect all photo-generated charge carriers by the bulk heterojunction at the electrode. Because the generated charge carriers can undergo various types of loss mechanism all the way to charge collecting electrode 5 .

The charge carrier in BHJ solar cell is governed by

recombination and various trap states. These types of loss mechanisms lead to the deviation of ideal charge transport in the device 1 . Here, the trap states can either be shallow or deep traps, which can


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occur at the bulk of the active layer or any of the device interfaces (donor/acceptor, electrode/BHJ layer). The various structural defects can induce active layer trap states. Whereas, interface defect states could be structural inhomogeneity at the interfaces and the defect states induced during the device fabrication. The efficient charge collection can be carried out by various means on the actual device. To avoid the carrier losses and effective exciton separation at the interfaces, various types of interface modification can be employed.

Interface modification includes introducing hole transport

layer (HTL)/electron blocking (EBL) at anode/active layer interface, electron transport layer (ETL)/hole blocking layer (HBL) at cathode/active layer interface, UV-ozone, plasma treatment, solvent treatment and solvent vapour annealing.

By introducing these interlayer energy level of

Active layer and electrode work function can be tuned. Improvement in the interface morphology will improve charge carrier injection/extraction and usually provide the interface trap free path for the charge carriers and reduces recombination rate at the interface 6 .

The interfacial energetic level

alignment followed by charge transport from BHJ to the respective electrode is a crucial step in device performance. The charge transport across organic semiconductors to the metal electrode is a critical step because this can create defective interfaces.

In this work, the effect of Al cathode

microstructure on the photovoltaic performance is investigated.

Aluminium cathode was deposited

from Al pellet and Al nanoparticle form and the effect of P3HT:PC 61 BM/Al interface was investigated through electrical properties such as capacitance-voltage, drive level capacitance profile (DLCP) and optical properties of the device. The notation used in this article is as follows, Al-LG and AL-SG respectively electrode deposited from Al pellet and Al nanoparticles. Devices are named as follows, Device-A:ITO/P3HT/Al-LG, Device-B: ITO//P3HT/Al-SG, Device-C:ITO/PEDOT:PSS/ P3HT:PC61 BM/Al-LG and Device-D:ITO/PEDOT:PSS/P3HT:PC 61 BM/Al-SG. 2. Experimental section



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2.1 Materials: Aluminium pellet (purity 99.999%) and Al nano-particle were purchased from AlfaAesar.

Regioregular poly(3-hexylthiophane-2,5-diyl) (rr-P3HT, Rieke metals).

Indium tin oxide

(ITO) coated glass substrates with 1ʹʹ 1ʹʹ (RS=100Ω sq-1 ) purchased from Delta Technologies Limited, USA. PEDOT:PSS (CLEVIOSTM P VP Al4083) was purchased from Heraeus Precious Metals GmbH & Co, Germany. 2.2 Device fabrication: Indium tin oxide (ITO) coated glass substrates were ultra sonicated (for 15 min each) in a soap solution, DI water, acetone, isopropanol then dried using nitrogen gas.

The

cleaned ITO substrates were UV-ozone treated at 35C for 20 min. The solution was prepared by dissolving 10 mg/ml of P3HT in chlorobenzene and stirred for overnight and then obtained solution was filtered through 0.2 µm syringe filter before use.

The cleaned ITO substrates were UV-ozone

treated at 35C for 20 min, then PEDOT: PSS layer was spin coated at 3000 rpm for 60sec and then annealed at 120C for 10 min. The coated substrates were transferred to the nitrogen filled glove box to deposit active layer and Al cathode. P3HT:PC 61 BM solution was spin coated on PEDOT:PSS layer and then annealed for 10 min at 140C. Al cathode in different forms was deposited by thermal evaporation under the chamber pressure of ~10 -6 mbar. For Schottky, the structured device was also fabricated using the same procedure, but only P3HT was used as an active semiconducting layer without PC61 BM and PEDOT: PSS. 2.3 Instrumentation: Nanosurf easyscan2 atomic force microscope (AFM) was used to study P3HT:PC60 BM/Al interface topography properties of the device interface. carried out using Rigaku smartlab X-ray diffractometer.

X-ray diffraction was

Electrical characterization such as current-

voltage (I-V, Current is measured on biasing voltage from -1 to 1V, with a step size of 0.01V), For diode parameter calculations following equation are used


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Equation 1 {

}

Where J diode current, Jo is saturation current density, ‘q’ is elemental charge, ‘V’ is applied voltage, ‘n’ diode ideality factor, kB is Boltzmann constant, T is experimental temperature (300K). 7 Equation 2 (

Where

)

is barrier height, J0 saturation current density, A is Richardson constant, q is elementary

charge, A is Richardson constant, kB is Boltzmann constant, T is experimental temperature (300K). Equation 1 and Equation 2 are further discussed in section 4. capacitance–voltage (CV, Capacitance measurement was carried out at 10kHz, with scan from -3 to 3V at an interval of 0.01V.Built in potential and carrier concentration is calculated using MottSchottky equation. 8 ), capacitance-frequency (C-f, measurement was carried out at 10mV RMS, 0V DC bias.) and drive level capacitance profiling (DLCP) measurements were carried out using Keithley 4200SCS.

The distribution of localized states is dictated by the characteristic time, trap

state attempt-to-escape frequency.

The energetic distribution of trap charges can be obtained from

the frequency dependent capacitance.

The tDOS can be calculated at the given energetic position

using the following equation. Equation 3

Here, Vbi is built-in-voltage, W is space charge region width, ω=2πf is angular frequency; k is Boltzmann constant, T temperature at which experiment is carried out. The product kT will give the total thermal energy of the states.

The distribution of the trap states was computed from C(f)



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characteristics.

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Computed trap state density is correlated with the device efficiency, as the device

efficiency is dictated by the short circuit current (JSC), open circuit voltage (VOC), fill factor (FF). Recombination rate will be high as the concentration of the trap states is high. The reduction in JSC of device-C suggests that higher trap states accelerate the rate of recombination thereby reducing the device efficiency. The energetic distribution of density of states in the BHJ layer follows the Gaussian distribution, Equation 4 √

[

]

Here, N t is total density in cm-3 , Et is middle point of energy distribution, E is the energetic position of the actual trap states in the valance band tail states and  is the width of the trap distribution or disorder induced parameter.

The parameter midpoint of energy distribution (Et ) is independent of

temperature, only the concentration of trap states on the centre point will change with temperature. The width of the trap distribution and energetic position of the trap states were calculated in both dark and light condition. The recombination lifetime can be calculated using the following relation

26

,

Equation 5

Here, e is lifetime;

is peak frequency value from Bode plot.

Newport Oriel Sol3A Class AAA solar simulator was used to characterize the solar cell. Solar cells were tested under 1 sun condition (AM1.5 and 1000 Wm-2 ). Enli-Tech QE measurement system has been used to study the photon to electron conversion percentage in the device.

The impedance

spectroscopy (IS) analysis was carried out using CH-660D electrochemical workstation.

Device

fabrication was carried out inside Jacomex glove box and Angstrom inert atmosphere thermal evaporator was used to deposit electrode.


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3. Results and discussion 3.1. Structural and thermal characterization: Figure 1(a) shows the X-ray diffraction pattern of the Al wire and Al nanoparticle. The observed dominant peak of the bulk sample and nanoparticle sample respectively is (200) and (111) respectively.

It is notices that in the bulk form (200) plane

grain orientation dominates whereas in the case of nanoparticle (111) planes dominates.

(311)

electrode(220)

(311)

(220)

(311)

(111) (200)Al-LG (200)

Al nanoparticle (111) (200)

40

50

60

Al{B}-656C

(311)

(220)

Al pellet

Al{N}-637C

Heat flow (mW/mg)

(220)

Al-SG electrode

(111)

(b)

(a)

(111) (200)

Intensity (a.u)

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70

2 theta (degree)

80

630

640

650

660

670

680

690

Temperature (°C)

Figure 1. (a) X-ray diffraction patterns of Al pellet, Al nanoparticle and Al-LG, Al-SG electrode, (b) DTA thermogram of Al pellet and nanoparticles. To understand thermal properties of electrode starting material differential thermal analysis (DTA) was carried out. The DTA thermogram of Al{B} and Al{N} are shown in Figure 1(b). The sample furnace was maintained inert atmosphere using continuous purging of nitrogen gas at the rate of 20µL min-1 . The samples were investigated from 30C to 750C at the heating rate of 10C. The calculated onset of melting for Al{B} and Al{N} is 656ºC and 637ºC respectively. The observed difference in melting temperature is ~20°C which is due to high surface area to volume ratio of Al{N}.

The

melting point depression of nanoparticle is assumed to be a reduction in the heat of fusion due to the high surface area.

8

The reduction in melting temperature of Al{N} suggests that the Al nano-particle

can be evaporated at a lower temperature compared to Al{B} samples.



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3.2 Morphology study: The evaluation of microstructure of electrode during the evaporation of Al pellet and Al nano-particles were studied.

The Al electrode was deposited at various evaporation

rates to attain final thickness of 100nm and their electrode morphology was studied by AFM. The surface morphology of electrode evaporated from Al{B} at the rate of 10 Ås-1 , 5 Ås-1 and 1 Ås-1 is shown in Figure 2 (a1), (b1) and (c1) respectively. Similarly the electrode morphology obtained from Al{N} at the evaporation rate of 10 Ås-1 , 5 Ås-1 and 1 Ås-1 is shown in Figure 2 (d1), (e1) and (f1) respectively. It is observed that as the evaporation rate increases from 1 Ås -1 to 10 Ås-1 the grain size decreases irrespective of the evaporation source materials. However, it is observed that Al electrode deposited from Al pellet showed larger particles size compared with Al nanoparticle evaporated electrode.

The same trend was observed for all the evaporation rates. The line roughness profile is

shown in Figure 2 a2, b2 and c2 with respect to the evaporation rate of 10 Ås-1 , 5 Ås-1 and 1 Ås-1 for Al{B} source materials and Figure 2 e2, e2 and f2 with respect to the evaporation rate of 10 Ås -1 , 5 Ås-1 and 1 Ås-1 for Al{N} source materials. The roughness calculated from AFM measurement is given in the Table 1. From the obtained SEM microstructure the grain size was calculated by a linear interpolation method. The obtained grain size is 46± 5 nm and 33 ± 5 nm respectively for Al-LG and Al-SG electrode respectively.


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(a1)

(d1)

100nm

100nm

(b1)

(e1)

100nm

100nm

(c1)

(f1)

100nm

100nm

(h)

(g)

Figure 2. (a1), (b 1) and (c 1) electrode morphology and (a2), (b2) and (c2) are roughness profile of electrode deposited from Al pellet and (d 1), (e1) and (f1) electrode morphology and (d 2), (e2) and (f2) are roughness profile of electrode deposited from Al nano-particle at 10 Ås-1 , 5 Ås-1 and 1 Ås-1 respectively by AFM. (g) and (h) microstructure of Al-LG and Al-SG electrode evaporated at 1 Ås-1 by SEM.

Table 1. Al-LG and Al-SG electrode roughness obtained for various evaporation rates # Al-LG roughness (nm) Al-SG roughness (nm)

1 Å/s

5Å/s

10Å/s

4.5±0.1

9.2±0.2

10.6±0.3

5.6±0.3

9.7±0.4

12.8±0.4



4. Schottky diode properties 4.1 Diode Characteristics: J-V characteristic of the device-A and device-B is shown in Figure 3(a). . Under forward bias condition, the current variation follows Ohmic behavior from 0 V to 0.33 V and above 0.33 V current increases exponentially as shown in Figure 3(a). In lower voltage region, the increment in current is proportional to the applied electric field.

Ideality factor of the device is

calculated from Equation 1. The ideality factor of the device-A is 1.45 and device-B is 1.13. Ideality factor calculated for both the devices is between qV/2kT and qV/kT. Since device B is approaching towards ideality factor 1 signifies that trap density in this devices is lesser than Device A.

100 10

(a)

2.4

(b)

-2

0.1 0.01

2.1

1E-3 1E-4 -0.6

-0.3

0.0

0.3

0.6

0.9

Device-A

Voltage (V) 5.7

(c)

Al-LG Al-SG

5.4 4 -2

-0.9

5.1 4.8

-2

1E-5

1.8

C (cm F )

-2

J(Am )

1

J (Am )

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4.5 4.2 3.9

-3.8

-3.6

-3.4

-3.2

Voltage (V)


-3.0

Device-B

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Figure 3. (a) J-V characteristics, (b) current density @ 0.5V and (c) Mott-Schottky characteristics of diode-A and diode-B, Figure 3(b) shows statistical distribution of J and average J for device A and B is 1.74 Am-2 and 2.48 A m-2 respectively at 0.5 V. The enhancement in J of device-B accounts for strong electronic wave function overlap with active layer larger active contact area.

8,10–12

. The increment in the average J of device-B should be due to

Hence, larger active contact area improves charge transport across the

junction. Moreover, it is easy for the Al nanoparticle to diffuse into the P3HT intricate surface layer, which will reduce contact resistance across Al-SG/P3HT interface.

This reduction in contact

resistance accounts for the decrease in the barrier height. Moreover, the reduction in diode threshold voltage may be due to decrease in Schottky barrier height(calculated using Equation 2) at the metal/organic semiconductor interface. Barrier height is calculated to be 0.61 eV and 0.55 eV for AlLG and Al-SG fabricated devices respectively. Ideality factor of 2 for Al-SG suggests that the charge transport mechanism at the interface of metal/polymer layer nearly follows the thermionic emission mechanism.

This resulting change in the barrier height may be due to presence of more grain

boundaries in the Al-SG metal electrode. Also, enhanced current density in Device-B could be due to enhancing in the surface electrons energy. The depletion property of Schottky diode was studied by C-V characteristic and it is shown in Figure 3(c).

From the Mott-Schottky plot built-in voltage (Vbi) and carrier concentration (NA) were

calculated .

The calculated NA for diode-A and diode-B structure are 6.672×1016 cm-3 and

8.134×1016 cm-3 respectively. The observed increment in NA and shift in Vbi could be densely packed grains at P3HT/Al-SG interface for the improved charge carrier transport. Calculated Vbi of Device-A and Device-B is 0.55 V and 0.61 V respectively, and the shift in C(V) peak position of Device-B towards lower voltage side indicates a decrease in the interface trap density. In addition, the peak position of the capacitance of this device is high compared with Al-LG cathode diode. 5. Photovoltaic Properties



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5.1 Interface Surface morphology: The cathode (Al-LG, Al-SG electrode)/P3HT:PC 61 BM were investigated to correlate with the observed improvement in the OPV performance.

The bottom

surface of Al electrode and top surface P3HT:PC 61 BM active layer were peeled off from devices to evaluate the topography by AFM. To study the electrode microstructure Al contact was peeled off from the device and then it was dipped in 1,2 dichlorobenzene, to remove active layer residue. Figure 4 (c) and (e) shows the AFM surface morphology of Al-LG and Al-SG electrode bottom surface.

Figure 4 (d) and (f) shows P3HT:PC 61 BM surface morphology after AL-LG and Al-SG

electrode peeled off from the device. The area RMS roughness (Rq ) of Al-LG and Al-SG electrode bottom surface was measured to be 7.90.3 nm and 4.80.5 nm. This difference in roughness should be associated with higher interfacial interaction at Al-SG/P3HT:PC61 BM layer. This phenomenon is possibly mediated through the evaporating source material, their interacting nature with the active layer and final developed microstructure of electrode.

Active layer (P3HT:PC 61 BM blend) surface

roughness was calculated to be ~101 nm. P3HT:PC 61 BM blend surface roughness was correlated with electrode interface morphology to explain the device performance.

Active layer roughness

distribution respectively bottom of Al-LG and Al-SG surface is 262 nm and 353 nm respectively. Figure 4 (d) and (f) shows P3HT:PC 61 BM layer surface morphology respectively peeled off from AL-LG and AL-SG electrode.

Active layer surface roughness is 9.690.6 nm and 11.770.7 nm

respectively underneath of Al-LG and Al-SG electrode.


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(a)

(c)

(b)

(e)

(d)

(f)

(h)

(g)

Figure 4. (a) Schematic of device-A, (b) Schematic of device-B, (c) and (e) bottom surface morphology of Al-LG electrode and Al-SG electrode, (d) and (f) is topography of P3HT:PC 61 BM blend surface underneath Al-LG and Al-SG electrode. (g) and (h) electrode morphology of Al-LG and Al-SG electrode underneath surface by SEM. For the investigation of electrode properties underneath surface, Al top electrode was peeled off from the active layer of OPV device.

SEM studied interface electrode grain size and

morphology. The AFM surface morphology of AL-LG and AL-SG electrode is show in Figure 4 (c) and (e) respectively. Figure 4(d) and 4(f) is the surface morphology of the P3HT:PC 61 BM after AlLG and Al-SG electrode removed from the device. Figure 4(g) and 4(h) show the SEM morphology of Al-LG and AL-SG electrode.

Further, the peeled off electrode bottom surface was studied by

SEM and their grain size was calculated by linear intercept method and it was found to be 603 nm



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and 414 nm correspondingly for Al-LG and Al-SG electrode.

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The obtained SEM microstructure

suggests that measured grain size of Al nanoparticle evaporated measured from Al-SG is considerably smaller than Al-LG obtained. There should be an optimum Al/P3HT:PC 61 BM overlap to obtain higher power conversion efficiency. The optimum electrode/BHJ overlap will decrease the series resistance and hence enhanced carrier transport.

This interface overlap usually achieved

through the diffusing of Al electrode into the P3HT:PC 61 BM active layer. Interface grain size and morphology was correlated with the performance

13 ,14

.

5.2 Photovoltaic Characteristics: The influence of Al cathode on P3HT:PC 61 BM BHJ solar cell performance has been studied.

OPV performance was investigated keeping all device processing

fabrication parameter same except Al cathode source material. Al electrode was deposited from Al pellet and Al nanoparticle form as the source. Figure 5(a) shows dark and light J-V characteristics of device-C and device-D.

The photovoltaic devices were studied at ~1000 W/m2 illumination intensity

and using Keithley 4200SCS electrical characterization system.


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(a)

78 180

device-C device-D

150

Device-C Device-D Device-C Device-D

120 -2

J (Am )

90 60 30

-0.2

(b)

75

-2

J(Am )

0 0.0 -30 -60

0.2

0.4

0.6

72

39

0.8

Voltage (V)

dark current

device-C

40

photocurrent

36

-90

device-D

device-C

device-D

(c) device-D

30

EQE (%)

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device-C

20

10

0 300

400

500 Wavelength (nm)

600

700

Figure 5 (a) light J-V characteristics , (b) current density plot under dark (@0.5V) and illuminated condition and (c) EQE spectra of device-C and device-D. The JSC is found to be 73.50.4 Am-2 and 88.60.3 Am-2 for device-C and device-D respectively and observed an enhancement in JSC is ~17%. The power conversion efficiency increase from 2.1 % to 2.97 % mainly comes from the improvement in JSC contribution. This enhancement could be due to the improved interfacial interaction between the active layer and Al-SG cathode. The improved interfacial interaction reduces interfacial trap states and hence reduced surface charge accumulation.

Since reduced interfacial trap state density and improved electronic coupling between

Al-SG cathode with P3HT:PC 61 BM leads to improved PCE

1516

of device-B suggesting as the reason for improved JSC and FF

. Moreover, reduced series resistance 17

. These increased FF also suggests

the better physical interface in Al-SG devices for charge transfer. tabulated in the Table.2.


The photovoltaic parameters are


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Table 2. Photovoltaic parameters #

Jdark (Am-2 )@0.5V

JSC (Am-2 )

FF (%)

PCE (%)

R S (Ω)

Device-C

522

73.50.4

442

2.110.3

1.36±0.04

Device-D

643

88.60.3

483

2.970.3

1.19±0.05

5.3 C-V Characteristics: Charge carrier concentration and the built-in voltage was studied under dark and light condition by C-V technique.

Figure 4 (a) and (b) shows C-V under dark and

illumination condition of device-C and device-D respectively. Capacitance was measured from -3V to +3V with 0.1 V step and 20 kHz with 20 mV ac voltage. The maximum capacitance obtained for device-C and device-D is (2.7210.15)×10-7 Fcm-2 and (2.1350.2)×10-7 Fcm-2 respectively, and corresponding Vpeak (Voltage at peak capacitance ) is 916 mV and 999 mV under dark condition. A significant

shift

in

maximum capacitance

Al/P3HT:PC61 BM interface.

could

be

due

to

charge accumulation at the

This difference in capacitance of (5.860.05)×10-8 Fcm-2 among

device-C and device-D could be trap induced capacitance

18

. The Vpeak shift in dark C(V) spectrum is

832 mV. Furthermore photo C(V) was measurement, the peak capacitance, and its voltage was measured and it is found to be (4.5910.3)×10-7 Fcm-2 and (3.7460.2)×10-7 Fcm-2 and corresponding voltage is 4804 mV and 5008 mV respectively for device C and D respectively, and difference in capacitance between device C and D is ~ 8.64×10-8 Fcm-2 and the observed shift in Vpeak is 201.7 mV. The noted phenomenon is that Cpeak (Value of maximum capacitance measured) under the illuminated shift to the higher capacitance side, and the possible reason for the increase of Na is charge accumulation at the interfaces

18

. Moreover, it is noted that the higher asymmetry in the

photo C(V) compared with the dark C(V) spectrum. The origin of the asymmetry in light C(V) is associated with the trap states which are induced by the bulk and interface defect states

19

. The

prominence of asymmetry in light C(V) peak could be the origin of the de-trapping of the shallow


Page 17 of 28

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traps and


a

traps states during the illumination of light.

This suggests that under illumination

shallow and medium trap states are dynamics or actively participate to the capacitance. It is noted that as the trap density of states increase (tDOS) the peaking nature of the C(V) curve is more prominent.

Moreover, the increase in tDOS also increases the series resistance. The trap induced

series resistance could be the possible reason for the marginal decrease in the FF of photo J-V characteristics in Al-LG electrode device

20

. The full width at half maximum (FWHM) of C-V curve

is measured to understand the trap induce asymmetry of C(V) characteristics. FWHM of device C and D in dark condition is 1.530.2 and 1.180.2, and under illumination, it is 1.980.18 and 1.670.14 respectively.

Observed higher FWHM of Al-LG electrode in both in dark and

illumination indicates that increased density of trap states present in this device compared with AlSG electrode device. It can also be explained qualitative from the C(V) curve that peaking nature of Cpeak indicates a higher density of interface trap states. The interface traps are the primary cause of interface morphology

18

.



3.0

5

-2

) device-C -1.2

-0.6

0.0

Voltage (V)

1.2 device-D

device-C

2

4 -2

3

-7

1.8

-2

-2

2

C (10 Fcm

-7

-2

C(10 Fcm )

device-C

(b)

device-C

device-D

4

-14

4

6 C (10 cm F )

device-D

4

-14

2.4

4

-2

C (10 cm F )

(a)

-2.5

-2.0

-1.5

-1.0

Voltage (V)

2

device-D

1

0.6 -3.0

-1.5

(c)

1.5

device-C

0 -3

3.0

-2

-1

(d)

Gaussian fit

0 1 Voltage (V)

2

3

device-C device-D

-1 -3

1.0

Gaussian fit

device-D

-2

C(10 Fcm )

0.5

-8

6

0.0

5

3 0 3 10

0.30

6

4

10

5

10

6

Frequency (Hz)

0.35

10

0.40

device-C

)

9

10 -2

device-C

4

-8

device-D

C(10 Fcm

-1

15

-16

-3

0.0 Voltage (V)

DOS (10-16cm eV )

1.5 DOS (10 cm eV )

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 18 of 28

device-D 2

0 3 10

7

10

0.45

0 0.36

0.39

E(eV)

0.42

10

4

5

6

10 10 Frequency (Hz)

0.45

10

7

0.48

E(eV)

Figure 6. (a) dark and (b) illuminated C-V characteristics and inset shows dark and illuminated MottSchottky plot for device-C and device-D, (c) tDOS spectrum in dark and (d) illuminated condition of device-C and device-D and inset shows dark and illuminated state C(f) spectrum of device-C and device-D. 5.4 Mott-Schottky characteristics: Figure 6 (c) and (d) shows Mott-Schottky characteristics of device C and D measured under dark and illumination condition respectively.

From the Mott-

Schottky plot, built-in potential (Vbi) and carrier density or doping density (NA) was calculated For the calculation P3HT: PC 61 BM layer dielectric constant used is 3.5

2223

21

.

. The calculated NA under

the dark condition for device-C and device-D is (1.910.2)×1017 cm-3 and (3.550.18)×1017 cm-3


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respectively, and the observed enhancement in NA is (1.640.15)×1017 cm-3 . Also, NA has calculated device under illumination, and it was found to be (2.180.2)×1017 cm-3 and (3.840.3)×1017 cm-3 respectively for device-C and device-D and the difference in NA are 1.66×1017 cm-3 . Moreover, the NA difference among device-C and device-D under dark and illumination is ~ (2.80.01)×1016 cm-3 . Vbi was calculated from the Mott-Schottky curve under the illuminated condition, and calculated Vbi is 5202 mV and 5602 mV respectively for device-C and device-D respectively. The marginal decrease in VOC (40 mV) is possibly due to interface recombination and the interface recombination usually associated with the localized states which induce charge accumulation at the interface and thereby present at the interface.

The injection of the carrier in the direction of the current flow

accelerates the recombination at the interface. Therefore, one can also infer that increase Cpeak will have the direct consequence of the rate of recombination of charge carrier. Any charge accumulation leads to the increase in the Cpeak value which will suggest the possible recombination. This can be studied by simple conventional capacitance measurement methods.

The cumulative Mott-Schottky

parameters are given in Table 3. Table 3. NA and Vbi and capacitance Sample/

C×10 -7 (Fm-2 )

Vpeak (mV)

CVFWHM

NA ×10 17 cm-3 Vbi (mV)

Parameter

dark

light

dark

Light

dark

light

dark

light

Device-C

2.7210.15

4.5910.3

9183

4804

1.530.2

1.980.18

1.910.2

2.180.2

5202

Device-D

2.1350.2

3.7460.2

9993

5023

1.180.2

1.670.14

3.550.18

3.840.3

5602

5.5 C-f Characteristics: C-f spectra were recorded both in dark and illuminated condition for OPV is shown in Figure 6(c) and 6(d) respectively. Capacitance was measured from 1 kHz to 10 MHz with 20 mVrms perturbation frequency.

Capacitance is a function of applied frequency, and total

capacitance comprises of depletion capacitance (Cd ) and defect states capacitance (Ct).


In all C-f


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 20 of 28

study, it is observed tha decrease in capacitance as the frequency increases.

This decrease in

capacitance is correlated with the Gaussian distribution of states in the polymer semiconductor. However, at higher frequency the deep level states cannot contribute to the capacitance. In the case of OPV, trap capacitance can be described as a combination of active layer traps and interface traps 24

. The dynamic behavior of traps was studied by applying small perturbation ac signal. Since the

contribution of trap capacitance occurs only at lower frequency region

25

. Therefore, the capacitance

in lower frequency region (4 kHz) was compared for device-C and device-D.

Measured dark

capacitance at 4 kHz for device-C and device-D is (10.720.2)×10-10 Fcm-2 and (9.040.18)×10-10 Fcm-2 respectively, and the difference in capacitance is 1.68×10 -10 Fcm-2 .

A similar trend was

observed in device under illumination the computed capacitance at 2 kHz is (10.690.15)×10-9 Fcm-2 and (9.270.21)×10-9 Fcm-2 respectively for device-C and device-D. The difference in capacitance is ~1.42×10-9 Fcm-2 and an order of increase in capacitance was observed between dark and illuminated condition.

Calculated to compare the capacitance at lower frequency region measured capacitance in

the lower frequency region but device-D showed lesser capacitance values.

The C(f) follows a

similar trend, but device-C showed higher capacitance value at the lower frequency signal. The C(f) spectra impose one on the other at the very high-frequency region. This trend indicates that device-C exhibits higher capacitance whereas lower capacitance in the lower frequency region.

Higher

capacitances possible due to the higher density of trap states in this device configuration. 5.6 Trap Density of States (tDOS): To study the influence of trap states on the device performance, trap density of states were calculated from C-f characteristics. The tDOS was studied device under dark and illuminated condition calculated using Equation 3.

Figure 6(a) and 6(b) depicts the

distribution of trap defect states for the device under dark and illuminated condition. The width of trap states distribution in dark condition for device-C and device-D is (1082) meV and (912) meV respectively, and the difference in the distribution of trap states width is 17 meV.


Page 21 of 28

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This difference in width of trap distribution is attributed to higher concentration of interface defect states at P3HT:PC 61 BM/Al-LG interface. The peak energetic position of trap states (Tpeak) under the dark condition is (3612) meV and (3542) meV respectively calculated using Equation 4.

The

marginal change in peak energetic position is possibly due to change in concentration of interface traps states25.

Trap states distribution width (Tw) under illuminated condition for device-C and

device-D is 510.95 meV and 451.2 meV, the difference in trap distribution width is ~6 meV. The difference in trap width between device-C and device-D is considerable in dark condition than device under in illuminated state.

Peak position energy value of trap states under illuminated case is

(4492) meV and (4412) meV respectively for device-C and device-D.

A marginal change is

possibly due to the concentration of interface trap states among these two devices. Trap density of device under dark condition was measured, and calculated values for device-C and device-D is (7.60.19)×1017 cm-3 eV-1 and (2.10.12)×1017 cm-3 eV-1 respectively. Device-D showed significantly lower trap tDOS compared with device-C, reduction in tODS in device-D could be the possible reason for the enhancement of device efficiency.

Similarly, tDOS was quantified under the

illuminated condition, and calculated values for device-C and device-D is 5.30.16×1017 cm-3 eV-1 and 1.30.14×1017 cm-3 eV-1 respectively.

The calculated trap distribution parameters are given in

Table 4. Table 4. Capacitance and tDOS width and peak position of trap states C(f) (Fm-2 )

DOS(cm-3 eV-1 )

Tw (meV)

Tpeak (meV)

Sample/ Dark@4kHz

Light@2kHz

parameter -10

×10

dark×1017

light×1017

dark

light

dark

light

-9

×10

Device-C

10.720.2

10.690.15

7.60.19

5.30.16

1082

510.95

3612

4492

Device-D

9.040.18

9.270.21

2.10.12

1.30.14

912

451.2

3542

4412



10k

(b)

(a)

45

device-C

Phase (degree)

8k

device-D Z" (Ohm)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 22 of 28

6k

4k

device-C

30

device-D

15

2k

0 0

0

5k

10k Z' (Ohm)

15k

20k

10

2

10

3

4

10 Frequency (Hz)

10

5

Figure 7. (a) Impedance spectra of device-C and device-D measured under dark, (b) Bode phase angle against applied frequency characteristics. The interfaces properties of polymer solar cell are studied by impedance spectroscopy (IS). Figure 7 shows impedance spectra of the device measured under dark condition. The measured impedance spectra forms semi-circle, which indicates that interface impedance properties and active layer properties are super imposed. From the Nyquist plot series, the resistance of device was calculated, and it was found to be 1942.3 Ω and 1841.8 Ω respectively for device-C and devices-D. This indicates that P3HT:PC 61 BM/Al-SG interface exhibits the higher electronic coupling which reduces series resistance. Moreover, device-D semicircle diameter is larger than device-D which shows that Al-LG cathode offers higher contact resistance.

Higher ohmic resistance induces a shift of overall

arch to the right end that towards the higher resistance end. Improvement in the device properties indicates that formation of P3HT:PC 61 BM/Al interface is a critical step in the device fabrication. Since the base parameter for device fabrication step kept constant except in the top electrode


Page 23 of 28

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fabrication condition.


Hence, enhancement of device performance is possibly due to top electrode

effect. Figure 7(b) shows Bode phase (frequency) plot calculated using Equation 5. The device-D exhibits substantial phase shift towards the lower frequency side, which qualitatively indicates that longer electron lifetime.

The

value corresponding to device-C and device-D is

16501300 Hz and 10247530 Hz respectively. From the Bode plot shift in peak frequency ( is ~6254 Hz between device-C and device-D.

The considerable shift in

is associated with

BHJ/electrode interface recombination rate or lifetime of charge carriers. 5.7 Drive level capacitance profile (DLCP): DLCP technique was employed to study the OPV interface defect state properties. This method helps to quantify the bulk defect states from interface defect states separately.

Moreover, spatial distribution and energetic position of the defect

concentration can be obtained from drive level charge density (NDL). In conventional C(V) method, the defect states are highly responsive to the applied dc bias. Figure 8 (a) and (b) shows DLCP spectra of device C and D under reverse and forward bias condition. Since, non-linear contribution induced by interface defect state is excluded depletion nature exhibits linear variation during capacitance measurement in ac voltage sweep. Figure 8(c) shows the variation of carrier density on applied dc bias under dark condition.



3 2 1

2

2 -13

4

5

-13

1V 2V 3V 4V -1V -2V -3V -4V

(a)

Capacitance (10 F/m )

5 Capacitance (10 F/m )

(b)

1V 2V 3V 4V -1V -2V -3V -4V

4 3 2 1 0

0 40

60

80

100

40

ac voltage (mVrms)

60

ac voltage (mVrms)

80

100

(C) 4.0

17

-3

DLCP Na (10 cm )

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 24 of 28

3.5 3.0 2.5

Device-C Device-D

2.0 -1.2

-1.8

-2.4

-3.0

-3.6

Applied Vdc

Figure 8. DLCP curve showing junction capacitance with respect to ac drive voltage (a) device-C under revers and forward bias, (b) device-D under reverse and forward bias condition and (c) carrier density on applied dc bias under dark condition. The calculated DLCP parameters are given in Table 5. Table-5: Carrier density obtained by DLCP method at different voltage Sample/

-1V

-2V

-3V

-4V

NDL

(NDL ×1017 cm-3 )

(N DL ×1017 cm-3 )

(N DL ×1017 cm-3 )

(N DL ×1017 cm-3 )

Device-C

2.130.16

2.440.12

2.820.11

3.270.10

Device-D

3.720.13

3.780.10

3.940.12

4.210.10


Page 25 of 28

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a.c driven capacitance was investigated both in reverse (-1V, -2V, -3V & to -4V) and forward bias (1V, 2V, 3V & 4V). Carrier concentration associated with interface defect or trap states computed using equation (12) and at 0 applied dc bias.

Calculated NCDDS is (1.70.01)×1016 cm-3 and

(0.90.01)×1016 cm-3 corresponds to BHJ device with Al-LG and Al-SG electrode. The calculated NCDDS is relatively higher in device-A. The junction capacitance and NA are inversely related in a device. Therefore, on comparing the NCDDS value among different device, one can able to calculate interface defect states qualitatively.

Since the BHJ device with device-B showed smaller NCDDS than

device-C, it is possible to interpret that interface defect contributed capacitance is lesser in device-D. Moreover, the consecutive difference in carrier density of device-C electrode BHJ is 3.1×1016 cm-3 (1V to -2V), 3.8×1016 cm-3 (-2V to -3V) and 4.5×1016 cm-3 (-3V to -4V) whereas in case of device-B it is 0.6×1016 cm-3 (-1V to -2V), 1.6×1016 cm-3 (-2V to -3V) and 2.7×1016 cm-3 (-3V to -4V). The following difference in N DL is less for Device-D which indicates that defect contributing capacitance is less in the case of Device-D. interface defect states.

The obtained results suggest that it is possible to calculate the

Also, the carrier concentration obtained by conventional C(V) method is

lesser than DLCP technique, which indicates that defect concentration is lower in the case of AL-SG electrode device. 6. Conclusions In summary, it is shown that electrode fabricated from Al nanoparticle showed uniform grain size and for the given evaporation rate the grain size is considerably smaller in Al-SG electrode. The grain size distributions property is consistent with three different evaporation rates (1, 5 and 10 Ås-1 ). Based on the observed result, the Schottky diode and OPV was fabricated, and it showed significant improvement in current density and JSC respectively for Al-SG electrode device.

The significant

change in the current could be due to electrically improved active contact area at the interface. The improvement in JSC is studied by EQE measurement. The calculated tDOS explains the reduced trap



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Page 26 of 28

states in device-D, the improved interfacial interaction could reduce charge trap at the interface. Therefore, it can be interpreted that nano-structuring electrode will help in improving the charge transport. Acknowledgement This work is based upon work supported in part under the US– India Partnership to Advance Clean Energy-Research (PACE-R) for the Solar Energy Research Institute for India and the United States (SERIIUS), funded jointly by the U.S. Department of Energy (Office of Science, Office of Basic Energy Sciences, and Energy Efficiency and Renewable Energy, Solar Energy Technology Program, under Subcontract DE-AC36-08GO28308 to the National Renewable Energy Laboratory, Golden, Colorado) and the Government of India, through the Department of Science and Technology under Subcontract IUSSTF/JCERDC-SERIIUS/ 2012 dated 22nd Nov. 2012. REFERENCES (1)

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Graphical Abstract


Page 28 of 28

Interface Electrode Morphology Effect on Carrier Concentration and

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