Letter pubs.acs.org/NanoLett
Large-Scale Graphene Micropatterns via Self-Assembly-Mediated Process for Flexible Device Application TaeYoung Kim,†,⊥ Hyeongkeun Kim,†,⊥ Soon Woo Kwon,‡ Yena Kim,‡ Won Kyu Park,‡ Dae Ho Yoon,‡ A-Rang Jang,§ Hyeon Suk Shin,§ Kwang S. Suh,*,∥ and Woo Seok Yang*,† †
Electronic Material and Device Research Center, Korea Electronics Technology Institute, Gyeonggi-do 463-816, Korea School of Advanced Material Science and Engineering, Sungkyunkwan University, Gyeonggi-do 440-746, Korea § Interdisciplinary School of Green Energy, KIER-UNIST Advanced Center for Energy, Ulsan National Institute of Science and Technology (UNIST), Ulsan 689-805, Korea ∥ Department of Materials and Engineering, Korea University, Seoul 136-713, Korea ‡
S Supporting Information *
ABSTRACT: We report on a method for the large-scale production of graphene micropatterns by a self-assembly mediated process. The evaporation-induced self-assembly technique was engineered to produce highly ordered graphene patterns on flexible substrates in a simplified and scalable manner. The crossed stripe graphene patterns have been produced over a large area with regions consisting of single- and two-layer graphene. Based on these graphene patterns, flexible graphene-based field effect transistors have been fabricated with an ion-gel gate dielectric, which operates at low voltages of < 2 V with a hole and electron mobility of 214 and 106 cm2/V·s, respectively. The self-assembly approach described here may pave the way for the nonlithographic production of graphene patterns, which is scalable to large areas and compatible with roll-to-roll system. KEYWORDS: Graphene, self-assembly, patterning, large-area, flexible electronics, field effect transistor
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regular patterns over a large area.22−27 The basic principle of this assembly is based on the so-called “coffee ring” effect, in which nonvolatile solutes are carried to the pinned droplet edge (i.e., contact line) by outward flowing of solvents from the interior to the edge. While this self-assembly method often lacks precise control over feature morphology, progress toward the improved regularities has been made by confining the solution in a restricted geometry.28−37 Prior reports show that a variety of hierarchically assembled structures can be obtained by this method with materials including polymers,28−30 inorganic nanostructures,31−33 and carbon nanomaterials.35−37 Hence, the controlled self-assembly in a restricted geometry is considered to be a simple nonlithographic route to producing a range of intriguing surface patterns. However, there is a limitation associated with the surface coverage of this method, since the typical use of a fixed self-assembly guiding jig results in surface patterns over a limited area in the vicinity of the jig. In addition, as-produced surface patterns usually show a gradient in the pattern spacing and width due to a variation during self-assembly process. Therefore, the ability to engineer
raphene, a new class of two-dimensional (2D) carbon nanostructure, has stimulated intense research interest because of its unique optoelectronic properties and potential applications in electronics.1−5 The key challenges associated with its incorporation into practical electronic devices are finding large-area production of graphene and effective methods for patterning graphene into desirable architectures. One promising method for preparing large-area graphene films is by chemical vapor deposition (CVD),6−9 and significant progress has been made to realize the potential of CVD-grown graphene for its use in various electronic devices, such as transparent conductive film,10,11 sensors,12 and field effect transistors (FETs).13−16 However, to address the specific challenge of integrating graphene into such devices, a scalable and compatible patterning methodology for covering large-area graphene films should be developed. To date, graphene patterns have been achieved through patterning of catalytic metal films prior to growth8,9,17 or direct patterning of graphene after growth.18−20 Lithography has been widely used to produce graphene patterns for electronic devices but suffers from several issues including low throughput and multiple processing steps which hinder the large-scale and rollto-roll fabrication of graphene-based devices.11,21 In recent years, drying-mediated self-assembly of nanomaterials represents a nonlithographic route toward generating © 2012 American Chemical Society
Received: October 20, 2011 Revised: January 21, 2012 Published: January 25, 2012 743
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Scheme 1. Schematic Illustration for Patterning Graphene by Evaporation-Induced Self-Assembly (EISA) Methoda
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(Step 1) The CVD-grown graphene was transferred to the substrates; the PMMA formed an ordered array on graphene surface by EISA method; a portion of graphene unprotected by PMMA stripes was etched away by O2 plasma treatment, and then PMMA atop the graphene patterns was removed by solvent washing. This resulted in a graphene pattern with lateral stripes. (Step 2) Another graphene sheet was transferred onto the striped graphene patterns, and a second set of line was formed perpendicular to the first patterns, which yielded a crossed stripe pattern with regions consisting of single- and two-layer graphene.
three-phase contact line (air−solution−substrate) of the PMMA solution undergoes continuous stick−slip motions as a result of competition between the pinning and capillary forces, leaving behind periodically striped PMMA patterns on graphene surface. Subsequently, O2 plasma treatment was carried out to etch the graphene film in the region that was not protected by the PMMA stripes (i.e., PMMA-free region), followed by the removal of PMMA atop the graphene patterns. This process led to the formation of graphene pattern with lateral stripe, which is scalable to large areas. For the fabrication of cross-striped patterns, another graphene film was transferred onto the first striped graphene patterns. A second set of graphene stripes was formed perpendicular to the first by rotating the substrate 90° in the self-assembly step, thereby generating a complex pattern consisting of single- and two-layer graphene at each crossed point. Therefore, the EISA approach described here is amenable to the fabrication of the striped and cross-striped graphene patterns on flexible substrate in a scalable manner. It is also noted that this self-assembly-mediated patterning method simplifies the conventional photolithographic process by eliminating several steps, such as coating, exposure, and developing. Figure 1a schematically illustrates the pattern formation mechanism that is based on the continuous stick−slip motion of the contact line.28−37 The cylindrical roll was positioned between the lower graphene film and the upper motorized plate that is programmed to slide at a defined speed. When the PMMA solution was loaded and trapped in a confined space,
a self-assembly process in a way to yield surface patterns over large area offers a potential for its practical application. In this work, we report a simplified and scalable approach for patterning graphene over a large area by an evaporationinduced self-assembly (EISA) process. In the earlier work, we reported that chemically modified graphene sheets are amenable to the self-assembly driven by solvent evaporation.37 Here, we further extend the study to a much larger area with CVD-grown graphene toward the large-scale production of well-ordered graphene patterns by the EISA process. For this purpose, a motorized movable roll was designed and utilized to produce graphene patterns, which is scalable to arbitrarily large areas and compatible with the roll-to-roll system. We also demonstrate that the as-formed graphene patterns can be assembled into high-performance graphene-based field effect transistors (FETs) with mechanical flexibility. The fabrication of patterned graphene involved the selfassembly of polymers on graphene, as illustrated in Scheme 1. CVD-grown graphene is utilized here due to its moderately high quality and scalability for large-area device integration.7,11 Single-layer graphene film has been grown on copper foil by CVD method and transferred to poly(ethylene terephthalate) (PET) film (or SiO2/Si wafer). A detailed description on the preparation of single-layer graphene film on flexible substrate is provided in the Supporting Information.7,11 For the controlled self-assembly of polymer on graphene film, a cylindrical roll was laid on the graphene surface to provide a restricted curve-onflat geometry for the self-assembly and deposition of poly(methyl methacrylate) (PMMA). As the solvent evaporates, the 744
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value at which point capillary forces exceed the pinning force, and the contact line slips to another equilibrium position. These stick−slip cycles result in a striped PMMA pattern formation on graphene film with stripes oriented parallel to the contact line. Monitoring the in situ pattern formation by optical microscopy (Figure 1a, right) reveals that the production rate of the stripes derived from EISA is usually a few micrometers per second depending on the self-assembling conditions, such as roll moving speed, temperature, and PMMA concentration in the solution. We also note that under an optimized roll moving speed, the pattern evolution rate is stable during the whole self-assembly process, which leads to a regularly spaced graphene patterns extending over large areas (Figure S1, Supporting Information). Figure 1b shows a photograph of the graphene pattern (60 × 60 mm2) on 4 in. SiO2/Si wafer, produced by the EISA method. Laser scanning microscope (LSM) measurement reveals that the striped graphene patterns (Figure 1b, middle) have almost equivalent spacing and width of ∼18 μm, and a tapping mode atomic force microscope (AFM) analysis indicates that the average thickness for single-layer graphene is 0.7 nm. The dimension of the resulting graphene pattern is directly related to that of the self-assembled PMMA pattern on graphene film and thus can be further controlled by adjusting the selfassembling conditions, such as the concentration of PMMA solutions and the roll moving speed. (Figure S2, Supporting Information) From the image of the crossed-stripe graphene patterns (Figure 1b, right), the regions of single- and two-layer graphene are clearly identified with contrast difference,
Figure 1. (a) Schematic representation of the evaporation-induced self-assembly process and optical micrographs showing the time evolution of the PMMA stripes on graphene surface. The white arrow indicates the moving direction of contact line. (b) Photograph of graphene patterns persisting over a 4 in. SiO2/Si wafer. Optical micrographs show the striped and cross-striped graphene patterns.
the capillary force pulls the solution inward forming a thin meniscus near the contact line. While the contact line is pinned, the greater solvent evaporation rate near the pinned contact line drives the outward flow of the solution, which leads to a migration and deposition of PMMA toward the contact line. As the meniscus is stretched by the movement of the roll and solvent evaporation, a contact angle is decreased to a critical
Figure 2. (a) Raman spectra of graphene patterns: For single-layer graphene regions, the D- and G- peaks are observed around 1343 and 1588 cm−1, respectively, and the 2D-peak at 2675 cm−1. For two-layer region, the 2D-peak is observed at 2693 cm−1 with increased intensity ratio of 2D- to Gpeaks. (b) Spatial Raman maps of D-, G-, and 2D-peak energies for graphene pattern. 745
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Figure 3. Electrical properties of graphene-based all organic FETs (a) Schematic illustration of ion-gel gated graphene FETs fabricated on PET film. The molecular structure of ion gel consisting of ionic liquid and polymer matrix is shown as illustrated. (b) current−voltage transfer characteristics of the graphene FETs at different Vd. (c) Output characteristics of the graphene FETs.
channel and terminal electrodes, respectively. Then, the ion-gel gate dielectric and poly(3,4-ethylenedioxythiophene) (PEDOT) gate electrode were constructed in order onto the graphene pattern. In this work, we used ion-gel gate dielectric consisting of ionic liquid (1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide, EMIM-TFSI) and poly(ethylene oxide) (PEO), due to its high capacitance of 5.7 μF/cm2 at 0.1 Hz (Figure S4, Supporting Information). The large capacitance of ion-gel, which arises from mobile ions to form an electric double layer (EDL) at the interfaces with nanoscale thickness,42−46 allows for the large charge density in the transistor channel on the application of an electric field across the ion-gel layer. Figure 3b shows the room temperature transfer characteristics of the ion-gel gated FET devices with a graphene channel width and length of ∼16 μm. All fabricated devices exhibit a typical ambipolar transport behavior with a Dirac point and can be operated either in hole and electron accumulation regime at low gate voltages (
