Nano-electromechanical Switch Based on a Physical Unclonable

Dec 13, 2017 - A physical unclonable function (PUF) device using a nano-electromechanical (NEM) switch was demonstrated. The most important feature of...
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Nano-electromechanical Switch Based on a Physical Unclonable Function for Highly Robust and Stable Performance in Harsh Environments Kyu-Man Hwang,†,‡ Jun-Young Park,† Hagyoul Bae,† Seung-Wook Lee,†,§ Choong-Ki Kim,† Myungsoo Seo,†,§ Hwon Im,† Do-Hyun Kim,†,∥ Seong-Yeon Kim,†,∥ Geon-Beom Lee,† and Yang-Kyu Choi*,† †

School of Electrical Engineering, 291 Daehak-ro, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 34141, Korea ‡ Semiconductor R&D Center, Samsung Electronics, Hwasung 18448, Korea § System LSI Division, Samsung Electronics, Samsung-ro 1, Yongin-City, Gyeonggi-do, Korea ∥ SK Hynix Inc., 2091 Gyeongchung-daero, Bubal-eub, Icheon-si, Gyeonggi-do, Korea S Supporting Information *

ABSTRACT: A physical unclonable function (PUF) device using a nano-electromechanical (NEM) switch was demonstrated. The most important feature of the NEM-switch-based PUF is its use of stiction. Stiction is one of the chronic problems associated with micro- and nano-electromechanical system (MEMS/NEMS) devices; however, here, it was utilized to intentionally implement a PUF for hardware-based security. The stiction is caused by capillary and van der Waals forces, producing strong adhesion, which can be utilized to design a highly robust and stable PUF. The probability that stiction will occur on either of two gates in the NEM switch is the same, and consequently, the occurrence of the stiction is random and unique, which is critical to its PUF performance. This uniqueness was evaluated by measuring the interchip Hamming distance (interchip HD), which characterizes how different responses are made when the same challenge is applied. Uniformity was also evaluated by the proportion of “1” or “0” in the response bit-string. The reliability of the proposed PUF device was assessed by stress tests under harsh environments such as high temperature, high dose radiation, and microwaves. KEYWORDS: physical unclonable function, stiction, silicon nanowire, NEM switch, NEMS, security

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ered one of the most promising methods, and works related to its development have been spotlighted.4−9 PUF is based on the extraction of the intrinsic physical parameters of the device, which are then used as a physical key to distinguish between the binary states of “0” and “1”. The physical parameters are random variations that have occurred during the fabrication process, and as a result, it is impossible to clone the key. Importantly, since the silicon technology-based PUF is implemented using the CMOS fabrication process, a PUF device can be produced in a small area with high packing

n the Internet of Things (IoT) era, a wide and increasing number of electronic devices are being connected to the Internet, which results in dense networks. As the number of connections has increased, protecting personal security has become a critical issue. High-level data security requires the consumption of a large amount of power because most encryption and decryption procedures are based on encoding processes that utilize specific software.1 For this reason, alternative security methods based on hardware, such as TPM (trusted platform module)2 and eSE (embedded security element),3 which integrate cryptographic keys into the device, have been proposed for low-power and high-security applications. The physical unclonable function (PUF), an alternative hardware-based security method, has been consid© 2017 American Chemical Society

Received: September 19, 2017 Accepted: November 27, 2017 Published: December 13, 2017 12547

DOI: 10.1021/acsnano.7b06658 ACS Nano 2017, 11, 12547−12552

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Figure 1. (a) Schematics of the proposed stiction-based NEM-PUF. Stiction occurs in a random direction after drying via natural evaporation. (b) SEM image after supercritical drying (no sticting). (c) SEM and TEM image after evaporative drying (with stiction).

density.10,11 The most important factor for PUF operation is the generation of random and unpredictable characteristics in a device, which determines the degree of security of the user’s private key. These characteristics are also indispensable to preserving generated data under harsh conditions. In a silicon technology-based PUF device, the difference between the “0” and “1” state is determined by detecting a difference in electrical properties, such as resistance, charge quantity, and electron spin.12−16 However, practically, such states are vulnerable and susceptible to harsh environments, such as those encountered in outdoor use and military applications.17 For such applications, a PUF with high robustness and stability needs to be developed. In this work, a PUF based on a nano-electromechanical (NEM) switch was investigated and experimentally verified. Unlike other PUFs which rely on changes in electrical characteristics, this PUF exploits the intrinsic, unpredictable, and random variability of the mechanical actuation of a SiNW. More specifically, the approach exploits the property of stiction, a major failure phenomenon in micro- and nano-electromechanical systems (MEMS/NEMS), to reinforce the robustness of the PUF.18,19 This mechanically actuated PUF device makes it possible to preserve data under various harsh environments, ensuring excellent reliability. The differences in robustness between the previous silicon-based PUF and the proposed NEM-PUF were compared, and the results are shown in the Supporting Information (Table S1). The structure of the proposed device was inspired by the design of the independently controlled double-gate fin field-effect transistor (FinFET). The proposed structure is similar to that of a separated double-side gate FinFET,20 except that the gate oxide has been removed. The region beneath the fin (channel), which is carved by wet etching the supportive buried oxide (BOX) and sacrificial oxide, is surrounded by an air gap. As a result, the fin is positioned to float in the air and is movable between two side gates, Gate 1 (G1) and Gate 2 (G2), as shown in Figure 1a. The key process involves naturally inducing stiction during

the drying process after the removal of the sacrificial oxide layer surrounding the SiNW (fin) and the BOX underneath the SiNW. Because supercritical drying and sublimation drying have paths from the liquid to vapor state without encountering a liquid−vapor interface,21 there is no capillary force, and consequently, stiction is not induced, as shown in Figure 1b. In contrast, when natural evaporation dries the residual liquid in the air gaps between G1-SiNW, G2-SiNW, and SiNW-BOX, it induces a strong capillary force at the liquid−vapor interface.22−24 This causes the silicon nanowire (SiNW) to bend, and the evaporative drying ultimately results in stiction, as shown in Figure 1c. Ideally, the fabricated NEM switch has a symmetric structure, and accordingly, the inherent and internal forces near the SiNW are counterbalanced without stiction. However, since uncontrollable and random manufacturing variations are inevitable, stiction can occur, and there is an equal probability that the SiNW will be adhered to either G1 or G2. This random and unpredictable event is a basic requirement for the PUF. The speed and direction of drying during liquid evaporation are the primary factors that result in these uncontrollable variations in fabrication, which are key to the randomness of the PUF. In fact, it was experimentally proven that the tendency of symmetric stiction (i.e., randomness) was broken by asymmetric evaporation, which introduced an asymmetric capillary force. The resulting asymmetry causes the NEM-switch-based PUF device (designated the NEMPUF) to be nonrandom (Supporting Information, Figure S2). The state of the switch is based on the mechanical state of the fin (SiNW): the “0” state is achieved when the fin comes into contact with G1, and the “1” state is achieved when the fin is in contact with G2. While stiction initially occurs due to the capillary force, the main adhesion force which maintains stiction is the van der Waals force, which is strong enough to withstand the restoring elastic force and thus stably maintain the state of the stuck SiNW. This is the main reason why the state of the NEM-PUF is very robust against harsh environmental factors. 12548

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Figure 2. Cross-sectional view of the TEM image, top view of the SEM image, and gate current (IG) versus gate voltage (VG) characteristics of the (a) “0” state (b) “1” state. (c) Logic distribution from 13 arrays consisting of 48 bits (3 × 16) per array (total: 13 × 3 × 16 = 624 bits).

The feasibility and performance of the fabricated NEM-PUF was demonstrated by measuring important PUF parameters: uniqueness, uniformity, and reliability. First, the value of uniqueness represents the noncorrelation between the responses measured from different chips.25−27 Ideally, the responses from any two selected chips or arrays should be uncorrelated, and so the state of a PUF with ideal uniqueness is unpredictable, even when the states of other chips or arrays are known. In order to evaluate the uniqueness, the interchip Hamming distance (interchip HD) was calculated by counting the number of different bits between two chips or arrays. Second, uniformity was evaluated by the probability of observing “1” or “0” in the bit stream of the responses. Ideally, the proportion for an entirely random response is 0.5 (1/2, 50%). A PUF with a uniformity of nearly 0.5 has high randomness, which makes its output unpredictable and nonclonable. Lastly, reliability is the ability of the PUF to reproduce the same response under different operating conditions and circumstances, showing the robustness of the PUF. The intrachip Hamming distance (intrachip HD) is the relative HD between the responses measured from the same PUF under different conditions, and it can be used to evaluate the reliability of the PUF. In this paper, the robustness of the NEM-PUF was also confirmed under several harsh environments, including high temperature, high-dose radiation, and

microwaves. Additionally, a simulation was conducted to confirm that the NEM-PUF showed nearly ideal characteristics.

RESULT AND DISCUSSION After removal of the sacrificial oxide layer surrounding the SiNW and the BOX layer, the SiNW (fin) becomes attached to G1 or G2. In other words, the fin is in a binary state. The final state is based on the mechanical state of the fin: the “0” state indicates the fin is in contact with G1, while the “1” state denotes the fin is in contact with G2. Figure 2a shows scanning electron microscopy (SEM) and transmission electron microscopy (TEM) images of the fabricated NEM-PUF and gate current (IG) versus gate voltage (VG) characteristics when the fin is in the “0” state. Similarly, Figure 2b shows the images and electrical characteristics when the fin is in the “1” state. When a positive bias was applied to the G1 or G2 while keeping the SiNW at ground potential, the leakage current (IG) increased at the G1 or G2 where stiction had occurred. This IG clearly informed us about the mechanical state of the fin. If stiction is not present, the NEM switch can be neither the “0” state nor the “1” state; that is, it is at a neutral position. The bendable fin can be considered analogous to a spring with a spring constant, k. In order to increase the capillary force of the fin, the airgap width (Wairgap) must be narrowed. k is known to be reduced as the fin length (Lfin) increases and the fin width 12549

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Figure 3. Histogram of the normalized (a) interchip HD and (b) uniformity experimentally extracted from 13 PUF arrays consisting of 48 bits per array. Comparison of simulation and measurement data on (c) interchip HD and (d) uniformity at various array sizes.

(Wfin) decreases. Increasing Lfin is an inefficient use of space. Reducing the Wairgap and Wfin is a more efficient way of promoting the occurrence of stiction. It should be noted that the proposed PUF device has a symmetric structure with equivalent air gaps on both sides of the movable SiNW. Since both sides of the movable SiNW have the same capillary force, ideally the probability of stiction occurrence is the same for both sides of the movable SiNW. This symmetric structure can be leveraged as physical randomness to implement the PUF. To examine the feasibility and performance of the PUF, NEM-PUF arrays were fabricated as shown in the Supporting Information (Figure S3), and the combined results from 13 arrays were obtained. A single array size is 48-bit (3 × 16 array). Figure 2c exhibits the logic distribution of the NEM-PUF arrays, which lack a regular and ordered pattern. To examine the quality of the PUF data, key parameters were calculated. The uniqueness represents the ability of the PUF to be authentically identified. It can be determined by measuring and comparing the interchip HD responses of a pair of PUFs for the same input, which is ideally 50%. The interchip HD between any two PUF arrays can be calculated as follows: interchip HD =

2 k(k − 1)

k−1

k

∑ ∑ i=1 j=i+1

uniformity =

1 n

n

∑ bi × 100(%) i=1

where bi is the i-th bit of the response and n is the length of response, that is, the size of the PUF array. The ideal value of uniformity is 50%. Figure 3b also shows that the mean of the distribution is close to the ideal value (average = 49.67% and σ is 3.16%). This result implies that there is equal probability for the data to be “0” and “1” in each PUF array, and that the signatures generated by the PUF arrays are unique. This experimental data demonstrate that the stiction tendency of the SiNW is random and unpredictable. The simulations additionally confirmed that the proposed PUF exhibited nearly ideal characteristics, as shown in Figure 3. Experimentally measured groups, each of which is composed of 13 arrays, were 8-bit group, a 24-bit group, and a 48-bit group depending on the array size. Simulated groups, which were implemented using the random function of MATLAB, were also composed of 13 arrays per group and classified depending on the various array size from 8 bits to 1 Mbits. A comparison of the simulated and experimental results of the interchip HD and uniformity depending on the array size of the PUF are shown in Figure 3c,d. These results indicate that the measurement results fit well with the ideal. In the simulation data, when the number of bits in an array was more than 100 bits, the interchip HD and uniformity converged to the ideal values of 50%. The standard deviation of the parameters was also less than 5% when the array size was more than 100 bits. Accordingly, a NEM-PUF with more than a 100-bit array exhibits a more ideal performance. In general, to produce randomness in PUFs to enhance security, various approaches have utilized the uncontrollable variations that occur during the fabrication process. Previous silicon technology-based PUFs have used variations in electrical characteristics, such as changes in the threshold voltage in flash memory,14 random geometric variations in magnetic random access memory,15 and the stochastic switching mechanism of resistive random access memory.16 PUFs such as these, based on variations in electrical characteristics, have shown good randomness and uniqueness; however, they have been

HD(R i , R j) n

× 100(%)

where Ri and Rj are the n-bit responses of the arrays “i” and “j” for a given challenge. k is the number of arrays, and n is the PUF array size. In the fabricated PUF arrays, a total of 13C2, that is, (13 × 12)/2 = 78 statistical data can be made. Figure 3a shows the histograms of the normalized interchip HD extracted between any two of the 13 PUF arrays based on 48-bit (3 × 16 array). The distribution of the interchip HD is centered at 50.3% with a standard deviation (σ) of 7.4%, very close to the ideal value of 50%. This experiment proves the excellent uniqueness of the NEM-PUF. Uniformity, another key parameter of the PUF, refers to the distribution of “0” and “1” in a PUF response. For an n-bit response, uniformity is computed as the percentage Hamming weight, as follows: 12550

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Figure 4. Comparison of the data state before and after the various stresses: (a) baking at 150 °C for 24 h, exposing to (b) γ-radiation with 5 Mrad, and (c) microwave with 2.45 GHz and power of 800 W for 7 min.

CONCLUSIONS In summary, we demonstrated a highly robust PUF device based on the random stiction of a nano-electromechanical switch. The random formation of stiction in the SiNW causes the proposed PUF to be unpredictable and highly robust. The PUF characteristics of uniqueness, randomness, and reliability were experimentally evaluated. The NEM-PUF not only has the advantages of monolithic integration and CMOS compatibility, like previous silicon-based PUFs, but also the benefits of improved robustness and reliability thanks to the NEMS design. These features qualify the NEM-PUF for use in personal security applications. Moreover, this PUF was very stable in harsh environments, making it suitable for aerospace and military applications. In addition, this device can be selfdestructive to provide a higher level of security28 as shown in the Supporting Information (Figure S4).

vulnerable to harsh environments. Unlike previous PUFs, the stability of the NEM-PUF stems from the nature of the physical actuation of the SiNW, which have very strong adhesion force, and can stably preserve a given state despite harsh conditions. This very important characteristic is related to reliability and durability in security applications. To evaluate the data retention of the proposed PUF, several stresses were applied to accelerate the device’s failure. First of all, the PUF device was baked at 150 °C for 24 h. Second, after the bake stress, it was exposed to γ-ray irradiation of 5 Mrad. Finally, it was also exposed to microwave irradiation in a microwave oven at 2.45 GMHz with a power of 800 W for 7 min. Even though this experiment does not reflect a realistic environment, it does demonstrate the immunity to strong electromagnetic waves. Figure 4 shows a comparison of the logic state before and after these stress operations. Although the proposed PUF device was exposed to harsh environmental conditions, there was not a single bit failure among all 288 bits. These experimental results show that the NEM switch PUF is highly robust and stable against harsh environments. Intrachip HD, one of the key parameters of the PUF, can be also quantitatively described by bit error rate, which is the percentage of error bits out of response bits due to stress on the PUF. The intrachip HD can be calculated as follows: intrachip HD =

1 k

k

∑ l=1

HD(R i ,1 , R i ,2) n

METHODS The fabrication details of the proposed NEM-PUF are shown in Supporting Information Figure S5. The fabrication process is similar to that used for the fin flip-flop actuated channel transistor (FinFACT) process,29 except for the intentional stiction. A p-type (100) silicon wafer was used as a starting material. The thickness of the thermally grown buried oxide and the top polycrystalline silicon (poly-Si), which becomes the SiNW (fin), were 400 and 100 nm, respectively. A fin with the Wfin of 100 nm was patterned by a nitride hard mask. A 15 nm thick sacrificial oxide and 200 nm thick n+ poly-Si gate were conformally deposited around the fin. The poly-Si gate was then separated by chemical mechanical polishing (CMP). Meanwhile, the nitride hard mask was used as an etching stopper layer during the CMP. As a result, two independent gate electrodes were formed on either side of the fin. After a gate with a Lfin of 2000 nm was patterned, the sacrificial oxide and the buried oxide were selectively removed by diluted HF solution. Finally, stiction of the suspended fin was induced as a result of surface tension during the evaporative drying process. Measurement of the device characteristics was conducted with a semiconductor parameter analyzer (4156C, Agilent Technology Inc.). The stiction state, that is, the stiction between G1 and SiNW or

× 100(%)

where Ri,1 and Ri,2 are the n-bit responses of the array “i” before and after the stress. n is the size of the PUF array, and k is the number of arrays used in the calculation. The ideal value of the intrachip HD is “0”. As shown in Figure 4, it was proven that the intrachip HD of the fabricated NEM-PUF had an ideal value of “0”. 12551

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ACS Nano between G2 and SiNW, was identified by applying a positive bias to the gates and zero bias to the source and drain.

(10) Gassend, B.; Clarke, D.; Van Dijk, M.; Devadas, S. Silicon Physical Random Functions. Proceedings of the 9th ACM Conference on Computer and Communications Security, November 2002, pp 148−160. (11) Lim, D.; Lee, J. W.; Gassend, B.; Suh, G. E.; Van Dijk, M.; Devadas, S. Extracting Secret Keys from Integrated Circuits. IEEE T. VLSI Syst. 2005, 13, 1200−1205. (12) Holcomb, D. E.; Burleson, W. P.; Fu, K. Power-up SRAM State as an Identifying Fingerprint and Source of True Random Numbers. IEEE Trans. Comput. 2009, 58, 1198−1210. (13) Hu, Z.; Comeras, J. M. M. L.; Park, H.; Tang, J.; Afzali, A.; Tulevski, G. S.; Hannon, J. B.; Liehr, M.; Han, S. J. Physically Unclonable Cryptographic Primitives Using Self-Assembled Carbon Nanotubes. Nat. Nanotechnol. 2016, 11, 559−565. (14) Kim, M. S.; Moon, D. I.; Yoo, S. K.; Lee, S. H.; Choi, Y. K. Investigation of Physically Unclonable Functions Using Flash Memory for Integrated Circuit Authentication. IEEE Trans. Nanotechnol. 2015, 14, 384−389. (15) Zhang, L.; Fong, X.; Chang, C. H.; Kong, Z. H.; Roy, K. Highly Reliable Memory-Based Physical Unclonable Function Using SpinTransfer Torque MRAM. Circuits and Systems (ISCAS), 2014 IEEE International Symposium, 2014, pp 2169−2172. (16) Chen, A. Utilizing the Variability of Resistive Random Access Memory to Implement Reconfigurable Physical Unclonable Functions. IEEE Electron Device Lett. 2015, 36, 138−140. (17) Herder, C.; Yu, M. D.; Koushanfar, F.; Devadas, S. Physical Unclonable Functions and Applications: A tutorial. Proc. IEEE 2014, 102, 1126−1141. (18) Maboudian, R.; Howe, R. T. Critical review: Adhesion in Surface Micromechanical Structures. J. Vac. Sci. Technol., B: Microelectron. Process. Phenom. 1997, 15, 1−20. (19) Yapu, Z. Stiction and Anti-Stiction in MEMS and NEMS. Acta Mech. Sin. 2003, 19, 1−10. (20) Fried, D. M.; Duster, J. S.; Kornegay, K. T. Improved Independent Gate N-type FinFET Fabrication and Characterization. IEEE Electron Device Lett. 2003, 24, 592−594. (21) Miller, S. L.; Rodgers, M. S.; LaVigne, G.; Sniegowski, J. J.; Clews, P.; Tanner, D. M.; Peterson, K. A. Failure Modes in Surface Micromachined Microelectromechanical Actuators. In Reliability Physics Symposium Proceedings. 36th Annual IEEE, 1998. (22) Buks, E.; Roukes, M. L. Stiction, Adhesion Energy, and the Casimir Effect in Micromechanical Systems. Phys. Rev. B: Condens. Matter Mater. Phys. 2001, 63, 033402. (23) Van Spengen, W. M.; Puers, R.; De Wolf, I. A Physical Model to Predict Stiction in MEMS. J. Micromech. Microeng. 2002, 12, 702. (24) Butt, H. J.; Kappl, M. Normal Capillary Forces. Adv. Colloid Interface Sci. 2009, 146, 48−60. (25) Chen, Q.; Csaba, G.; Lugli, P.; Schlichtmann, U.; Rührmair, U. The Bistable Ring PUF: A New Architecture for Strong Physical Unclonable Functions. In Hardware-Oriented Security and Trust (HOST), 2011 IEEE International Symposium, 2011, pp 134−141. (26) Majzoobi, M.; Koushanfar, F.; Potkonjak, M. Testing Techniques for Hardware Security. Test Conference, 2008. ITC 2008. IEEE International, 2008, pp 1−10. (27) Maiti, A.; Casarona, J.; McHale, L.; Schaumont, P. A Large Scale Characterization of RO-PUF. In Hardware-Oriented Security and Trust (HOST). In 2010 IEEE International Symposium, 2010, pp 94− 99. (28) Han, J. W.; Seol, M. L.; Choi, Y. K.; Meyyappan, M. SelfDestructible Fin Flip-Flop Actuated Channel Transistor. IEEE Electron Device Lett. 2016, 37, 130−133. (29) Han, J. W.; Ahn, J. H.; Choi, Y. K. FinFACTFin Flip-Flop Actuated Channel Transistor. IEEE Electron Device Lett. 2010, 31, 764−766.

ASSOCIATED CONTENT S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsnano.7b06658. Differences in robustness between the previous siliconbased PUF and NEM-PUF; control experiment designed to confirm the effect of liquid evaporation rate and drying direction on the randomness; implemented PUF array; self-destructible NEM-PUF for improved security against hacking; process flow of the nano-electromechanical switch-based PUF (PDF)

AUTHOR INFORMATION Corresponding Author

*E-mail: [email protected]. ORCID

Yang-Kyu Choi: 0000-0001-6678-5451 Notes

The authors declare no competing financial interest.

ACKNOWLEDGMENTS This work was sponsored by the Center for Integrated Smart Sensors funded by the Ministry of Science, ICT & Future Planning as Global Frontier Project (CISS-2011-0031848). This work also partially sponsored by the Global Ph.D. Fellowship Program (2017H1A2A1042274 and 2014H1A2A1022137) through the National Research Foundation (NRF) of Korea funded by the Ministry of Science and ICT. REFERENCES (1) Moradi, A.; Barenghi, A.; Kasper, T.; Paar, C. On the Vulnerability of FPGA Bitstream Encryption Against Power Analysis Attacks: Extracting Keys from Xilinx Virtex-II FPGAs. Proceedings of the 18th ACM Conference on Computer and Communications Security, October 2011, pp 111−124. (2) Bajikar, S. Trusted Platform Module (TPM) Based Security on Notebook PCs-White Paper; Mobile Platforms Group, Intel Corporation, June 20, 2002; pp 1−20. (3) Francis, L.; Hancke, G.; Mayes, K.; Markantonakis, K. On the Security Issues of NFC Enabled Mobile Phones. Int. J. Internet Technol. Secured Trans. 2010, 2, 336−356. (4) Suh, G. E.; Devadas, S. Physical Unclonable Functions for Device Authentication and Secret Key Generation. Proceedings of the 44th Annual Design Automation Conference, June 2007, pp 9−14. (5) Maes, R.; Verbauwhede, I. Physically Unclonable Functions: A Study on the State of the Art and Future Research Directions. Towards Hardware-Intrinsic Security; Springer: Berlin, 2010; pp 3−37. (6) Nellore, V.; Xi, S.; Dwyer, C. Self-Assembled Resonance Energy Transfer Keys for Secure Communication over Classical Channels. ACS Nano 2015, 9, 11840−11848. (7) Helinski, R.; Acharyya, D.; Plusquellic, J. A Physical Unclonable Function Defined Using Power Distribution System Equivalent Resistance Variations. Proceedings of the 46th Annual Design Automation Conference, July 2009, pp 676−681. (8) Ozturk, E.; Hammouri, G.; Sunar, B. May. Physical Unclonable Function with Tristate Buffers. IEEE International Symposium on Circuits and Systems 2008, 3194−3197. (9) Rosenfeld, K.; Gavas, E.; Karri, R. Sensor Physical Unclonable Functions. IEEE Int. Symp. 2010, 112−117. 12552

DOI: 10.1021/acsnano.7b06658 ACS Nano 2017, 11, 12547−12552