Article www.acsanm.org
Cite This: ACS Appl. Nano Mater. XXXX, XXX, XXX−XXX
Rapid Fabrication of 100 nm or Thinner Fully Depleted Silicon-onInsulator Materials for Ultralow Energy Consumption Benjamin T.-H. Lee,* Ching-Han Huang,1 Chia-Che Ho,2 and Fa-Sain Lo3 Department of Mechanical Engineering, National Central University, Taoyuan City 32001, Taiwan, ROC S Supporting Information *
ABSTRACT: The fully depleted silicon-on-insulator (FD-SOI) wafer is the core material of the FD-SOI technology used for manufacturing the applications with ultralow energy consumption for internet of things, artificial intelligence, automotive, and wearable devices. Ion-cut process is the main technology to fabricate FD-SOI wafers. After ion cutting, the silicon layer transferred on the insulator includes a spongelike damaged layer. Therefore, it must contain a thinning buffer layer with a thickness more than 150 nm to remove the damaged layer by a polishing step. The requirement of the additional buffer layer makes the direct fabrication of a less than 100 nm thick SOI layer from the as-split status impossible. Here, we develop a process based on solid-phase epitaxial growth (SPEG) technique, abandoning the polishing step, and thus achieve a one-step fabrication of FD-SOI substrate. First, inducing amorphization of an SOI layer via blistering supersaturated hydrogen ions through microwaving fully consumes the possible stable defect clusters. Next, using SPEG technique catalyzed by surrounding hydrogen ions restores the amorphized SOI layer to the initial crystalline structure. To approach the purpose, a silicon (Si)-clad layer deposited on the oxidized surface was used. The Si-clad layer has two functions promoting the success of SPEG processing. It acts as a filter to prevent co-implanted impurities in the silicon layer to avoid the occurrence of crystal segregation during recrystallization. It also serves as a sacrificial layer to bring the split location close to the implant peak causing the hydrogen concentration in the entire SOI layer in supersaturation. When amorphizing this layer, an undamaged crystalline layer is retained at the interface of the SiO2/Si as a seed layer to promote the regrowth of a perfect SOI layer in a argon-annealing step. By integrating with the ion-shower implantation used in flat-panel display manufacturing, the technology can fabricate the next generation of larger SOI wafers without the need to upgrade the ion implanter. KEYWORDS: FD-SOI, hydrogen enhancement, ion-cut process, layer transfer, solid-phase epitaxial-growth process, ultralow energy consumption
■
INTRODUCTION Fully depleted silicon-on-insulator (FD-SOI) is a planar-type process technology used for integrated circuit (IC) device manufacturing. Its primary innovation is an ultrathin singlecrystal silicon layer on an insulator implementing the transistor channel. Because the ultrathin thickness makes the transistor fully depleted, there is no need to dope the channel that reduces processing steps. The insulating layer of FD-SOI can also minimize leakage of the electrical current while nanoscale IC devices are operating, which greatly decreases power consumption and improves performance. The feature enables ultralow-power electronic applications,1,2 which expand the core technological capability of wireless devices ranging from internet of things (IOT) to automotive to artificial intelligence (AI) even to the implementation of a scalable quantum processor-based complementary metal oxide semiconductor (CMOS) quantum computers.2,3 Furthermore, transistors fabricated on FD-SOI wafers are planar, so they may serve as a cost-efficient alternative to 3D finFETs.4,5 The core material of FD-SOI technology is the FD-SOI wafer. Therefore, the key to the development and popularization of FD-SOI transistors is how to make large, uniform, © XXXX American Chemical Society
defect-free, and ultrathin FD-SOI wafers at a low cost. In the current production of SOI material technology, the most important technique is the ion-cut process6 or smart-cut process.7 Through the technique, a silicon layer with a thickness of less than 100 nm split from a prime wafer is transferred onto a surface-oxidized silicon wafer to form an FDSOI wafer. Invented in 1992,8 the ion-cut process6 has been developed into a mature manufacturing technology for silicon on insulator (SOI) materials and many applications in sensors, optoelectronics, and microelectronics.9−14 However, this process always requires the addition of a polish-to-thin step to remove the damaged region caused by layer-splitting and to thin the transferred layer (usually at several hundred nanometers) to a thickness of less than 100 nm. In a typical ion-cut process including H+ implantation, wafer bonding, and layer splitting, two factors degrade the yield and throughput of manufacturing FD-SOI wafers. One factor is the Received: April 11, 2018 Accepted: April 24, 2018 Published: April 24, 2018 A
DOI: 10.1021/acsanm.8b00602 ACS Appl. Nano Mater. XXXX, XXX, XXX−XXX
Article
ACS Applied Nano Materials requirement for an ultrahigh hydrogen dose ([H+] > 1.0 × 1017 ions/cm2) for layer-splitting,15 which renders low-energy implantation (e.g., 5 keV for 100 nm SOI16,17) very difficult to integrate into the manufacturing system. This occurs because the implant energy must usually be higher than the extraction voltage of more than 30 keV for producing a sufficiently high dosage.18 The second factor is the introduction of a polish-tothin step15,19 that may allow the expected thickness precision to decrease substantially. Here, we present the nanoscale solid-phase epitaxial-growth (SPEG) technique20−22 catalyzed by the surrounding hydrogen ions23,24 established in ion implantation processing to completely remove damage in the 100 nm silicon layer. Yamashita et al.25 reported that hydrogen ions in silicon induced by plasma irradiation (temperature < 480 °C) can remarkably enhance dislocation mobility. In general, the concentration of hydrogen ions acquired via diffusion from hydrogen plasma is much lower than that injected from ion implantation (usually in supersaturation). Nevertheless, the activation energy is still significantly reduced from 2.2 eV (under hydrogen-free conditions) to 1.2 eV (with hydrogen plasma irradiation). The concept of the SPEG technique uses self-ion implantation first to destruct the defect clusters in a solid film amorphizing the entire film but reserving an unimplanted portion as a seed layer.20,21 Then, in a following high-temperature annealing step, the crystalline of the film is completely recovered by crystal regrowth via the reserved seed layer. The technique is successfully applied to manufacturing silicon on sapphire (SOS) wafers, overcoming the serious issue of crystal defects owing to a notable lattice mismatch between silicon and sapphire.26 In a conventional ion-cut process, the high-temperature annealing in the layer-split stage enhances the rapid diffusivity of hydrogen atoms. Hydrogen atoms conglomerate to form microvoids that are then aggregated into cracks, platelets, void clusters, or extrinsic dislocation loops, thereby forming several stable and tough defects distributed throughout the splitting location. The traces and remnants of stable defects can be erased with preamorphization following annealing processes27,28 because, for silicon, the activation energy required to annihilate defects (>5 eV) is greater than that needed to regrow the crystalline structure from an amorphous state via SPEG (2.5−2.7 eV).29 Figure 1 shows the flowchart of the nanoscale SPEG technique for fabricating nanoscale SOI wafers. However, in the study, we report the critical condition necessary for fabricating a sub-100 nm thick SOI material using the nanoscale SPEG technique, which could be met with excited supersaturated hydrogen ions. To demonstrate the concept of an extensible ion-implanted area applied to future larger wafers, we adopted a ribbon-beam ion-shower implantation system to implant hydrogen (H2+) ions. The samples were 300 mm silicon prime wafers precovered by a bilayer of chemical vapor deposition (CVD) deposited 150 nm Si-clad layer and 100 nm of thermal SiO2 layer. The Si-clad layer can adjust the H+ implant depth30 for splitting a silicon layer less than 100 nm but avoid reducing implant energy below 30 keV.18 The clad layer acts not only as a sacrificial layer to absorb the implant energy and most of the bombardment damage but also serves as a filter blocking any co-implanted impurities weighing more than hydrogen ions. Impurity-free is a necessary condition for perfect recrystallization, because, in silicon, subsequent annealing to reconstitute
Figure 1. Flowchart of the nano-SPEG technique for fabricating nanoscale SOI wafers. (a) A 150 nm silicon layer being deposited on the oxidized surface of silicon substrate. (b) Hydrogen ion implantation forming a concentration peak location for layer transferring (The layer to be transferred will be in the supersaturation of hydrogen ions). (c) Sacrificial layer removal and (d) wafer bonding to fuse the implanted wafer with a handle wafer. (e) Microwave irradiation splitting and blistering (right-lower) the transferred layer, originally including stable defect clusters (right-upper) but reserving a seed layer (left) at the interface of the SiO2/wafer, and (f) the SPEG process, restoring the whole layer to the form of a perfect crystalline structure.
the crystalline lattice structure may lead to the precipitation of impurities. The precipitation of impurities during recrystallization may occur ahead of the advancing crystal−amorphous interface or may remain randomly dispersed and incorporate into the crystalline lattice, depending on the diffusivity of the impurity.31 In short, the introduction of the impurities may alter the intrinsic crystallization kinetics of silicon causing the inhomogeneity of solid-state recrystallization.29 After the Si-clad layer is passed, a large amount hydrogen ions were decelerated and then inserted in the interstitial sites at or a little beyond the end of the projected range by electronic stopping rather than nuclear stopping. 32 The damage morphology affected its annealing behavior and thus the damage accumulation. On the one hand, formation of B
DOI: 10.1021/acsanm.8b00602 ACS Appl. Nano Mater. XXXX, XXX, XXX−XXX
Article
ACS Applied Nano Materials nanovoids by restricting the out-diffusion of interstitial hydrogen led to a distortion or strain of the lattice but not severe destruction of the crystal structure.27 On the other hand, thermal annealing usually makes defect clusters stable, because it agglomerates a number of interstitial hydrogen atoms together via diffusion, leading to the formation of platelets that coalesce into larger microcavities and clusters. To demonstrate the concept of an extensible ion-implanted area applied for future larger wafers, we adopted a ribbon-beam ion-shower (IS) implantation system to implant hydrogen (H2+) ions. The ion-shower implantation system lacks a mass filter and is designed for thin-film transistor (TFT) fabrication; thus, it provides very high implantation efficiency for implanting hydrogen. The samples were 300 mm, (100) oriented, CZ boron-doped 1−50 ohm cm, 775 μm silicon prime wafers, which were prepared by thermally growing a 100 nm SiO2 layer and then depositing an undoped 150 nm polycrystalline silicon layer. In the ion-shower implantation system, five silicon wafers were mounted on a 920 mm × 730 mm graphite plate to receive H2+ ion implantation at 60 keV with a dose of either 5 × 1016 or 2.5 × 1016 ion/cm2 (Figure S1 in Supporting Information). After ion implantation, the deposited Si layer was removed with a tetramethylammonium hydroxide solution (20 wt %) at 80 °C. Then each sample was cleaned using the RCA process and was dried, packaged, and delivered to a wafer bonding site. Bonded samples were annealed for 1 h either by 750 °C heating or by 900 W microwaving. The as-split SOI wafers were then cut into 20 mm × 20 mm pieces, annealed at 950−1050 °C in argon, and inspected using transmission electron microscopy (TEM) for structure analysis. Figure 2 shows the structures of the processing materials for hydrogen ion-shower implantation and the corresponding cross-sectional TEM image.
Figure 2. Structure of the processing materials for hydrogen ionshower implantation and the cross-sectional TEM image. (a) Schematic illustration of the structures of the processing materials and the functions of the top Si/SiO2 bilayer. (b) Cross-sectional TEM image of a specimen implanted with H2+ at a dose of 2.5 × 1016 ions/ cm2 by ion-shower implantation. The deeper damaged region was caused by the co-implanted H+ ions. In addition, the implant damage caused by the co-implanted H3+ was located in the silicon clad layer, and the layer was removed by tetramethylammonium hydroxide etching prior to the wafer bonding.
■
RESULTS AND DISCUSSION After H2+ was implanted at 5.0 × 1016 ions/cm2, equal interval strip tracks appeared on the wafer surface due to the overlapped implantation caused by the ribbon-beam design.33 However, the strip tracks disappeared after the implant dose was reduced to half. In Figure 3, the secondary-ion mass spectrometry (SIMS) measurements showed all hydrogen profiles between the SiO2/ Si interface and the concentration peak being plateaulike and in supersaturation ([H+] = 3.5 × 1021 > (1.5−2.5) × 1021 atoms/ cm3). Two peaks on the hydrogen profiles were caused by the co-implanted three hydrogen species in the plasma source: H+ (75%), and H3+ (
