Reconfigurable Complementary Monolayer MoTe2 Field-Effect Transistors for Integrated Circuits Stefano Larentis,*,† Babak Fallahazad,† Hema C. P. Movva,† Kyounghwan Kim,† Amritesh Rai,† Takashi Taniguchi,‡ Kenji Watanabe,‡ Sanjay K. Banerjee,† and Emanuel Tutuc† †
Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas 78758, United States ‡ National Institute for Materials Science, 1-1-Namiki, Tsukuba, Ibaraki 305-0044, Japan S Supporting Information *
ABSTRACT: Transition metal dichalcogenides are of interest for next generation switches, but the lack of low resistance electron and hole contacts in the same material has hindered the development of complementary fieldeffect transistors and circuits. We demonstrate an air-stable, reconfigurable, complementary monolayer MoTe2 fieldeffect transistor encapsulated in hexagonal boron nitride, using electrostatically doped contacts. The introduction of a multigate design with prepatterned bottom contacts allows us to independently achieve low contact resistance and threshold voltage tuning, while also decoupling the Schottky contacts and channel gating. We illustrate a complementary inverter and a p-i-n diode as potential applications. KEYWORDS: transition metal dichalcogenides, MoTe2, transistor, reconfigurable, hBN encapsulated
T
the ML limit, rendering this class of materials a promising platform for optoelectronic devices.1,3 TMDs, along with graphene and hexagonal boron nitride (hBN) and their heterostructures, offer a unique combination of material, electronic, and optical properties, which could be exploited for the development of new device architectures.8 In spite of these promising attributes, most TMD-based devices have so far been limited by the availability of reliable, low resistance contacts for both electrons and holes in the same TMD material.9 Specifically, MoS2 has to date received most of the attention due partially to its availability and stability but also, more fundamentally, to its low resistance contacts for electron injection, securing good n-type performance, despite showing moderate intrinsic mobility.10,11 Recently, WSe2 based p-FETs have outperformed their MoS2 counterparts, thanks to low resistance Pt bottom contacts for hole injection, showing room temperature mobility >100 cm2/V·s.12,13 While both MoS2 n-type and WSe2 p-type-based FETs have shown promising performance, it is important to be able to
ransition metal dichalcogenides (TMDs) have, to date, drawn significant interest due to their semiconducting properties. Their two-dimensional (2D) nature combined with the presence of a sizable energy band gap (>1 eV), as opposed to graphene, allows to readily fabricate field-effect transistors (FETs) with high ON−OFF current ratio.1 Molybdenum- and tungsten-based TMDs have garnered the lion’s share of attention, with MoS2 being the most investigated material due to its geological availability and environmental stability down to a monolayer (ML).2 Early assessments of TMDs’ electrical and mechanical properties showed promise, suggesting that TMDs could be employed as a future channel material candidate for more-than-Moore applications, namely, low cost, flexible integrated circuits (IC), as well as lightemitters, detectors, and sensors.3−5 The TMDs’ 2D nature allows thickness scaling down to one ML, ∼0.7 nm, providing optimum electrostatic gate control necessary to enable gate length scaling past the 10 nm node.6 The energy band gap is a function of the number of layers, with TMD MLs exhibiting the largest band gap (>1 eV),7 a feature desirable for low-power operation in FETs.4 Different TMDs offer an array of thicknessdependent band gaps spanning the visible and near-infrared spectra, as well as the availability of a direct energy band gap at © 2017 American Chemical Society
Received: February 23, 2017 Accepted: April 6, 2017 Published: April 17, 2017 4832
DOI: 10.1021/acsnano.7b01306 ACS Nano 2017, 11, 4832−4839
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Figure 1. (a,b) Optical micrograph of exfoliated hBN flakes on SiO2/Si. (c) Selective hBN pick-up schematic, showing release on target: MoTe2 flake or Cr-Pt gate. (d) PDMS micromechanical handle bonded on glass, with inset showing handle’s hemispherical shape. Optical micrographs showing (e) ML MoTe2 exfoliated on SiO2/Si; (f) hBN/MoTe2 stack formed immediately after exfoliation to protect MoTe2 from atmospheric degradation; (g) Cr−Pt local bottom gate, defined on SiO2/Si; (h) Cr−Pt local gate underneath the bottom hBN dielectric; (i) bottom contact patterning, with two sets of high WF metals (∼15 nm) onto bottom hBN. (j) Optical micrograph showing the hBN/MoTe2 stack on PPC/PDMS after pick-up, also illustrated in the cross-sectional schematic of (m). The hBN/MoTe2 stack released on the patterned bottom contacts as shown in the optical micrograph (k) and cross-section schematic (m). (l) Optical micrograph of the final device, after top gate pattering in alignment with the underlying contacts. (n) 3D illustration of the top half of the completed device in (l).
RESULTS AND DISCUSSION Here, we report the fabrication of an air-stable ML MoTe2 transistor fully encapsulated in hBN. The introduction of a multigate scheme, with a local bottom control gate, contact, and plunger gates, allows for decoupling and control of the gate-dependent contact resistance (RC), channel resistance, and device threshold voltage (VT), independent of the unintentional flake doping. Local contact gates are used to induce a large carrier concentration in the proximity of the metal−TMD contact, allowing for reduced contact resistance, independent of the channel gating, and reconfigurable electron or hole injection depending on the bias polarity. This electrostatic doping-enabled device scheme is used to design a complementary inverter and a diode, showing potential for its use in ICs and optoelectronic devices. We fabricate our encapsulated MoTe2 FETs by forming a vertical hBN-MoTe2-hBN heterostructure, as shown in Figure 1. Using a two-step process, we first stack the top hBN dielectric onto the ML MoTe2, then we place this stack on a set of high work function (WF) metal contacts, prepatterned on the bottom hBN dielectric. Figure 1a,b shows two hBN flakes on a SiO2/Si substrate, which will serve as the top and bottom dielectrics, respectively. After exfoliation, the hBN flakes are selectively detached (Figure 1c) using a small contact area hemispherical handle, shown in Figure 1d.30 In order to avoid possible atmospheric degradation of exfoliated MoTe2 MLs (Figure 1e), hBN flakes (∼5−10 nm) are aligned and released on the ML region (Figure 1c,f), immediately after exfoliation. Once the MoTe2 ML is hBN-encapsulated, we proceed to pattern the bottom gate and the bottom contacts. To form the bottom gate stack, we first pattern a Cr-Pt local bottom gate on a different SiO2/Si substrate (Figure 1g), which we cover with the bottom hBN dielectric (∼10−20 nm), as shown in Figure 1c,h. Two sets of metal contacts are then patterned on the bottom hBN (Figure 1i). We note that in a bottom contact architecture, where the metal contacts are exposed for extended time to atmosphere, high WF metal contacts are desirable. In our investigation, we considered the following metals with WF > 5 eV:31 Ni, Pd, Au, and Pt, which we assume to be largely immune from substantial surface oxidation. An ultra-high
integrate both p- and n-type transistors in the same TMD material, possibly down to a ML, as opposed to hybrid structures where p- and n-type transistors are integrated on different TMDs.14 It is also equally important to explore complementary architectures, as opposed to pseudo n-MOS ones,15 which use only one type of transistor. Possible solutions to integrate complementary FETs in the same TMD include a number of doping techniques relying on chemical doping (K, NO2),16,17 organic molecules,18 or substoichiometric oxides.19 Another route is electrostatic doping achieved through gating.20 In this approach, a set of buried or overlapping split gates are biased at different, opposite voltages, allowing to define spatially controlled p-type (hole) or n-type (electron) doped regions, enabling diverse device structures, such as p−n diodes, as demonstrated in carbon nanotubes.21−23 To utilize this doping scheme, the semiconductor needs to exhibit ambipolar behavior, namely contacts should be able to inject both electron and holes depending on the gating polarity. ML MoTe2 is a favorable candidate for ambipolar injection, being characterized by an intermediate electron affinity (χ) = 3.8 eV24 and narrower energy band gap (EG) = 1.1 eV,25 compared to ML WSe2 (χ = 3.5 eV, EG = 1.7 eV)13,24 and ML MoS2 (χ = 4.2 eV, EG = 1.8 eV).7,26 In addition, 2D materials properties are often sensitive to environmental conditions. In particular, organic residues, chemical adsorbate contamination,27 atmospheric degradation,28 and metal contact deposition instability10,12 may degrade FET performance, for example, impacting devices’ contact resistance, carrier mobility, and threshold voltage. The high surface-to-volume ratio, typical of any 2D material, is an inherent reliability and process integration challenge, and while bulk MoTe2 is stable, the exfoliated material is particularly sensitive to atmospheric interaction, showing obvious signs of degradation in air.29 This renders the fabrication of back-gated, top-contacted structures, where the channel is exposed, extremely challenging, particularly at the ML limit,14 thereby necessitating stable encapsulation techniques in order to achieve reliable operation. 4833
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Raman spectra show the typical ML MoTe2 signature characterized by two peaks corresponding to A1g and E12g modes at 174 and 239 cm−1, respectively, and the absence of the B12g mode (∼290 cm−1), present in thicker flakes.25,29 The red traces refer to areas where the MoTe2 is hBN-encapsulated, and black ones refer to exposed areas. The encapsulated MoTe2 spectra show little variation over time, with both peaks remaining clearly visible and their intensity unchanged, whereas exposed regions show a dramatic reduction in the peaks’ intensity, until no Raman signature is detected. Measuring the intensity ratio of ML MoTe2 E12g and Si 520 cm−1 peaks (IE12g/ ISi) as a function of time allows us to track the flake degradation. The exposed region’s IE12g/ISi drops quickly, more than half in less than 24 h, consistent with the observed optical contrast variation. Conversely, the hBN-encapsulated region’s IE12g/ISi remains unchanged for an extended period, >250 h, confirming the encapsulation reliability (Figure S2 in the Supporting Information). Optical contrast and Raman spectroscopy data confirm that ML MoTe2 flakes have a short lifetime in air, and that hBN encapsulation proves effective in preventing oxidation. Once we established that hBN-encapsulated MoTe2 MLs remain structurally intact, we fabricated dual-gated, bottomcontacted, hBN-encapsulated MoTe2 devices. We first examine devices characterized by a top gate and a local bottom gate, as illustrated in Figure 3b inset. The top gate overlaps both channel and contact regions, while the bottom gate is patterned underneath the channel and the bottom contacts, as shown in Figure 3a,b insets. Tuning the top gate bias (VTG) induces carriers in both the channel and contact regions. Carriers induced in the contact region, at the TMD−metal interface, modulate the contact’s Schottky barrier, determining electron and hole injection, which determines RC.12 Conversely, tuning the bottom gate bias (VG) induces carriers only in the channel because of screening by the bottom contacts. Figure 3a,b shows the top gate transfer characteristic (ID vs VTG) at different drain biases (VD), and VG = 0 V for a set of four different high WF metal contacts, Ni, Pd, Au, and Pt. All traces are obtained from a multicontact device fabricated using a single MoTe2 ML. Each pair of metal contacts defines a device with channel length L = 0.75 μm and a width W = 3.5 μm, defined by the top gate (Figure 3a inset). The top hBN dielectric is 11.8 nm thick. The ID vs VTG data display ambipolar behavior, resulting from VTG modulating both the contact and channel regions, injecting electrons for positive VTG (n-branch), and holes for negative VTG (p-branch). The ID vs VTG data measured weeks apart after the initial encapsulation show reliable current levels and threshold voltage stability, confirming that encapsulated monolayers are electrically stable (Figure S3 of Supporting Information). For all metal contacts examined here, the ID vs VTG data for the p-branch show high ON−OFF current ratios ION/IOFF > 106, at VD = 1 V, comparable with that of other TMDs,10,12 whereas n-branches ION/IOFF are about 2 orders of magnitude lower for Ni, Au, and Pt metal contacts. For Pd metal contacts, n-branch ION/IOFF > 105 at VD = 1 V, revealing an ambipolar behavior, with comparable injection for electron and holes. Figure 3c shows the expected MoTe2−metal band alignment in the contact region, based on the difference between metal WFs and ML MoTe2 χ.24,31 Based on this band alignment picture of Figure 3c, we expect the metals’ Fermi levels to align toward ML MoTe2 valence band edge, determining predom-
vacuum anneal allows for the hBN/MoTe2 stack to be picked up at once (Figure 1j,m) and transferred on the prepatterned high WF metal contacts (Figure 1k,m). Finally, top gates are defined in alignment with the underlying contact electrodes (Figure 1l). Figure 1n illustrates the completed hBNencapsulated MoTe2 device. The air stability of exfoliated 2D layers varies significantly from one material to another. While graphene and hBN do not show visible degradation in air over a period of many months, black phosphorus degrades in a matter of days.32 Sulfur- and selenium-based TMD MLs are characterized by an intermediate air stability compared to that of graphene and black phosphorus and are prone to environmental degradation over a period of several weeks to months.28 MoTe2 ML on the other hand has been shown to be considerably more unstable, showing clear signs of degradation resulting from interaction with atmospheric O2.29 A significant variation of optical contrast and the Raman spectra intensity capture this interaction. Figure 2a−c
Figure 2. (a−c) Optical micrographs of a MoTe2 flake taken over the course of 5 days. A section of the ML region is hBNencapsulated. The optical contrast decreases with time in the exposed ML region (black dot). (d) Raman spectra of different ML MoTe2 regions, marked in panels (a−c), and their evolution with time. The red (black) traces represent the encapsulated (exposed) region.
and S1 (Supporting Information) show two different sets of optical micrographs illustrating the optical contrast evolution of two MoTe2 flakes as a function of time, including a MoTe2 ML partially covered with hBN. While the optical contrast variation with time, associated with the MoTe2 flake degradation, is different for each individual exposed flake, the results generally show an optical contrast that drops monotonically until the flake becomes invisible under optical microscopy. On the other hand, hBN-encapsulated MoTe2 flakes (Figure 2a−c) and thicker MoTe2 flakes (Figure 2a−c and S1) do not display appreciable optical contrast variation during the same time frame. While optical contrast variation provides a qualitative estimate of the degradation process, Raman spectroscopy offers a more systematic way to track the time-dependent structural alterations in the exposed material and verify the encapsulation effectiveness. Figure 2d shows the Raman spectra of the corresponding MoTe2 ML regions highlighted in Figure 2a−c, measured using a 532 nm excitation wavelength. The measured 4834
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Figure 3. (a,b) ID vs VTG measured at VD = 0.1 V and 1 V for Ni, Pd, Pt, and Au metal contacts, showing ambipolar behavior, injecting holes (electrons) for VTG < 0 (>0) V. The data display good hole injection, whereas electron injection is strongly metal-dependent (W = 3.5 μm, L = 0.75 μm, thBN,top = 11.8 nm). Panel (a) inset shows the device top-view schematic, and panel (b) inset shows a 3D illustration of the device. (c) Illustration of the expected band alignment between MoTe2 ML and the high WF metal contacts.24,31 (d) |ID| vs VG measured at different VTG values, for VD = ±0.1 V for a device with Pt contacts. While VTG modulates each branch’s RC, depending on the its value and polarity, a variation of both VTp and VTn (marked with solid symbols, VTG = 0 V trace) depending on the VTG is also observed, not allowing independent adjustment of RC and VT (W = 13 μm, L = 1 μm, thBN,top = 8.2 nm, thBN,bottom = 18.5 nm).
Figure 4. (a) Schematic of the gating layout showing top view and cross section. The device is characterized by a local bottom gate, two contact gates, and a plunger gate (W = 4 μm, L′ = 0.9 μm, LPG = 0.25 μm, thBN,top = 5.5 nm, thBN,bottom = 18 nm). (b) ID1,2 vs VCG1 measured at VD = 0.1 V and 1 V (Pt contacts), showing ambipolar behavior. The solid symbols indicate the VCG values used in panels (c,d). (c,d) |ID2,3| vs VG measured at |VD| = 0.1 V and 1 V. Setting different VCG1,2 < 0 (>0) V determines p-FET (n-FET) reconfigurable operation. The contacts gates induce high carrier densities at the metal−MoTe2 junction, modulating RC but also no longer impacting the VT. Tuning the VPG values allows adjustment of the threshold voltage without affecting the RC.
VG measurements show ambipolar characteristics displaying a clear insulating state between p- and n-branches. Two threshold voltages, for each branch, VTp and VTn, are marked with solid symbols on the VTG = 0 V trace in Figure 3d. Their values are extrapolated from the linear region of each branch. A clear variation of both VT values as a function of the VTG is apparent in Figure 3d. While an applied VTG induces carriers in the channel and sets both VT values concurrently, it also changes the carrier density in the proximity of the contact metal− MoTe2 interface, thus affecting the RC value. Increasing the | VTG| value reduces the transfer characteristic typical ambipolar character. For example, negative VTG values result in a decrease of the p-branch and an increase n-branch RC and vice versa. While rendering the transport unipolar is desirable, the device structure of Figure 3 does not allow an independent tuning of VT and RC. The inherent limitation of this device structure stems from the top gate geometry, which concurrently controls the contact region and channel carrier densities. To mitigate the VTG induced VT shift and render the device unipolar, a different gating scheme is required.
inant hole injection for all metals considered. Conversely, our measurements show ambipolar transfer characteristics for each metal contact, particularly in the case of Pd where p- and nbranch currents at |VTG| = 5 V differ by less than an order of magnitude. These experimental results suggest that MoTe2− metal contact band alignment based on existing WF and χ values cannot accurately predict the carrier injection, a finding consistent with experimental observations in MoS2 FETs.10 The emergence of ambipolar, as opposed to predominant ptype conduction, may result from Fermi level pinning toward midgap energies at the MoTe2−metal interface (Figure 3c). Tellurium vacancies in MoTe2 are believed to give rise to midgap states responsible for the Fermi level pinning,33 which would explain the emergence of ambipolar conduction even when high WF metal contacts are used. Figure 3d shows transfer characteristics (|ID| vs VG) measured at different fixed VTG values, for VD = ±0.1 V, using a device with Pt contacts, W = 13 μm, and L = 1 μm, as shown in Figure 3b inset. The hBN thicknesses for the top (thBN,top) and bottom (thBN,bottom) dielectric are 8.2 and 18.5 nm, respectively. |ID| vs 4835
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Figure 5. (a) |ID| vs VG measured for p- and n-FET at |VD| = 0.1 V and 1 V. Different VCG value settings allow us to define complementary nand p-FETs, namely, a Au-contacted n-FET (VCG > 0 V) and a Pt-contacted p-FET (VCG < 0 V), whereas VPG settings allow to set symmetric VTs. Inset shows a schematic of the device (W = 6.5 μm, L′ = 0.9 μm, LPG = 0.25 μm, thBN,top = thBN,bottom = 12 nm). (b) |ID| vs VD measured for p- and n-FET at different fixed VG values, showing current saturation. (c) |ID| vs VPG1,2 measured for p- and n-FET at |VD| = 0.1 V and 1 V. The plunger and bottom gate roles are exchanged, compared to (a), showing good symmetry between VG and VPG in this device design. Fixed VG values are used to set either VT, with VCG values settings the same as that in (a). (d) Measured voltage transfer characteristic (VTC) of the complementary inverter gate for different VDD, obtained using p- and n-FET of (a,b). Good VTC symmetry is obtained by tuning VCG values, balancing pull-up and pull-down transistors. The inset shows the biasing scheme for the inverter operation. (e) Voltage gain = |dVOUT/dVIN| vs VIN for different VDD values. For each VDD in the transition region (near VDD/2), the voltage gain is larger than 1, ensuring signal regeneration properties of the logic gate. (f) |ID| vs VD measured for opposite VCG values, thus defining a p-i-n junction, showing rectifying behavior. The inset shows a schematic of the device cross section (W = 5 μm, L = 1.5 μm, thBN,top = 12.3 nm).
marked with solid symbols in Figure 4b, allows us to measure unipolar p- and n-type |ID2,3| vs VG, where VCG1,2 < 0 V (VCG1,2 > 0 V) allows for hole (electron) injection (Figure 4c,d). The VCG polarity determines electron or hole injection, as shown in Figure 4b, while the VCG value determines RC for either device type. As described earlier, Pt contacts are expected to yield lower RC for hole injection (Figure 4b), as is reflected by the maximum |ID2,3| measured for each characteristic. Tuning the carrier density in the contact regions using individual contact gates electrostatically dopes the contacts, allowing for RC control, and decoupling of the contact gate dependent RC from the channel resistance, which is controlled by the bottom gate. The use of contact gates render the contacts selective for electron or holes, thus enabling reconfigurable unipolar devices. Ideally, reconfigurable devices, based on truly ambipolar, low RC contacts would allow IC reconfiguration down to the single transistor, which would be either p- or n-type depending on the contact gates’ polarity.34 Most importantly, Figure 4c,d data show that the applied VCG1,2 no longer impacts the VT in either p- or n-type configuration, as opposed to Figure 3d data. We note that devices with split contact gates but without a plunger gate do not allow for RC and VT decoupling because the contact gates’ fringing field will still affect the channel, rendering VT again VCG dependent.
Figure 4a illustrates a new gating scheme, where a single top gate is replaced by two separate top contact gates (CG1, CG2) and by an additional plunger gate (PG), introduced between the two split contact gates. The structure retains the local bottom gate patterned under the bottom hBN dielectric. The use of two individual contact gates and a plunger gate instead of a single top gate allows us to separately control the carrier density in the contact and channel regions of the device, thus separately controlling VT and RC. An additional contact is introduced (contact 1 in Figure 4a) to measure the individual transfer characteristic for contact gate 1 (ID1,2 vs VCG1). Figure 4b shows ID1,2 vs VCG1 at VG = 0 V, displaying ambipolar behavior, similar to Figure 3b data. Measuring ID1,2 vs VCG1 allows us to evaluate carrier injection as a function of the VCG, that is, p-type (n-type) injection for VCG < 0 (>0) V, and estimate the RC for each branch (for an estimation of the RC from a multiterminal device, see Figure S4 in the Supporting Information). Figure 4c,d shows the measured bottom gate transfer characteristic between contacts 2 and 3 (|ID2,3| vs VG) at fixed contact gates 1,2 (VCG1,2) and plunger gate (VPG) biases. The distance between the two contact gates (L′) is 0.9 μm, plunger gate length LPG = 0.25 μm, flake width W = 4 μm, and thBN,top = 5.5 nm and thBN,bottom = 18 nm. Setting fixed VCG1,2 values, 4836
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ACS Nano Figure 4d shows |ID2,3| vs VG measured at VPG = 0, 0.5, 0.75 V. Tuning the VPG value compensates for unintentional doping in the region underneath the plunger gate, allowing for VTn adjustment without compromising RC, which is set by the contact gates. The subthreshold swings (SS) for the p- and nFET are 180 mV/dec (VCG1,2 = −3 V, VPG = 0 V) and 240 mV/ dec (VCG1,2 = 4.75 V, VPG = 0.75 V), respectively, while using an 18 nm thick hBN bottom gate dielectric. The VT and SS values for either type FET are largely insensitive to VD, consistent with a long channel picture. The availability of p- and n-type devices along with the ability to achieve symmetric characteristics allows us to design complementary logic gates. Figure 5a shows a schematic of the complementary device where two sets of bottom contacts and top gates are introduced to integrate two complementary FETs, along with a common local bottom gate. Two separate sets of contact and plunger gates allow to control and decouple each FET’s RC and VT, in order achieve balanced p- and n-FET performance, required for complementary logic operation. Two separate sets of Pt and Au metal contacts are used to integrate p- and n-FETs, respectively. In this specific implementation, the Au contacts are chosen for the n-FET over the Pt ones because they provide better electron injection, as shown in Figure 3b. Figure 5a shows |ID| vs VG for both p- (VG, VD < 0) and n-FET (VG, VD > 0), measured for a set of fixed VCG and VPG values, with W = 6.5 μm, L′ = 0.9 μm, LPG = 0.25 μm, and thBN,top = thBN,bottom = 12 nm. The VCG values are set to provide the highest ID, and the VPG values are set to determine matching threshold voltages for the p- and n-FET, |VT| ≅ 1.45 V, extracted from the linear region of |ID| vs VG, for VD = ±0.1 V traces. The output characteristics (|ID| vs VD) for both p- and n-FET, measured for the same set of VCG and VPG biases in Figure 5a, are shown in Figure 5b. The |ID| vs VD characteristics show linearity at low VD and current saturation at high VD. Figure 5c shows a set of plunger gate transfer characteristic (|ID| vs VPG1,2) for both p(VPG1, VD < 0) and n-FET (VPG2, VD > 0) using the same device considered in Figure 5a,b. In this measurement, the roles of bottom gate and plunger gates are exchanged compared to Figure 5a. The plunger gate modulates the channel, and fixed VG values are set to achieve matching threshold voltages (VTp ≅ −1.5 V, VTn ≅ 1.7 V, extracted from the linear region of |ID| vs VPG1,2, for VD = ±0.1 V traces). The VCG values are the same as in Figure 5a,b, set to minimize RC for both p- and n-FET. Our dual gating scheme is largely symmetric, albeit not fully because the PG does not cover the entire channel (LPG < L′). Such partial symmetry is displayed by the lower peak drain currents shown in Figure 5c as compared to Figure 5a, with a peak current ratio close to 1/2. The channel regions between contact and plunger gates behave as contact access regions when using the plunger gate as the control gate. These areas are only affected by contact and plunger gates’ fringing field, while VG is set to obtain matching VT values. Hence, the contact access regions are lightly doped, thus limiting the maximum ID because of their series resistance contribution. Figure 5d shows the configuration used to implement a complementary inverter gate, where the p- and n-FETs described earlier (Figure 5a,b) are connected in series. Their drain contacts are shorted, defining the inverter output voltage (VOUT) node, while the source of the n-FET is grounded and the source of the p-FET is connected to the supply voltage (VDD). The input voltage of the inverter (VIN) is connected to the local bottom gate. Figure 5d shows the voltage transfer characteristic (VTC) of the inverter, for a set of VCG and VPG
biases specified in Figure 5e. The inverter operates as follows: at low VIN the n-FET is off, and the p-FET (pull-up) connects VOUT to VDD, while for high VIN the p-FET is off, and the nFET (pull-down) connects VOUT to ground, effectively inverting the VIN signal, thus performing the NOT logic operation. The VTC displays full logic swing with wide noise margin, and a steep transition between the logic states. The logic state’s transition is characterized by the voltage gain | dVOUT/dVIN|, shown in Figure 5e as a function of VIN. In the transition region, near VDD/2, the voltage gain is larger than 1 (Figure 5e), implying signal regeneration through the logic gate. Noise immunity of the inverter is characterized by the high and low noise margins (NML, NMH), measured as a percentage of the VDD: NML = 37% and NMH = 32% for VDD = 2 V. While the p- and n-FET performance remains uneven in this demonstration, and further work is needed to improve the nFET performance, the successful integration of a complementary inverter gate reveals potential for this device scheme, relying on electrostatic doping. To obtain a symmetric VTC transition, the VCG1,2 values for the p-FET are tuned as a function of VDD, to balance the pull-up and pull-down transistors. The VPG values for the p-FET are left unchanged because, as shown in Figure 4c,d the VT is largely independent of VD and VCG. Figure 5f inset shows a device structure with split contact gates, but without a plunger gate. Applying opposite, fixed VCG values to the adjacent contact gates, we obtain two contacts, one selective to electron injection and another selective to hole injection. The contact gates overlap the channel determining two spatially defined electrostatically doped regions adjacent to the bottom contacts, a p- and n-doped region, respectively. This scheme resembles a traditional Si p-i-n junction, where spatially defined p and n regions are achieved through substitutional doping. The diode characteristic (|ID| vs VD), measured for VCG1 = 8 V and VCG2 = −6 V, displays rectifying behavior, coupled with series resistance effects at large VD biases. Electrically tunable ML MoTe2 p-i-n diodes can be of interest for optoelectronic applications, such as photodetectors, photovoltaic cells, and light-emitting diodes in the infrared spectrum. Similar devices have been integrated using ML WSe2 electrically tunable diodes.35−37
CONCLUSIONS In summary, we report the successful fabrication of an air-stable and reconfigurable ML MoTe2 FET. hBN encapsulation of MoTe2 MLs prevents atmospheric degradation, preserving structural and electrical properties, as confirmed using Raman spectroscopy. Using a set of prepatterned high WF contacts and introducing contact specific gates to tune the carrier density at the metal−MoTe2 junction, we obtain a gate-independent low RC, enabling reconfigurable unipolar operation. Adding a plunger gate between individual contact gates allows us to set VT independently from RC. The availability of p- and n-FET with low RC and adjustable VT allows for complementary operation, demonstrated by integrating a complementary inverter on a single MoTe2 ML flake, highlighting possible integrated circuit application. Using a similar gating scheme, MoTe2 electrostatic doping enables p-i-n diode fabrication, showcasing potential optoelectronic applications. The importance of this multigate structure goes beyond MoTe2-based devices, allowing to decouple channel gating and the Schottky contacts. 4837
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ACS Nano Notes
MATERIALS AND METHODS
The authors declare no competing financial interest.
Device Fabrication. The devices are fabricated using monolayer MoTe2 (commercially available from HQ Graphene) and hBN flakes (5−20 nm), which are exfoliated onto a 285 nm thick SiO2 dielectric, thermally grown on a highly doped Si substrate (SiO2/Si). MoTe2 MLs are identified using optical contrast and Raman spectroscopy. MoTe2 MLs are susceptible to atmospheric degradation and need to be hBN-encapsulated immediately after exfoliation. The typical amount of time between ML individuation and encapsulation, where the flake is exposed to air, is ∼30 min. hBN flakes are selectively detached from the exfoliation substrate using a small contact area (
