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Chemical lnstrurnentation Edited by GALEN W. EWING, Seton Hall University, So. Orange, N. J. 07079
These articles are intended to serve the readers o j ~ mJOURNAL s by calling attention to new developmenla i n the theory, design, m availobilily of chmical laboratory instrumentation, m by presenting zlsejul inaights and explanations of topics that are of practical imporlonee to those who use, m leach the use of, modem instrumentation and instrumental techniques. The editor invites correspondence from prospective contributors.
LXXI.
An Introduction to Microelectronics (Concluded) Edward M. Winkler a n d Maarten van Swaay, Kansas Stale Un,.nrsiry. Department o f Chemistry. Manhaltan. Kansas 66506
MONOLITHIC CAPACITORS
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A Loeiesl source of ca~aeitancein a monolithic circuit is junction capacitance. A double diffused junction cspacrtor (Fig. 2ua1 may be created simultaneously with the base of an npn transistor. The upper p-type region forms one plate of the capacitor, and the n-isolation region makes up the other. The equivalent circuit includes two diodes instead of a parasitic pnp transistor, because the capacitor junction should never he fmvard-biased, i.e., it should never function as an emitter. The substrate junction is always reverse-hiased. The series resistance of the lower plate is represented by RI, and C o is the parasitic capacitance. The ratio of totalto-shunt capacitance is about 20:1, which limits the usefulness at high frequencies. The sandwich junction capacitor (Fig. 20b) effectively doubles the area of the dielectric and thereby increases the C/C,s ratio. Note that the latter structure is in effect an npn transistor with a common emitter-collector contact. The junction capacitor has many disadvantages. The width of the depletion layer will vary with the bias voltage, resulting in a nonlinear capacitance characteristic. In addition, the capaeitor is polarized, i.e., the emitter diode must always he reversebiased. Both of these objections are eliminated with the MOS (metal-oxide-semiconductor) capacitor (Fig. 20c). ~
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MOS TECHNOLOGY The dielectric in the MOS capacitor is an oxide layer, usually SiOz, and the upper electrode is deposited during metallization. The oxide layer is formed by removal of the original film and regrowing a new film to a thickness of about 500A.The C/Crs ratio depends on the hias voltage, hut it is greater than that of the junction capacitor. In addition, series resistance and leakage are lower. A394
/ Journal of Chemical Education
Another MOS capacitor structure, which illustrates the thin-film nature of these devices, is shown in Fig. 20d. In that respect, MOS capacitors are compatible with the monolithic process (thin-film monolithic or compatible circuits). An active MOS device which has significantly contributed to digital and memory monolithic circuitry is the field effect transistor (FET) (51, 57, 58). Recent improvements in FET performance have also promoted a serious challenge to applications which were previously dominated by hipalar devices. The attractive features of the FET are its small size and the need for fewer process steps. The size factor allows increased packing density and decreases the probability of failure due to metallization faults, e.g., pin holes. Control of the conduction mechanism bv maioritv , . carrwrs offera two additional advantages over the bipolar transiator: lower noise lewls. and less degradation due to nuclear radiation. The current path is compatible with the monolithic geometry, i.e. parallel to the surface, and operation is not destroyed by diffusion spikes across the channel. The primary disadvantages of FETs are the slower switching speed and smaller handwidth. All FETs have source, gate, and drain electrodes. Current flow between the source and drain is modulated by control of the cross sectional area of an induced channel or of the charge carrier density by means of the gate voltage. For the FET most commonly used in monolithic circuits an oxide layer separates the gate from the substrate. A variety of names have been derived from that structure: metal-oxide-semiconductor, or silicon, transistor (MOST or MOSFET); insulated-gate-FET (IGFET); and metal-insulator-semiconductor-FET (MISFET). An IGFET produced by p-type diffusion into an n-type suhstrate or isolation region is illustrated in Fig. 21. Please note that only a single diffusion step is required, compared to two for the hipolar transistor. ~~~~~~
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A negative voltage induces hole migration, resulting in a depletion layer under the oxide (Fig. 22). At a characteristic voltage (threshold voltage, VT),a p-channel inversion layer connects the two p+ electrodes and current flow begins. The current will increase to a limiting value as the negative gate bias increases (enhancement mode operation). Such a device is referred to as a p-channel IGFET orP/MOS. An IGFET is self-isolating, i.e., the source, drain, and induced channel are isolated by their own p-n junctions, and the gate is isolated by the thin oxide layer.
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Figure 22. Formation of depletion and inversion layers in e P/MOS device.
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