Shell Nanowires through

LETTER pubs.acs.org/NanoLett

Transport Modulation in Ge/Si Core/Shell Nanowires through Controlled Synthesis of Doped Si Shells Yanjie Zhao,† Joshua T. Smith,‡,§ Joerg Appenzeller,‡,§ and Chen Yang*,|| Department of Physics, ‡Department of Electrical and Computer Engineering, §Birck Nanotechnology Center, Department of Chemistry, Purdue University, West Lafayette, Indiana 47907, United States )

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bS Supporting Information ABSTRACT: Appropriately controlling the properties of the Si shell in Ge/Si core/shell nanowires permits not only passivation of the Ge surface states, but also introduces new interface phenomena, thereby enabling novel nanoelectronics concepts. Here, we report a rational synthesis of Ge/Si core/shell nanowires with doped Si shells. We demonstrate that the morphology and thickness of Si shells can be controlled for different dopant types by tuning the growth parameters during synthesis. We also present distinctly different electrical characteristics that arise from nanowire field-effect transistors fabricated using the synthesized Ge/Si core/shell nanowires with different shell morphologies. Furthermore, a clear transition in the modification of device characteristics is observed for crystalline shell nanowires following removal of the shell using a unique trimming process of successive native oxide formation/etching. Our results demonstrate that the preferred transport path through the nanowire structure can be modulated by appropriately tuning the growth conditions. KEYWORDS: Core/shell nanowire, doped shell, dopant, growth rate, transport modulation, nanowire trimming, nanowire heterostructures

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emiconducting nanowires with controllable structures, compositions, and predictable properties have been demonstrated as the building blocks for exploratory research and emerging technologies.1 The unique structure of core/shell heterostructure nanowires, especially Ge/Si nanowires synthesized by the chemical vapor deposition (CVD) method,2 has led to promising discoveries for future nanoelectronic applications. Extensive works have been reported, including experimental and theoretical studies of high-performance nanoelectronics,3
6 exploration and utilization of low-dimensional physics and quantum confinement effects,7
11 impacts of structure, composition, defect, and strain on bandgap engineering and electrical performance,12
17 novel nanoelectronic applications such as superconducting devices,18 surround-gate nanowire field-effect transistors (NWFETs),19 and nonvolatile crossbar switches,20 as well as nanoscale mechanics21,22 and thermoelectric properties.23 While Ge/Si nanowire heterostructures show great promise toward novel nanoelectronic applications, previous work has mainly focused on intrinsic Si shells. Additionally, a detailed study on the controllable synthesis of the shell is still missing at this point. Understanding the impact of growth conditions on the doped shell of Ge/Si core/shell nanowires will allow for control of shell uniformity, morphology, thickness, and doping concentration, therefore enabling further possibilities in bandgap engineering. A variety of new and desirable electronic functionalities can be realized by this Ge/doped Si core/shell arrangement. For example, nanowire band-to-band tunneling (BTBT) devices, a r 2011 American Chemical Society

promising candidate for future low-power computing,24 requires an abrupt source/channel junction with a degenerately doped source. This requirement can be conveniently met by using a Ge/ doped Si nanowire architecture, since the nature of this two-step CVD synthesis coupled with controllable dopant incorporation at the shell growth step provides a highly tunable band alignment with an abrupt junction at the Ge/Si interface. Additionally, by simply extrapolating the foregoing single shell growth study, more complex systems consisting of core/multilayer-shells2 and nanowires with alternate core materials with Si shells25
27 can be realized to appropriately tune electronic properties for a given application. To this end, we report a rational synthesis of the Ge/ Si core/shell nanowires with doped Si shells. We demonstrate that the morphology and thickness of Si shells can be controlled for different dopant types by tuning growth parameters during synthesis. We also present vastly different electrical characteristics for synthesized Ge/Si core/shell nanowires with n-type amorphous (a-Si) and crystalline Si (c-Si) shells, providing clear evidence of preferred transport through the core and shell, respectively. Furthermore, a unique comparison of NWFET characteristics obtained from n-type c-Si shell nanowires before and after a controlled shell trimming process is used to support the notion of selective transport. Received: September 2, 2010 Revised: February 16, 2011 Published: March 21, 2011 1406

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Figure 1. (a) TEM image of a representative Ge/a-Si core/shell nanowire. (b) HRTEM image at the Ge/a-Si interface. (c) TEM image of a representative Ge/c-Si core/shell nanowire. (d) HRTEM image at the Ge/c-Si interface. Inset: FFT of (d), arrows indicate distinct diffraction signals at [111] position. Scale bars for (a
d) are 20, 5, 20, and 5 nm, respectively.

Ge/Si core/shell nanowires were prepared using a two-step CVD method.2 Radial growth of the Si shell was achieved following the axial growth of the Ge core by altering the synthetic conditions to favor vapor-phase deposition on the Ge surface. Au nanoparticles of various diameters were used to initiate axial growth of the Ge core. All Ge nanowire cores in this study were synthesized at identical conditions, namely, 5 sccm of GeH4 (10% in H2) and 80 sccm of H2 at total pressure of 100 Torr and 260 °C for 2 h, varying only the size of the Au particles used. After Ge nanowire growth, the residual GeH4 was purged from the system while maintaining the flow of H2 to prevent any potential oxidation of the Ge core. Intrinsic Si shell growth was then accomplished using 10 sccm of SiH4 (10% in H2) with 200 sccm H2 at a lower pressure, 25 Torr, a condition in which conformal surface deposition is favored. The effects of growth temperature on shell morphology were studied by transmission electron microscopy (TEM) imaging of nanowires with shells grown at 470 and 600 °C. A representative TEM image of a Ge/Si nanowire with the shell grown at 470 °C is shown in Figure 1a. The clear contrast indicates the different elements: the Ge core at the dark region in the center and Si shell represented by the lighter region surrounding the core. The measured core diameter of 22 nm is consistent with 20 nm Au nanoparticle used, an indication of a well-controlled process during the core growth step. The shell with a uniform and conformal thickness has almost a uniform contrast due to full relaxation of the Si atoms. A high-resolution TEM (HRTEM) image of the interface between Ge and Si is shown in Figure 1b. The Ge core is single crystalline with a [111] growth direction while the Si shell shows no sign of crystallinity, a completely amorphous structure. As an expected outcome from this two-step growth method, the abrupt interface between Ge and Si is clearly resolved. For comparison, TEM images were also taken from nanowires with a 600 °C shell growth in which all other growth conditions

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were maintained identical to the 470 °C shell growth. A representative TEM image is shown in Figure 1c. The contrast between Ge and Si is still clear. Fringes are observed in both the core and shell areas. The fringes in the shell region are typically large in length and randomly located, which is likely due to the presence of local strain. The fringes in the Ge core are more pronounced at higher magnifications, as shown in the HRTEM image in Figure 1d, and much more periodic. We attribute the observation of these periodic fringes in the Ge core region to the Moire effect,28 which occurs because of the constructive or destructive superposition of the phase shifted electron waves, after passing through crystalline Si shell, crystalline Ge core, and crystalline Si shell again in the energy-filtered TEM mode of HRTEM. Since the direction of the Moire fringes is neither parallel nor perpendicular to the lattice planes, it is clear that both the lattice spacing difference and the orientation shift contribute to this effect. The crystallinity of the shell is implied since the atomic periodicity in both Si and Ge is required for the presence of these fringes. We observed fringe spacings (dark to dark) between 3 and 5 nm from the core of different nanowires, consistent with the spacing of Moire fringes reported for bulk Si/ Ge.28,29 Additionally, as shown in the inset of Figure 1d, the fast Fourier transform (FFT) exhibits two nearby, but distinguishable, signals at each reciprocal location: a brighter one at the outer and a lighter one at the inner portion, as indicated by arrows at the [111] position. The measured reciprocal distance difference is 4.0% between these two signals. We then conclude that the brighter/outer and lighter/inner signals correspond to the Si and Ge, respectively, given the fact that the sampled Si area is larger than the Ge area and lattice constant of Ge is 4% larger than that of Si. The measured angle of 10.8° between [111] of Si and Ge suggests a slight shift orientation between the two crystals, which is consistent with the discussed Moire effect observation. A high degree of abruptness at the Ge/Si core/shell interface is crucial for many applications such as tunneling devices. Previous studies have reported that a Ge/Si interface with an abruptness of approximately 1 nm results in core/shell nanowire grown using this two-step synthesis method.2 Since this method ensures that the SiH4 and GeH4 precursors do not mix, the only possible mechanism available to produce a nonabrupt interface is Si
Ge interdiffusion occurring during the shell growth step. Previous bulk Si
Ge interdiffusion studies reported approximately 10 nm of mixing at 600 °C after five days.30,31 Compared to these studies, the temperatures and time durations used in this work are significantly lower, which should produce negligible interdiffusion at the Si/Ge interface. Thus, an abrupt interface can be expected. Adding dopants during the growth steps will enable nanowire heterostructures with a doped core and/or shell, which will significantly change the band structure, a tool very useful in nanoscale band-structure engineering. Shell doping is achieved by providing a specific dopant gas during the shell growth step. P-, i-, and n-type Si shells were grown by supplying SiH4 together with B2H6 in H2, H2 only, and PH3 in H2, respectively. All other parameters such as total pressure, total flow rate, and SiH4 flow rate were kept identical, and the atomic ratio of supplied dopant atoms to SiH4 was maintained at 1:50 for both p- and n-type shells. Both a-Si shells grown at 470 °C and c-Si shells grown at 600 °C were synthesized for comparison, and for each morphology and doping type two growth runs were carried out. At least 10 randomly sampled wires from each run were measured for statistical confirmation. 1407

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Figure 2. Thickness of a-Si (a) and c-Si (b) shells (with Ge core diameters of 20
30 nm) as a function of growth time. Red squares, black circles, and blue triangles represent p-, i-, and n-Si shells, respectively. The standard deviation is indicated with an error bar. Inset: a-Si (a) and c-Si (b) shell thicknesses as a function of Ge core diameter.

In the range we tested, the measured shell thickness (with Ge core diameters of 20
30 nm) is almost directly proportional to growth time, which indicates a sufficient precursor supply and high degree of reproducibility of the synthesized shell thickness. We observed that the thickness of the shell for a given growth time changes dramatically as a function of dopant type, for both a-Si (Figure 2a) and c-Si (Figure 2b) morphologies. The growth rates are estimated from the slopes of linear fits, resulting in a-Si shell growth rates of ∼18 nm/hour for B2H6 doped p-Si, ∼4 nm/hour for i-Si and ∼1 nm/hour for PH3 doped n-Si. In the case of c-Si shells, the comparative trend between the dopant types still holds: ∼216 nm/hour for p-Si, ∼150 nm/hour for i-Si, and ∼13 nm/hour for n-Si. Such trend is consistent with the wellexplored phenomenon of dopant-induced growth rate change in both thin films and nanowires.32
39 In the boron case, the diborane dopant, acting as a catalyst, reduces the effective activation energy of SiH4 to pyrolyze, resulting in a faster deposition rate, whereas the phosphine dopant inhibits the SiH4 decomposition and blocks surface sites on the Ge core, resulting in a reduced deposition rate. In addition, for the same doping type, the increased growth rate at 600 °C is due to the higher thermal energy. Although the actual kinetics and dynamics of the reaction require a discussion that is beyond the scope of this work, a simple estimate can be provided by considering Arrhenius equation r µ exp(
E/RT), where r is the reaction rate, E is the effective activation energy, R is the gas constant, and T is the temperature in Kelvin. The extracted effective activation energy of SiH4 based on i-Si growth rates is about 36 kcal/mol, which is in good agreement with previous studies on the kinetics of Si deposition by SiH4 pyrolysis.40 Significantly, the small standard

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deviation (σ), indicated by the bars in Figure 2, suggests the realization of well-controlled synthesis and uniformity of the synthesized shells. For all amorphous shells, the typical σ is about 0.7 nm, while the crystalline shells have a typical σ of about 9%. The effect of the core diameter on the thickness of the shell was also studied. To rule out other contributing factors to synthesis, shell growth was carried out on various Ge core diameters using identical growth conditions as stated above. The only difference was the size of Au nanoparticles, which resulted in Ge core diameters ranging from 4 to 40 nm. The measured amorphous and crystalline shell thicknesses for various Ge core diameters are shown in the insets of Figure 2a,b, respectively. The inset of Figure 2a shows that the a-Si shell thickness is virtually independent of the core diameter for core diameters larger than 5 nm. For core diameters smaller than this, a very subtle trend of a slight increase in shell thickness appears to develop. These experimental data points are described well by a normal distribution fit of 7.7 ( 0.7 nm (not shown). The excellent quality of the fit with only a small deviation of 0.7 nm is further evidence of good control over shell thickness and independence of the core diameter. This suggests furthermore that the formation of an a-Si shell on a Ge core under the stated growth conditions is similar to a thin-film deposition with a sufficient precursor supply throughout the duration of the growth process. For c-Si shells, as shown in the inset of Figure 2b, a small diameter dependence was observed. The trend shows that a small increase in the shell growth rate results from a decrease in the size of Ge core, while additional data will be required to confirm this observation. The dopant diffusion is another potential concern in addition to interface abruptness. A diffusion simulation in bulk Si, assuming a P concentration of 5  1019/cm3 at 600 °C for 30 min, shows a diffusion depth of less than 3 Å (see Supporting Information),41 suggesting that the P atoms in the doped Si shell are almost completely immobile under the chosen growth conditions. Therefore, only the dopant atoms that reside in the first one or two atomic layers of the Si shell can provide a source for dopant diffusion into the Ge core. Once across the interface, P diffusion in Ge proceeds much more aggressively than in Si (∼100 nm diffusion length within 10 s assuming a high doping concentration).42,43 As a result, a very light n-type doping may be expected throughout the entire core while an abrupt doping profile remains in close proximity to the interface. Collectively, these results provide necessary insights for this reliable method to synthesize the desired doped shell nanowire heterostructures. To confirm that the electrical properties of the nanowires were consistent with the observed shell morphologies, the electrical behavior of the n-Si shell nanowires was explored by fabricating back-gated NWFETs with Ni contacts, as illustrated in Figure 3a, followed by room temperature characterization. For comparison, two types of Ge core/n-Si shell nanowires were measured: a-Si shell (Figure 3b
d) and c-Si shell (Figure 3e
g) nanowires. Both nanowire structures had typical channel lengths of 3
5 μm, core diameters of 20
30 nm, and shell thicknesses of around 7 nm. A typical transfer characteristic for an n-type a-Si shell NWFET is shown in Figure 3c. Dominant p-type semiconducting transport is observed with a comparatively small electron current contribution at positive Vgs values. Note that negative drain voltages were applied. The output characteristics in Figure 3d show a linear increase in hole current at small Vds, indicating the formation of low resistive contacts to the NWFET device. The stronger p-type behavior can be attributed to the Fermi level lineup of the Ni contacts being closer to the Ge 1408

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Figure 3. (a) Schematic of a back-gated core/shell NWFET. (b) HRTEM image and (c,d) electrical characteristics (at negative Vds) of an n-type a-Si shell nanowire. (e) HRTEM image and (f,g) electrical characteristics (at positive Vds) of an n-type c-Si shell nanowire.

valence band than the conduction band. From the p-branch of characteristics in Figure 3c, the extracted hole mobility is as high as 125 cm2/V 3 s (see Supporting Information). Comparing this value to the higher mobility reported elsewhere,3 we conclude that the suppression of hole mobility is likely due to an additional access resistance associated with contact formation to the a-Si shell between the Ni contacts and Ge channel, and/or an oversimplified gate capacitance estimate used to calculate the mobility. The notion of the Ge core being the primary transport path is an intuitive conclusion here since the a-Si shell may not contribute in any meaningful way to p-branch current flow as it lacks the atomic periodicity and contains a heavy concentration of n-type dopants. Additionally, from the n-branch of Figure 3c, an extracted electron mobility of 4.8  10
2 cm2/V 3 s is consistent with previous reports for heavily n-doped, amorphous Si,44 which further supports the notion of transport occurring primarily through the Ge core as illustrated in Figure 3b. The on/ off ratio of about 3
4 orders of magnitude and rather high off-state current are consistent with a bandgap of around 500 meV, which is close to that of Ge, but inconsistent with the 1.1 eV bandgap of Si. In contrast to the amorphous shell morphology, nanowires with an n-type c-Si shell synthesized at 600 °C show a radical transformation to strong n-type behavior, as shown in Figure 3f,g. The positive slope of the Id
Vgs transfer characteristics provides a definitive n-type conduction signature, and the small gate voltage dependence is evidence of a high doping level in the shell, yielding resistor-like behavior, the deep on-state of a transistor. If we assume current transport occurring primarily in the 7 nm nþ-Si shell, since the source-limited dopant diffusion into the Ge core will likely yield only a light n-type doping in the core region (a point further discussed below), a shell doping concentration in the 4  1019 cm
3 range is extracted.

The extraction is based on resistivity calculations assuming that bulk mobility captures the transport situation in the silicon shell, and by accounting for surface depletion around the circumference of the shell (see Supporting Information). Using the transfer characteristics of Figure 3f, an electron mobility of around 100 cm2/V 3 s is estimated (see Supporting Information), which is in reasonable agreement with the doping level estimate. We conclude that the c-Si shell grown at 600 °C is degenerately doped and highly conductive, serving as the preferred transport path as illustrated in Figure 3e. Although our extracted doping level is still slightly lower than the approximate 8  1019
2  1020 cm
3 doping range necessary to realize optimized tunneling field effect transistor (TFET) devices, further tuning of the doping concentration is still possible. Indeed, doping levels up to the mid 1020 cm
3 range have been achieved in deposited thin films by lowering the total pressure to further enhance dopant incorporation.45,46 Although a strong n-type conduction was observed in the n-type c-Si shell case, we cannot exclude at this point the possibility of the Ge core participating in the transport from source to drain. To further examine this aspect, a unique trimming process, as depicted in Figure 4a
c, was employed on the NWFETs, which consisted of 20
30 nm diameter Ge cores with a shell thickness of ∼7 nm. In this experiment, a PMMA mask was used to protect the source/drain contacts and neighboring portion of the channel, while a 700 nm window was opened in the center of the channel for exposure to subsequent native oxidation/etch processing to remove the n-type c-Si shell in this region. The shell thickness was trimmed down by subjecting it to a series of five native oxide etches in a dilute buffered oxide etchant. Each etch iteration resulted in the removal of ∼1 nm from the Si shell (∼2 nm of native SiO2). A minimum of 2 h was allowed to elapse 1409

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Figure 4. (a) Schematic of a trimmed n-type c-Si shell NWFET. (b) SEM of a post-trimmed NW. (c) SEM image zoom-in at the edge of an etch window. (d) Transfer characteristics of a NWFET before and after the shell trim process. (e) Transfer characteristics of an i-Ge/a-Si core/shell NWFET at positive Vds.

between each etch to ensure full regrowth of the native SiO2 and the etch time was selected to guarantee full removal of the native SiO2. As a result, the total NW diameter reduction in the trimmed region was found to be around 10 ( 1 nm as measured by SEM, indicating a shell thickness reduction of approximately 5 nm. In the trimmed segment of the NWFET channel, only a thin depleted Si shell remains, which passivates the surface of the Ge core. Noticeably, the underlying gate oxide is also etched (darker middle portion of Figure 4b). On the basis of the experimentally tested etch rate and overall etch time, the total etched oxide thickness was ∼19 nm, which is relatively small compared to the original 100 nm thick back-gate oxide. Electrical characterization was carried out on the same device right before and after the trimming process, as shown in Figure 4d. The gate leakage for the pre- and post-trimmed NWFETs was found to be negligible (∼1  10
13 A) throughout the measurement, ensuring the reliability of the data taken. The measurements in Figure 4d were carried out at positive Vds values, as indicated, to allow for an accurate evaluation of n-mode operation in all devices. Comparing the data of pre- and posttrimmed NWFETs, it was found that the on-state current at high positive Vgs is reduced by at least 1 order of magnitude following the trimming process. Further, the ION/IOFF ratio increases from ∼2 to ∼2.5  102 over the same voltage window, a clear transition to a more semiconducting case. These observations confirm that the current is in fact conducting primarily through the shell in the original c-Si shell nanowires. Further analysis of the doping level in the Ge core is carried out by comparing the characteristic features of the post-trimmed c-Si shell NWFET (Figure 4d) and a typical i-Ge/a-Si core/shell NWFET (Figure 4e), both at the identical Vgs, Vds windows. It was found that the on-state current levels in both n-branches (circled) are very similar, in particular when considering deviceto-device variations and the existence of an air gap in the etched region of back-gate oxide underneath the nanowire. As explained previously, almost no dopant diffusion is expected for the a-Si shell NW because of the low growth temperature employed; hence, it is reasonable to conclude that no substantial dopant diffusion has occurred in the c-Si shell NWs. In addition, a shift in threshold voltage (VT) between the post-trimmed c-Si shell NWFET and the i-Ge/a-Si NWFET was observed moving the p-branch outside of the covered gate voltage window. Though doping can certainly result in a VT shift, we believe that this shift is more likely a result of the modified oxide quality through

etching during our trimming process. Indeed, the altered inverse subthreshold slope and higher degree of noise are further indications that the gate oxide quality had been impacted during the etch process. The clear difference in electrical characteristics between the a-Si and c-Si shell NWFETs and the change of device characteristics from the pre- to post-trimmed c-shell NWFETs provide crucial insight into the primary transport path in nanowires with different shell morphologies that is essential for a variety of novel device applications. Additionally, both the fact that dopants in the shell are almost immobile and the comparison between posttrimmed c-Si shell NWFET and i-Ge/a-Si NWFET reveal that the Ge core was not substantially impacted by dopant diffusion during the higher temperature growth process needed to produce the c-Si shell. Furthermore, the dopant diffusion, if any, that does take place across the Ge/c-Si interface yields a rather uniform dopant distribution in the core region because of the fast diffusion of P in Ge. Altogether, this means that dopant diffusion in these nanowire heterostructures does not harm the doping abruptness, therefore does not inhibit their implementation into many of the applications suggested in this work, such as the TFET. In this case, a lightly doped Ge-channel versus an intrinsic one simply translates into a VT shift, but does not alter the tunneling efficiency at the source/channel junction. For applications that cannot tolerate any doping in the core region, a diffusion buffer layer may be considered using a multilayer shell arrangement, such as an n-Si/thin i-Si/i-Ge (shell/shell/core) nanowire. This structure can be realized by implementing a short PH3 gas delay at the beginning of shell synthesis to first grow a 1
2 nm i-Si shell. This i-Si shell acts as a buffer layer, enabling confinement of the dopants to the shell at all growth conditions described in this work. In conclusion, we have demonstrated control of shell morphologies in core/shell nanowires in which the lower temperature will produce nanowires with amorphous shells while higher temperatures will lead to crystalline shells. The observation of Moire fringes in the core region and the FFT of HRTEM images indicate the high quality, crystalline structure of the synthesized Si shells grown at higher temperature. The shell growth rates were found to have a strong dependence on the doping type for a given set of conditions. The small standard deviations in shell thickness suggest a high degree of controllability, repeatability, and reliability of this synthesis method. NWFETs were fabricated and tested to characterize the electrical properties of the 1410

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Nano Letters synthesized nanowires. P-type behavior was observed in n-type a-Si shell nanowires due to dominant Ge core conduction. Conversely, n-type resistor-like behavior was observed for n-type c-Si shell nanowires. Trimming off the shell from the same c-Si shell NWFET led to a clear transition from a highly conductive to a semiconducting behavior, and a reduction of on-state current by 1 order of magnitude. Our results reveal that the shell provides the dominate current path in the c-Si shell NWFETs, and the Ge core in c-Si shell nanowires was not substantially impacted in terms of dopant diffusion by growth at higher temperature. Together with the facts that dopants in the Si shell are almost immobile but diffuse rapidly in the Ge core, the doping abruptness at core shell interface remains
a suitable platform for novel device applications.

’ ASSOCIATED CONTENT

bS

Supporting Information. Additional information and figure. This material is available free of charge via the Internet at http://pubs.acs.org.

’ AUTHOR INFORMATION Corresponding Author

*E-mail: [email protected].

’ ACKNOWLEDGMENT Authors gratefully acknowledge Dr. Eric Stach for insightful discussions on TEM data. This work is supported by NSF GOALI 103822 funding. ’ REFERENCES (1) Li, Y.; Qian, F.; Xiang, J.; Lieber, C. M. Mater. Today 2006, 9 (10), 18–27. (2) Lauhon, L. J.; Gudiksen, M. S.; Wang, C. L.; Lieber, C. M. Nature 2002, 420 (6911), 57–61. (3) Xiang, J.; Lu, W.; Hu, Y. J.; Wu, Y.; Yan, H.; Lieber, C. M. Nature 2006, 441 (7092), 489–493. (4) Liang, G. C.; Xiang, J.; Kharche, N.; Klimeck, G.; Lieber, C. M.; Lundstrom, M. Nano Lett. 2007, 7 (3), 642–646. (5) Zhang, L. N.; He, J.; Zhang, J.; Liu, F.; Fu, Y.; Song, Y.; Zhang, X. IEEE Trans. Electron Devices 2008, 55 (11), 2907–2917. (6) Fu, Y.; Zhang, L. N.; He, J.; Ma, C. Y.; Chen, L.; Xu, Y. W. J. Comput. Theor. Nanosci. 2010, 7 (3), 528–535. (7) Lu, W.; Xiang, J.; Timko, B. P.; Wu, Y.; Lieber, C. M. Proc. Natl. Acad. Sci. U.S.A. 2005, 102 (29), 10046–10051. (8) Musin, R. N.; Wang, X. Q. Phys. Rev. B 2006, 74, 165308. (9) Hu, Y. J.; Churchill, H. O. H.; Reilly, D. J.; Xiang, J.; Lieber, C. M.; Marcus, C. M. Nat. Nanotechnol. 2007, 2 (10), 622–625. (10) Yang, L.; Musin, R. N.; Wang, X. Q.; Chou, M. Y. Phys. Rev. B 2008, 77, 195325. (11) Pekoz, R.; Raty, J. Y. Phys. Rev. B 2009, 80, 155432. (12) Musin, R. N.; Wang, X. Q. Phys. Rev. B 2005, 71, 155318. (13) Goldthorpe, I. A.; Marshall, A. F.; McIntyre, P. C. Nano Lett. 2008, 8 (11), 4081–4086. (14) He, Y. H.; Zhao, Y. N.; Yu, S. M.; Fan, C.; Du, G.; Kang, J. F.; Han, R. Q.; Liu, X. Y. IEEE Int. Electron Devices Meet., Tech. Dig. 2008, 189–192. (15) Goldthorpe, I. A.; Marshall, A. F.; McIntyre, P. C. Nano Lett. 2009, 9 (11), 3715–3719. (16) Park, J. S.; Ryu, B.; Moon, C. Y.; Chang, K. J. Nano Lett. 2010, 10 (1), 116–121. (17) Peng, X. H.; Logan, P. Appl. Phys. Lett. 2010, 96, 143119.

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