Suppressing Segregation in Highly Phosphorus Doped Silicon

Nov 14, 2015 - ... School of Physics, University of New South Wales, Sydney, New South Wales 2052, Australia. ‡ Department of Applied Physics, Eindh...
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Joris G. Keizer,*,† Sebastian Koelling,‡ Paul M. Koenraad,‡ and Michelle Y. Simmons*,† †

Centre for Quantum Computation and Communication Technology, Australian Reseach Council Centre of Excellence, School of Physics, University of New South Wales, Sydney, New South Wales 2052, Australia and ‡Department of Applied Physics, Eindhoven University of Technology, P.O. Box 513, NL-5600 MB Eindhoven, The Netherlands

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Suppressing Segregation in Highly Phosphorus Doped Silicon Monolayers

ABSTRACT Sharply defined dopant profiles and low resistivity

are highly desired qualities in the microelectronic industry, and more recently, in the development of an all epitaxial Si:P based quantum computer. In this work, we use thin (monolayers thick) room temperature grown silicon layers, so-called locking layers, to limit dopant segregation in highly phosphorus doped silicon monolayers. We present secondary ion mass spectroscopy and atom probe tomography measurements that demonstrate the effectiveness of locking layers in suppressing P segregation. Scanning tunneling micrographs of the surface of the locking layer show that the growth is epitaxial, despite the low growth temperature, while magnetotransport measurements reveal a 50% decrease in the active carrier density. We show that applying a finely tuned rapid thermal anneal can restore the active carrier density to 3.4  1014 cm

2

while maintaining ultra sharp dopant profiles. In particular, 75% of the initial deposited P is confined in a layer with a full

width at half-maximum thickness of 1.0 nm and a peak P concentration of 1.2  1021 cm

3

(2.5 atom %).

KEYWORDS: silicon . phosphorus . monolayer . delta-layer . active carrier density . segregation . locking layer . rapid thermal anneal

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s dimensions are pushed beyond the 10 nm scale in silicon microelectronics, abrupt dopant profiles and low resistivity become of crucial importance. The same parameters are also a key element in silicon based spintronic architectures1 and the development of an all epitaxial silicon based quantum computer.2 The Si:P material system is of particular interest with respect to the latter due to its integration with STM lithography for the fabrication of atomic scale devices that can serve as building blocks for a quantum computer.3 The technique involves selectively removing hydrogen from a passivated silicon surface and subsequent dosing with the gaseous precursor phosphine (PH3) followed by low-temperature epitaxy to encapsulate the device. A multitude of devices, e.g., tunnel junctions,4 charge sensors,5 wires,6 single atom transistors,7 and multiple quantum dot devices8 have been fabricated in this way. A high carrier density and an abrupt dopant profile in the growth direction are important for the performance and reproducibility of these devices. Recently, the KEIZER ET AL.

latter has become especially important with the advent of 3D devices.9,10 Traditionally, Si:P delta-layers have been used to study and optimize the dopant profiles within these architectures. Historically, Si:P delta-layers have been fabricated by saturation dosing the silicon surface with gaseous PH3 followed by an anneal to incorporate the P atoms into the surface. An all Si encapsulation layer is then epitaxially grown on top. The maximum achievable active carrier density and 2D sheet resistivity with such a single dose approach is 2.4  1014 cm 2 and 210 Ω 0 1, respectively.11 In the quest for higher active carrier density and lower resistivity, a more elaborate dosing scheme has been devised: the so-called double dose where the silicon surface is dosed twice with an incorporation anneal after each dose. With this recipe, the highest active carrier density (3.6  1014 cm 2, corresponding to 0.53 ML of P) and lowest resistivity (193 Ω 0 1) in a single Si:P delta-layer to date was achieved.12 Stacking of multiple Si:P delta-layers provides another pathway to increase the VOL. XXX

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* Address correspondence to [email protected], [email protected]. Received for review October 6, 2015 and accepted November 14, 2015. Published online 10.1021/acsnano.5b06299 C XXXX American Chemical Society

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RESULTS AND DISCUSSION Growth of Locking Layer. The whole growth process of the double dosed Si:P monolayers and the locking layer is summarized in Figure 1. We first focus on the growth of the locking layer. Figure 2 shows typical scanning tunneling micrographs of the surface after the initial sample preparation and after the growth of a locking layer. No contaminants are observed on the initial surface and the defect density is low, with the only observed defects being the various types of Si vacancies in the surface layer. The room temperature growth of the locking layer results in a roughing of the surface which makes the identification of Si P heterodimers by STM difficult since there is not sufficient brightness contrast between the Si P heterodimer and the surrounding surface. The possible presence of H from the dissociated PH3 after the double dose further frustrates identification. We can however infer from the high ordering of the atoms in the first few layers and the presence of dimer rows in the lower observable layers that the growth is epitaxial. This was found to be the case for the whole range of locking layer thickness. Moreover, in terms of roughness (typical root-mean-square of ≈90 pm) and KEIZER ET AL.

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active carrier density.13 However, we recently showed that when trying to closely stack multiple Si:P deltalayers to maximize the 3D active carrier density (with the ultimate goal of achieving superconductivity in n-type silicon) the active carrier density is limited by segregation of P donors and the subsequent formation of electrically inactive P P dimers.12,14 A well-known and effective technique to reduce segregation of dopants is gas-growth of Si at elevated substrate temperatures (g450 °C).15 18 Unfortunately, the high temperature involved makes this technique incompatible with the hydrogen mask used in fabrication of atomic scale devices; hydrogen desorbs from the surface at ≈415 °C19 resulting in substantial lateral diffusion of P before the start of the encapsulation.20 More recently, another technique which involves an extreme temperature gradient ( 80 f 350 °C) during encapsulation to suppress dopant segregation was proposed.21 Although demonstrated to be effective in suppressing Mn segregation in Si, it is not clear whether this approach will result in the level of dopant activation required for atomic scale device fabrication where we use individual dopants and where a close to 100% dopant activation is needed for these device to function as intended. In this article, we propose another technique to suppress dopant segregation, one that is fully compatible with the current state of hydrogen lithography atomic scale device fabrication and that allows for the close stacking of doped monolayers: thin Si layers are grown at room temperature, so-called locking layers, to suppress P segregation followed by a rapid thermal anneal to obtain a high active carrier density.

Figure 1. Growth of the double dosed Si/P monolayers including a room temperature grown locking layer of variable thickness. An optional rapid thermal anneal (RTA) is applied after the growth of the locking layer. The monolayers are encapsulated with a 30 nm thick all Si layer.

Figure 2. Scanning tunneling micropgraphs of the surface. (Left) Initial surface and (right) after the room temperature growth of a 9 ML thick locking layer. The insets show closeups of single dimer (SD), double dimer (DD), and type C (C) vacancy defects observed in the initial surface.

atomic ordering, the surface is found to be identical for all locking layers used in this study. To determine the effectiveness of the locking layer in suppressing the P segregation, we subjected samples with varying locking layer thickness to SIMS. Note that, the RTA was omitted in these samples. The results are presented in Figure 3a. We find that the P is better confined with increasing locking layer thickness; from the orange (6 ML) to the blue (12 ML) trace, the peak P density increases and the segregation tail in the growth direction decreases. Note that the difference between P profiles of the 9 and 12 ML thick locking layers is small, and that we consider a g 9 ML thick locking layer effective in suppressing P segregation. The APT results presented in Figure 3b will be discussed later. Electrical Characterization. We first turn our attention to the electrical characterization of the samples. The results are summarized in Figure 4, which shows the active carrier density, ns, and the zero field resistance, Fxx (B = 0 T), as a function of the thickness of the locking layer. The maximum active carrier density is achieved in the reference layer (3.6  1014 cm 2), in agreement with previous studies that showed that all the P in the double dosed Si:P monolayer is electrically active.12 The active carrier density shows a downward trend with increasing locking layer thickness, decreasing by a factor of 2.5 to 1.5  1014 cm 2 going from 0 to 12 ML, while the zero field resistance shows an upward trend from 200 to 700 Ω over the same range. VOL. XXX

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Figure 4. Electrical activation of donors. (a) The 2D sheet carrier density, ns (red line) and zero field resistance, Fxx (B = 0 T) (blue line) as a function of the locking layer thickness. The dashed lines mark the change in active carrier density and zero field resistance when including a rapid thermal anneal (RTA) in the growth process. N.B., the number of Si atoms per surface unit is 6.8  1014 cm 2.

The downward trend of the active carrier density can be attributed to the introduction of vacancy defects in the Si crystal that can form a complex with a nearby phosphorus atom (P V) and/or the nonincorporation of phosphorus donors into interstitial sites (P I) during the room temperature growth of the locking layer. In both cases, there are geometrical configurations for which the P V and P I complexes are electrically inactive.22 This will quench the active carrier density as the thickness of the locking layer, and thus, the number of inactive complexes, increases. Rapid Thermal Anneal. It is well known that vacancy and interstitial defects can be repaired by subjecting the material to a thermal anneal.23 However, several aspects need to be considered during this thermal anneal. First, dopants tend to diffuse during annealing and will spatially broaden the layer in which they were originally confined, possibly to such an extent that the initial confinement effect of the locking layer is KEIZER ET AL.

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Figure 3. Phosphorus depth profiling. (a) SIMS results of samples with varying thickness of the locking layer where the rapid thermal anneal (RTA) was omitted. Only a modest increase in the P confinement is observed going from a 9 to a 12 ML thick locking layer. (b) Atom probe tomography (APT) results of samples with a 9 ML thick locking layer without (green line) and with a RTA (orange line).

nullified. Second, dopant diffusion might facilitate the formation of nearest-neighbor P P pairs, which are also electrically inactive.14,24 Third, there may be accumulation of P at the surface as a result of an anneal resulting in further P segregation, and hence spreading out of the dopants, during the growth of the encapsulation layer. Finally, the buildup of P at the surface has been shown to be the limiting factor on the maximum achievable 3D active carrier density in stacked deltalayers.14 Although vacancy and interstitial mediated P diffusion and the annealing of vacancy and interstitial complexes in Si has been extensively studied for bulk,22 26 the results cannot be directly translated to the current situation where we have an ≈9 ML thick doped layer with a surface interface that acts as a sink for vacancy and interstitial defects. This said, there may exist a window of anneal temperature and duration for our system in which the vacancy and interstitial defects are repaired and where P diffusion is negligible. In Figure 5, we present the measured active carrier density of the Si:P monolayers encapsulated with a 9 ML thick locking layer as a function of the rapid thermal anneal parameters. We find that the active carrier density is extremely sensitive to the anneal parameters; the variation in parameter, ns varies in the range of (1.8 3.4)  1014 cm 2 within a window of 65 °C and 20 s. With careful tuning of the RTA (500 °C, 14 s), we are able to almost fully restore the activation to 100%, see the red dashed arrow in Figure 4 and the encircled point in Figure 5a. Deviation from these temperature settings results in a lower active carrier density: a lower temperature and/or duration fails to repair all the vacancy and interstitial defects, whereas a higher temperature and/or duration results in the formation of electrically inactive P P dimers on the surface12 and the desorption of P as PH3 due to the recombination with residual H of the second dose present at the surface.13 The sensitivity of the active carrier density to the temperature and duration (thermal budget) of the RTA can be further illustrated by comparing the scanning tunnneling micrographs of the surface before (Figure 2b) and after the anneal (Figure 5b). We find that the RTA flattens the surface and that the island size increases with increasing thermal budget, due to an increase of mass transport in, and on the surface layer. Atom Probe Tomography. As mentioned before, the phosphorus atoms might diffuse during the RTA. To investigate this, we performed APT, which has a better spatial resolution than SIMS, on samples with a 9 ML thick locking layer. Figure 3b shows the P profile, as obtained by APT, of two samples where one was subjected to a RTA (green line) and one where it was omitted (orange line). The RTA (550 °C, 14 s) has the largest thermal budget of all RTAs and represents a worst case scenario in terms of P diffusion. As with SIMS, the results shows the effectiveness of the locking layer in suppressing the P segregation and that the

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diffuses toward the surface during the anneal and further segregates during the growth of the encapsulation layer. However, the P is still more confined than in the reference sample: 75% of the deposited phosphorus is confined in a layer with a full with at halfmaximum thickness of 1.0 nm and a peak concentration of 1.2  1014 cm 3 (2.5 atom %). Note that this RTA is not the optimized RTA which was found to almost fully restore the active carrier density; the thermal budget of the current RTA is higher. Therefore, it is most likely that the P profile corresponding to the optimized RTA will be more confined. CONCLUSIONS

Figure 5. Impact of rapid thermal anneal. (a) Active carrier density, ns of Si:P monolayers encapsulated with a locking layer as a function of the temperature and duration of the rapid thermal anneal (RTA). The RTA that almost fully restores the active carrier density is encircled by the dashed line. (b) Scanning tunneling micrographs of the surface before and after the RTA for increasing thermal budget.

peak P density is much higher and the segregation tail much less pronounced in the sample with a locking layer than in the reference sample. We find that the application of a RTA reduces the peak P slightly. In addition, the segregation tail is more pronounced in the RTA sample indicating that some fraction of the P

METHODS The Si:P monolayers were grown on Si pieces of 2.5  10 mm . The pieces were cut from an (001) oriented n-type (1 10 Ω 3 cm) wafer. The whole fabrication was done in an ultra high vacuum (UHV) system with a base pressure of ≈10 11 mbar. A clean Si(001) 2  1 surface was obtained by outgassing the samples for several hours, followed by a sequence of high temperature anneals in which the samples were heated to ≈1150 °C. The Si:P monolayers were fabricated by following the double dose recipe12 in which the surface is saturation dosed (1.35 L, chamber pressure of 5  10 9 mbar, 6 min) twice at room temperature with gaseous PH3 with a 550 °C (350 °C) anneal after the first (second) dose to incorporate the P. The temperature of the first incorporation anneal is above the H desorption threshold and opens up new reactive silicon sites to which the PH3 of the second dose can absorb. Note that the surface after the second incorporation anneal is covered with H. After the double dose, the reference layer was encapsulated with 30 nm of Si grown at 250 °C using a sublimation cell with evaporation rates of ≈1 ML min 1. The evaporation rate of the Si sublimation cell was calibrated by atomic force microscopy (AFM); the Si 2

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To summarize, we have shown that room temperature grown silicon locking layers are effective in suppressing the dopant segregation in Si:P monolayers. SIMS demonstrated that a g 9 ML thick locking layer is effective in suppressing P segregation. We found that, due to the formation of electrically inactive P V and/or P I complexes during the growth of the locking layer, the active carrier density decreases. We showed that the vacancy and interstitial defects can be repaired by the application of a RTA, thereby almost fully restoring the active carrier density (3.4  1014 cm 2). APT measurements show that the ultra sharp dopant profile is maintained during the RTA and that 75% of the P is confined in a layer with full width at half-maximum thickness of 1.0 nm and peak concentration of 1.2  1014 cm 3 (2.5 atom %). The dopant confinement and 3D active carrier density of our single Si:P monolayer are the highest reported to date and open up the way for fabricating three-dimensional devices in which dopants are patterned in multiple separate planes. In the long term, we aim to address whether superconductivity can be achieved in high phosphorus doped silicon utilizing this method

pieces are clamped in a holder during fabrication and the height difference between the exposed and covered regions was measured and converted to a growth rate. The sample thickness was later independently confirmed by secondary ion mass spectroscopy (SIMS) measurements. For the other samples, the double dosed surface was overgrown at room temperature with a thin layer, the so-called locking layer, of which the thickness was varied (0 12 ML). Next, the samples are subjected to an optional rapid thermal anneal (RTA) which resistively heats the sample under UHV conditions and is controlled by a proportional-integral-derivative feedback (for more details on the RTA see the Supporting Information). Subsequently, the samples are overgrown with the same 30 nm thick Si encapsulation layer as in the reference samples. At various points in the growth process, the surface was imaged by scanning tunneling microscopy (STM). The whole growth process is summarized in Figure 1. Afterward, the samples were processed into Hall bars for electrical characterization. Pieces of representative samples were subjected to SIMS to determine the P profile along the growth direction and assess the effectiveness of the locking layer. The superior depth resolution of atom probe

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Acknowledgment. This research was supported by the Australian Research Council Centre of Excellence for Quantum Computation and Communication Technology (Project Number CE110001027), the U.S. National Security Agency and the U.S. Army Research Office under contract number W911NF-131-0024. M.Y.S. acknowledges an Australian Research Council Laureate Fellowship. This work was partly financed by The Netherlands Organization for Scientific Research (NWO). Supporting Information Available: The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsnano.5b06299. Details of the rapid thermal anneal (PDF)

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tomography27,28 was used to study the effect of a RTA on the P profile. Conflict of Interest: The authors declare no competing financial interest.

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