Surface state dynamics dictating transport in InAs nanowires - Nano

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Surface state dynamics dictating transport in InAs nanowires David Lynall, Selvakumar V. Nair, David Gutstein, Alexander Shik, Igor Savelyev, Marina Blumin, and Harry E. Ruda Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.7b05106 • Publication Date (Web): 18 Jan 2018 Downloaded from http://pubs.acs.org on January 18, 2018

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Surface state dynamics dictating transport in InAs nanowires David Lynall,∗,†,‡ Selvakumar V. Nair,†,‡ David Gutstein,†,¶ Alexander Shik,†,‡ Igor G. Savelyev,†,‡ Marina Blumin,†,‡ and Harry E. Ruda†,‡,¶,§ †Centre for Advanced Nanotechnology, University of Toronto, 170 College Street, Toronto, Ontario M5S 3E3 ‡Department of Materials Science and Engineering, University of Toronto, 184 College Street, Toronto, Ontario M5S 3E4 ¶Department of Electrical and Computer Engineering, University of Toronto, 10 Kings College Road, Toronto, Ontario M5S 3G4 §Institute of Fundamental and Frontier Sciences, University of Electronic Science and Technology of China, Chengdu 610054, China E-mail: [email protected] Abstract Because of their high aspect ratio, nanostructures are particularly susceptible to effects from surfaces such as slow electron trapping by surface states. However, nonequilibrium trapping dynamics have been largely overlooked when considering transport in nanoelectronic devices. In this study, we demonstrate the profound influence of dynamic trapping processes on transport in InAs nanowires through an investigation of the hysteretic and time-dependent behaviour of the transconductance. We observe large densities (∼ 1013 cm−2 ) of slow surface traps and demonstrate the ability to control and permanently fix their occupation and charge through electrostatic manipulation by the gate potential followed by thermal deactivation by cryogenic cooling.

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The severe impact of electrostatic history and dynamics on the characteristics of an InAs nanowire field-effect transistor is revealed when a transition from enhancementto depletion-mode and a 400% change in field-effect mobility is observed in the same device by varying the initial gate voltage and sweep rate. A time-dependent model for nanowire transconductance based on non-equilibrium carrier population dynamics with thermally activated capture and emission was constructed and showed excellent agreement with experiments, confirming the effects to be a direct result of the dynamics of slow surface traps characterized by thermal activation barriers on the order of hundreds of meV. This work reveals a clear and direct link between the electrical conductivity and the microscopic interactions of charged species with nanowire surfaces and highlights the necessity for considering dynamic properties of surface states in nanoelectronic devices.

Keywords: InAs, nanowire, transistor, hysteresis, trap dynamics, surface state

Introduction The field of nanoelectronics has seen the scaling of device dimensions into the quantum regime, resulting in smaller, faster, high-performance devices as well as the advent of new technologies and physical phenomena. However, as physical dimensions become smaller than electronic screening lengths, the properties of nanostructured materials begin to vary drastically from their bulk counterparts due to the unique properties of the surface. For example, surface states introduce scattering centers that limit the electron mobility in classical nanoelectronic devices and prevent ballistic, phase-coherent transport necessary for quantum nanoelectronic devices. Thus, surfaces and interfaces pose a significant barrier limiting the performance of nanoelectronic devices. On the other hand, the sensitivity of nanostructures to their surface properties can be utilized to probe the surrounding environment. For example, the strong capacitive coupling to charged species on the surface in semiconductor nanowires (NWs) has led to promising applications in catalysis 1,2 and bio-chemical sens2


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ing 3–5 where a molecular binding event at the surface is transduced into an electrical signal by the NW. To best utilize the unique properties of nanostructured electronic materials and their sensitivity to surface interactions, it is necessary to gain an intimate understanding of the interplay between microscopic interactions at the surface and macroscopic properties such as electrical conductivity. An InAs NW provides an excellent system for studying such interactions since transport is dominantly influenced by surface states. 6,7 Additionally, InAs NWs are amongst the most promising candidates for next-generation high-performance field-effect transistors (FETs) 8,9 and thin-film transistors (TFTs), 10,11 future quantum nanoelectronic devices such as spin-orbit qubits 12 and bio-chemical sensors 13–16 owing to their high electron mobility, strong spin-orbit interaction 17,18 and electron confinement effects 19,20 and native accumulation layer of electrons at the surface. 21 In this study, we investigate the non-equilibrium carrier population dynamics and resulting transport properties of InAs NWs by measuring the hysteretic and dynamic behaviour of the NW FET conductance in response to the electric potential provided by the gate. Slow electron trapping due to large densities of surface trap states is found to dominantly influence the transport in our NWs. We construct a model to describe and predict this behaviour based on time-dependent rate equations and thermally activated electron capture and emission processes. The model is applied to experiments on InAs NW FETs where the dynamic conditions and electrostatic history of the device are varied. Simulated and experimental results are presented and discussed. The primary focus of this paper is to investigate the role of trapping dynamics on transport in NWs and demonstrate the necessity and utility for non-equilibrium, time-dependent modelling of carrier populations in low-dimensional semiconductors.

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Results and Discussion InAs NWs were grown by molecular beam epitaxy and had diameters ranging from 20 to 50 nm. To investigate their electrical properties, InAs NWs were configured as the conductive channel in back-gated FETs. Zero-bias differential conductance gate spectroscopy measurements were performed under high vacuum in a liquid helium cryostat. A scanning electron micrograph of a 46 nm diameter InAs NW FET is shown in the inset of Fig. 1a. Experimental results presented in the following sections were acquired from larger diameter InAs NWs (40 to 50 nm). However, reported characteristics of hysteresis and electron trapping phenomena were found to be independent of diameter within the range of 20 to 50 nm for all NWs measured in this study which were produced from the same growth batch. Further details of NW growth, FET fabrication, and electrical characterization are described in the Methods section.

G-Vg hysteresis Hysteresis effects are routinely observed in the G-Vg transconductance measurements of InAs NW FETs. Fig. 1a shows an example of such behaviour where the NW FET conductance G was measured while the gate voltage Vg was swept from 4 V to -4 V (blue) and immediately back to 4 V (red). All NW FETs measured in this study showed qualitatively similar behaviour having lower (higher) conductance measured at negative (positive) dVg /dt. This hysteresis effect occurs as a result of trapping from electron trap states with capture and emission rates similar to the Vg sweep rate. During the decreasing Vg sweep, slow emission of electrons from traps into the conduction band causes faster depletion of free electrons by Vg resulting in a lower free carrier density with respect to equilibrium, i.e., ndn (Vg ) < n0 (Vg ). During the increasing Vg sweep, slow electron capture processes cause faster accumulation of free electrons provided by the gate into the conduction band resulting in a higher free carrier density with respect to the decreasing sweep, i.e., nup (Vg ) > ndn (Vg ). This behaviour can be

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(a)

(b)

𝑉𝑇,𝑢𝑝 𝑉𝑇,𝑑𝑛

(c)

(d) 𝑦 = 0.97𝑥 + 0.44

Figure 1: (a) Room temperature NW conductance G as a function of gate voltage Vg for a 46 nm diameter InAs NW FET. Measurement was started at Vg = 4 V, swept to -4 V (blue), and immediately swept back to 4 V (red) at a constant rate of 27 mV/s. Inset shows a scanning electron micrograph of the same InAs NW FET. (b) Room temperature NW conductance as a function of gate voltage with Vg sweeps performed from 6 → Vmin → 6 V at a rate of 27 mV/s. Solid lines represent initial decreasing sweep, dotted lines represent final increasing sweep and arrows indicate sweep direction. Inset shows hysteresis AH divided by the gate voltage sweep range (6 − Vmin ) as a function of Vmin . (c) Room temperature NW conductance as a function of gate voltage for Vg sweep rates of 3.4 V/s (green), 349 mV/s (magenta), 173 mV/s (blue), 34 mV/s (red), and 3.4 mV/s (black). Solid lines represent initial decreasing sweep, dotted lines represent final increasing sweep and arrows indicate sweep direction. Measurements were performed from fastest to slowest Vg sweeps with approximately 1 hour between measurements with Vg held at 0 V. Inset shows hysteresis AH as a function of Vg sweep rate. (d) NW conductance as a function of gate voltage at T = 10 K for initial gate voltage values from Vi = −4 V (far left) to 4 V (far right) at 1 V increments. Inset shows the threshold voltage VT as a function of Vi with the linear fit VT = 0.97Vi + 0.44 represented by the dotted line.

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seen in Fig. 1a where the threshold voltage on the increasing Vg sweep VT,up is less than that on the decreasing sweep VT,dn . We can estimate the linear free carrier density from VT as

n=

(Vg − VT ) Cox e

(1)

where Cox is the gate oxide capacitance per unit length, R is the NW radius, and L is the NW FET channel length. Since VT,up < VT,dn , we can infer from Eq. 1 that ndn (Vg ) < nup (Vg ), as was the case for all samples measured in this study regardless of the initial Vg sweep direction. To evaluate the hysteresis in our InAs NW FETs quantitatively, the total hysteresis AH was defined as the area between the conductance for increasing (Gup ) and decreasing (Gdn ) R Vg sweeps in the G-Vg curves such that AH = (Gup − Gdn ) dVg . Although the temperature and Vg sweep rate dependence of AH varied from sample to sample, certain reproducible trends were observed in all NW FETs, independent of NW diameter and channel length. For instance, Fig. 1b shows the dependence of AH on the minimum gate voltage of the sweep Vmin . In this experiment, the gate voltage Vg was swept from 6 V to Vmin and back to 6 V for Vmin = 0 → −10 V at -2 V increments at a constant Vg sweep rate. The inset of Fig. 1b shows the hysteresis normalized over the Vg sweep range AH /(6−Vmin ) as a function of Vmin . The normalized hysteresis increased linearly as Vg was swept to more negative values. The increasing hysteresis effect may be attributed to the activation of lower lying deep states in the NW band gap resulting from the Fermi level being pulled relatively further below the conduction band by the gate potential. Fig. 1c shows the room temperature G-Vg characteristics for a NW FET operated in the subthreshold regime (Vg < VT ) at several different Vg sweep rates. The hysteresis AH was found to increase with decreasing sweep rate, as can be seen in the inset of Fig. 1c. This behaviour suggests the existence of deep trap states having time constants on the order of several minutes to hours which is in contrast to the results obtained by Dayeh et al. on locally gated InAs NW FETs where the hysteresis was observed to diminish at slower sweep 6


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rates and was almost completely suppressed at a rate of 6.7 mV/s. 22 This discrepancy can be explained by their use of a ZrO2 /Y2 O3 local gate dielectric and the passivating effects of the deposition on the InAs NW surface. 23 Slow trap states which contribute to the hysteresis effect are believed to originate from the InAs NW native surface oxide which is modified during the ZrO2 /Y2 O3 sputtering process. Thus, contributions from these native oxide surface traps to the hysteresis effect would not be expected in such samples. Furthermore, the SiO2 gate oxide in NW FET devices with similar global back-gate architecture has been shown to provide slow trap states which contribute to the hysteresis effect. 24

Slow traps in InAs NWs An interesting feature of the curves in Fig. 1c is the drift in conductance between measurements. The Vg sweeps were performed from the fastest to slowest sweep rate to avoid activation of slower states. Approximately one hour of recovery time between measurements was allowed with the gate voltage held constant at Vg = 0. The long term drift in conductance indicates the existence of trap states with time constants much larger than the time scale of the measurements. To further investigate, the gate voltage pulse transient response of the NW conductance was measured for accumulating and depleting Vg pulses, examples of which are shown in Fig. S1 of the Supporting Information. The pulse transients had time constants on the order of several hours and had non-exponential time dependence likely due to the convolution of the emission/capture response from trap states having multiple time constants. This is consistent with the results of Astromskas et al. who probed trap states in InAs/HfO2 NW capacitors by deep-level transient spectroscopy (DLTS) and observed a broad distribution of characteristic time constants of trap states when time intervals of the measurements were expanded. 25 The number of InAs NW trap states active within a given time interval was estimated from the gate voltage dependence of the NW FET conductance activation energy, similar to the methodology previously applied for determining the Schottky barrier height of Ni 7


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contacts to InAs NWs. 26 Further details of this method for determining surface state density were reported in a previous study. 27 Conductance activation energies (Ea ) were extracted from Arrhenius plots of ln(G) vs. T −1 at constant values of Vg (see Fig. S2a of the Supporting Information). The spectral distribution of surface trap density Ds was calculated from the dependence of Ea on Vg through the relation Cox Ds (E) = 2 2e πR

"

dE − edVg

−1

# −1

(2)

The spectral distribution of surface states Ds (E) determined by this method shows excellent agreement with the results of Halpern et al. who acquired similar distributions from scanning Kelvin probe measurements on individual InAs NW FETs. 28 All NWs measured had qualitatively similar Ds (E) distributions. The results averaged over all InAs NWs measured in this study can be found in Fig. S2b of the Supporting Information plotted with respect to the scanning Kelvin probe results of Halpern et al. for comparison. The conductance activation energy Ea corresponds to the emission of electrons from a trap level Es over some potential barrier for capture Eb into the conduction band such that Ea ≈ Ec + Eb − E. Directly interpreting this data as the spectral distribution of surface states may be incorrect when considering the non-equilibrium dynamics of traps since it is unlikely that all surface trap states are characterized by the same capture barrier Eb . However, the average trap density active within the time interval of a measurement may be estimated from the linear regime of the Ea -Vg curves. For a 46 nm diameter NW, the average trap density acquired within a time interval of 5 minutes was Ds,f ast ≈ 1.6 × 1012 cm−2 eV−1 , consistent with typical values reported by other groups using C-V measurements 29 and from fitting to I-Vg measurements. 22,30 In the same NW, the average trap density acquired within an expanded time interval of 2 hours was Ds,slow ≈ 4 × 1013 cm−2 eV−1 , 25 times greater than Ds,f ast . The Ea -Vg curves with linear fits can be found in Fig. S3 of the Supporting Information. Such a large disparity in Ds indicates that significantly higher densities of surface trap states with slower time constants exist and demonstrates that the electrical properties of InAs NW 8


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FETs vary drastically depending on the dynamic conditions in which they are measured. Electron capture and emission from slow surface traps was found to demonstrate thermally activated character. Fig. 1d shows several G-Vg curves for the same NW FET acquired for a sequence of thermal cycles from T = 300 K to T = 10 K at various gate potentials. In this experiment, the gate voltage was set to some value Vg = Vi at room temperature until the conductance saturated to a constant value. The NW FET was then cooled down to T = 10 K where the G-Vg characteristics were measured. Interestingly, the threshold voltage VT of the NW FET was found to be directly proportional to Vi such that VT = 0.97 · Vi + 0.44 for Vi values ranging from -4 to 4 V, as depicted in the inset of Fig. 1d, with a negligible amount of hysteresis observed between subsequent gate sweeps. According to Eq. 1, VT is proportional to the change in fixed charge in the NW. Thus, we can conclude that a large majority (∼ 97%) of the surface traps are effectively deactivated and frozen into the charge state distribution set by the gate potential during cool down. To achieve such behaviour, emission/capture barrier heights must be significantly larger than kT which is reasonable given the slow capture and emission time constants observed in experiments. As a result, the threshold voltage is almost entirely determined by the electrostatic history of the NW FET and can be controlled and permanently set by the gate potential and cryogenic cooling. Furthermore, the positive threshold voltage values indicate that surface states in InAs NWs must be comprised of both donor- and acceptor-like defects. The results depicted in Fig. 1 highlight the significant impact non-equilibrium dynamics of surface traps have on the performance and operation of InAs NW FETs. In the following section, we develop a transport model that considers such non-equilibrium phenomena and apply it to describe the behaviour of NW FETs under varying dynamic conditions and electrostatic history.

Time-dependent transport model In a gated NW device with surface traps, the total charge is equal to the sum of free charges in the NW, the fixed charges on the surface and the charge on the gate capacitor. Based on 9


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the condition of charge neutrality, the total charge in the NW Qtot = 0 so that

Qtot = Qf ree + Qf ixed + Qgate = 0

(3)

where Qf ree is the mobile charge consisting of free electrons and holes, i.e., Qf ree = e(p − n), Qf ixed is the fixed charge from ionized acceptors and donors, i.e., Qf ixed = e(ND+ − NA− ) and Qgate is the charge on the NW from the gate potential Vg . These contributions may be described by the equivalent circuit shown in in Fig. 2a where the capacitance of the NW is the so-called quantum capacitance that accounts for the change in potential of the NW corresponding to the change in free carrier density. Then,

Qgate = Cox (Vg − VN W )

(4)

The potential on the NW VN W is equivalent to the change in Fermi level resulting from the applied gate potential Vg such that

VN W =

Ef − Ef 0 e

(5)

where Ef 0 is the Fermi level in the NW when Vg = 0. Thus, Eq. 3 can be rewritten as

n−p−

ND+

+

NA−

Cox Vg + Cox − e

E f − Ef 0 e2

=0

(6)

where n and p are always assumed to be in equilibrium as determined by the Fermi level (see Methods for details). The Fermi level Ef can be determined by solving Eq. 6 given some known distribution of R +/− donor/acceptor-like trap states Ns = 2πR Ds (E)fs (E)dE. In thermal equilibrium, the probability of occupancy of an individual trap state fs having energy Es would be determined h i−1 Es −Ef 1 by Ef such that fs = 1 + 2 exp . However, when considering the dynamic kT properties of surface traps, a self-consistent solution to Eq. 6 with a rate equation describing

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(a)

Rfixed

Cfree

VNW

Cfixed Vg

NW

Cox

Vox

SiO2

(b)

Oxide

InAs NW cn

E

en Eb

x Ea

Ec Ef

Es Figure 2: (a) Simple circuit diagram of the cross section of an InAs NW FET showing the InAs NW (blue region) and the 100 nm SiO2 gate oxide (red region) (b) Energy band diagram of a trap state Es in the native oxide at the InAs NW surface. Eb and Ea represent the capture and emission barrier heights, respectively.

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the evolution of fs (E) with time is required. Since InAs NWs are intrinsically n-type due to pinning of the Fermi level above the conduction band edge at the surface, we can neglect the contribution from holes and write the rate equation for each surface trap as dfs (E) = 2 [1 − fs (E)] cn (E) − fs (E)en (E) dt

(7)

where cn and en are the electron capture and emission rates, respectively. Capture and emission from trap states in InAs NWs has previously been measured by deep level transient spectroscopy 25 and random telegraph noise. 31,32 Slow capture and emission processes are believed to originate from trap states residing in the amorphous native oxide at the InAs NW surface and possibly even the SiO2 gate oxide due to the large activation energies (Eb ∼ 0.1− 1.37 eV) and small capture cross sections (σ0 ∼ 10−17 −10−19 cm2 ) found in these experiments. Additionally, passivation of the NW surface has shown to be effective in suppressing the hysteresis in InAs NW FETs, 24,33 further supporting the claim that slow trapping processes originate from traps at the InAs NW surface and native oxide. Suppression of the G-Vg hysteresis has been observed in our InAs NWs as a result of sulphur-based surface passivation and is to be reported in a later study. Based on these findings, we consider electron trapping processes to occur as a result of emission over an interfacial barrier between the oxide and the InAs NW, similar to the thermionic emission model applied to individual traps in Si MOSFETs. 34 In this model, the trap level Es is assumed to reside in the transition regime of the interface potential. A potential barrier is formed from the superposition of the trap potential and the interface barrier and is depicted in the energy band diagram in Fig. 2b where Eb and Ea = Eb − Es are the barriers for capture and emission, respectively. Under these assumptions, the capture rate for an individual trap can be written as

− (Ec + Eb − Ef ) cn = σ0 vth Nc exp kT

(8)

where σ0 is the capture cross section of the trap, vth is the electron thermal velocity, and

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Nc is the effective conduction band density of states. The emission rate en is obtained by E −E applying the condition of detailed balance ecnn = exp skT f which gives

− (Ec + Eb − Es ) en = σ0 vth Nc exp kT

(9)

Substituting Eq. 8 and Eq. 9 into Eq. 7 and defining γ = σ0 vth Nc , the rate equation for a trap in InAs NWs becomes

dfs (E) − (Ec + Eb − Ef ) − (Ec + Eb − Es ) = 2γ [1 − fs (E)] exp − γfs (E) exp dt kT kT

(10)

We note that other authors studying individual traps in InAs NWs through random telegraph noise applied a multi-phonon emission model to describe electron capture and emission processes from individual surface traps. 31,32 This picture is consistent with our model where Eb and Ea are representative of the lattice distortion energy required to transition between the free and bound state. In either case, electron capture and emission processes require thermal activation over some potential barrier characteristic of the trap state. Typical surfaces do not consist of only one individual trap level but are characterized by many trap states distributed over energy according to some density distribution function Ds (E). Given Ds (E), the distribution can be discretized into individual trap levels Ds (Es ) with a rate equation associated with each level Es . Then, Ef and the non-equilibrium distribution of surface traps fs (Es ) may be found by numerically solving Eq. 6 self-consistently with Eq. 10. In InAs NWs, electron mobility is limited by coulomb scattering from charged surface states. 6,27 Therefore, electron mobility µ will scale in inverse proportion to the number of scattering centers µ ∝ (ND+ + NA− )−1 so that the NW conductance G scales as

G ∼ nµ ∼

ND+

n + αNA−

(11)

where ND+ and NA− are the ionized donor and acceptor densities and α is a factor representing 13


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the proportional scattering strength between repulsive (acceptors) and attractive (donors) coulomb centers. For similar diameter InAs NWs, calculations based on single coulomb centers at the NW surface give α ≈ 30. 35 Axial variation of the NW potential due to the gate, source and drain contacts may also affect the NW conductance, especially at large positive gate voltages. To account for this effect, we include a constant series resistance in our model as a fitting parameter. We note that a more sophisticated treatment of the electron mobility and axial dependence of the NW potential is necessary to determine the magnitude of the conductance. However, the simplicity of this model enables fast simulations of qualitative trends in the G-Vg characteristics of InAs NW FETs allowing us to investigate the influence of surface trap dynamics on transport as well as the properties of surface traps themselves.

Modelling NW FET G-Vg characteristics To test the model, G-Vg transconductance measurements were performed on a 46 nm diameter InAs NW FET with varying Vg sweep rate and electrostatic history. The electrostatic history was set by holding the gate voltage constant at Vg = Vi for approximately 48 hours prior to the measurement. Measurements were repeated for Vi values of -4 V and 6 V at Vg sweep rates of 270 mV/s, 27 mV/s, and 44 µV/s. The results are shown in Fig. 3a. For the faster sweep rates of 270 mV/s and 27 mV/s, the G-Vg characteristics of the InAs NW FET changed drastically, switching operation from depletion-mode (VT < 0) when Vi = −4 V to enhancement-mode (VT > 0) when Vi = 6 V. This behaviour indicates that slow trap states which were given sufficient time to equilibrate at Vg = Vi are inactive on the time scale of the measurement, unable to respond to the relatively quickly varying gate potential. As a result, the threshold voltage of the device strongly depends on the electrostatic history. For the slow sweep rate of 44 µV/s, the peak field-effect mobility µF E was found to be suppressed by 400% from the 270 mV/s sweep with the G-Vg curve nearly intersecting the equilibrium starting point of the Vi = −4 V curves. Such a significant change in the NW FET characteristics 14


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indicates that surface trap states which were inactive during the faster sweeps have sufficient time to respond to the slowly varying gate potential, leading to an effectively higher density of active surface traps in the NW for the slow gate sweep (Ds,f ast < Ds,slow ). The suppression of the peak field-effect mobility results from the significant change in trapped surface charge ∆Qf ixed by the gate voltage and the proportional overestimate of the change in free carrier density ∆n assumed by the linear capacitance model. When surface trap densities are large such that ∆Qf ixed ∼ ∆n, the field-effect mobility µF E ∼ Cg−1 (dG/dVg ) becomes a significant underestimate of the electron mobility µe . 36 Nevertheless, the field-effect mobility is characteristic of FET operation and an important figure of merit for benchmarking transistor performance and operation. This experiment demonstrates that transport in InAs NW FETs is indeed far from equilibrium and a time-dependent model that considers non-equilibrium trapping dynamics is necessary to explain and predict the G-Vg characteristics. To obtain a self-consistent solution for the Fermi level Ef and surface trap occupation fs , Eq. 6 and Eq. 10 must be solved numerically with a known distribution of surface trap states Ds (E) and emission barrier heights Ea . Average trap densities of Ds,f ast = 1.6 × 1012 cm−2 and Ds,total = 4 × 1013 cm−2 were found from the gate voltage dependence of conductance activation energy (Eq. 2) for time scales corresponding to Vg sweep rates of 27 mV/s and 44 µV/s, respectively. For capture and emission rates to be responsive on these time scales, emission barrier heights Ea = 0 (fast) and 700 meV (slow) are required with γ = 106 s−1 based on experimental values of capture cross-sections for InAs NW surface traps (σ0 ∼ 10−18 cm2 ). 25,31 InAs surfaces are known to be comprised of donor-like surface states associated with filled As dangling bonds near the valence band maximum and acceptor-like surface states associated with unfilled In dangling bonds well above the conduction band minimum. 37,38 In our model, surface trap states are represented by Gaussian distributions having standard deviations of 200 meV located 400 meV above (acceptors) and 300 meV below (donors) the conduction band minimum. 39,40 Inclusion of both donors and acceptors is necessary as the positive threshold voltages observed in experiment could not occur without acceptor-like

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(a)

Experiment

(b)

Model

(c)

Figure 3: (a) Experimental and (b) simulated NW conductance G as a function of gate voltage Vg with initial gate voltage Vi = 6 V and Vg sweep rates of 270 mV/s (black), 27 mV/s (red), and 44 µV/s (blue) and with Vi = -4 V and sweep rates of 27 mV/s (magenta) and 270 mV/s (green). Dotted lines represent increasing Vg sweep rate. (c) Calculated Fermi level Ef relative to the conduction band edge as a function of gate voltage. Dashed line represents equilibrium Ef . The red and black lines in (b) and (c) are nearly overlapping, red being slightly to the left of black.

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surface states. Acceptor and donor distributions are composed of a superposition of fast (Ds,f ast = 1.6 × 1012 cm−2 , Ea = 0 meV) and slow (Ds,slow = Ds,total − Ds,f ast = 3.84 × 1013 cm−2 , Ea = 700 meV) trap states based on our experimental values. The simulated G-Vg transconductance curves are shown in Fig. 3b. The model shows excellent agreement with experiment, demonstrating the same transition of FET operation from depletion- to enhancement-mode depending on the electrostatic history Vi as well as the strong dependence of the field-effect mobility µF E , threshold voltage VT and hysteresis AH on the Vg sweep rate. The simulated transfer curves for Vi = 6 V, 270 mV/s (black) and 27 mV/s (red) show less hysteresis than that observed in experiment. Fig. S4 of the Supporting Information shows results for the same simulation performed using an exponential distribution of Ea rather than a single value and demonstrates a greater amount of hysteresis for the same transfer curves. The inclusion of trap states with lower emission barrier heights enables capture and emission processes by deep trap states in the band gap to be activated during the depleting gate voltage sweeps when the Fermi level resides far below the conduction band minimum. Although it is reasonable to assume surface trap states exist with varying emission barrier heights, more knowledge of the composition and properties of InAs NW surfaces and native surface oxides are necessary to determine such distributions. The calculated Fermi level Ef in the NW relative to the conduction band edge is shown in Fig. 3c with the equilibrium Fermi level position represented by the dashed line. The position of the calculated Fermi level in the NW varies significantly from the equilibrium value indicating that characteristics produced from this simulation could not have been realized with an equilibrium model. Simulations of the G-Vg characteristics were performed for the same NW FET with the gate voltage swept from equilibrium at Vg = 0 V to -4 V and back to 0 V at rates ranging from 1.33 mV/s to 1330 mV/s. The results are shown in Fig. 4a and agree well with the experimental results presented in Fig. 1c, where the hysteresis AH was found to increase significantly for slower sweep rates with qualitatively similar G-Vg characteristics. Fig. 4b

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(a)

(c)

(b)

Figure 4: Simulated NW (a) conductance and (b) Fermi level vs. gate voltage at various Vg sweep rates. Solid lines represent the initial decreasing Vg sweep and dotted lines represent the final increasing Vg sweep. The inset shows the hysteresis AH as a function of Vg sweep rate. (c) Simulated NW conductance as a function of gate voltage swept from (Vi − 2) to 4 V at T = 10 K for Vi values from -4 V (far left) to 4 V (far right) at 1 V increments. Inset shows the threshold voltage VT as a function of Vi with the linear fit VT = 0.92Vi − 0.7 represented by the dotted line.

shows the calculated Fermi level Ef dependence on gate voltage. Interestingly, the Fermi level remains far from equilibrium even at the slowest sweep rate of 1.33 mV/s. Fig. 4c shows the simulated G-Vg characteristics at T = 10 K for initial room temperature gate voltage values ranging from Vi = -4 V to 4 V at 1 V increments, similar to the experiment depicted in Fig. 1d. For this simulation, equilibrium conditions were set at T = 300 K and Vg = Vi . For each value of Vi , the G-Vg characteristics were simulated at T = 10 K for Vg sweeps from (Vi − 2) to 4 V at 27 mV/s. The same linear dependence of the threshold voltage VT with the initial equilibrium gate voltage Vi seen in experiment was observed with a slope of 0.92 obtained from a linear fit to the VT -Vi data, indicating thermal deactivation of trap states and further validating the assumptions of our model.

Conclusions We have demonstrated the significant role of non-equilibrium surface trapping dynamics on the electronic transport properties of InAs NWs. Key FET characteristics such as threshold voltage, field-effect mobility, and the G-Vg hysteresis showed a strong dependence on the Vg

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sweep rate and history. This behaviour was attributed to the presence of surface trap state densities measured on the order of ∼ 1013 cm−2 and characterized by multiple capture and emission time constants ranging from seconds to several hours. Surface traps demonstrated thermally activated character which was observed through cycles of the thermal deactivation of traps from cryogenic cooling after electrostatic manipulation of the occupation and charge state by the gate potential at room temperature. The nearly one-to-one linear dependence of threshold voltage with the initial cool down voltage Vi revealed that a significant majority of surface traps are characterized by large thermal activation barriers on the order of hundreds of meV and have a drastic effect on the NW G-Vg characteristics. Our results showed that operation of InAs NW FETs occurs so far from equilibrium that the same device may operate in depletion- or enhancement-mode depending on its electrostatic history and the field-effect mobility showed a strong dependence on the dynamics of the gate potential, varying by up to 400% for different Vg sweep rates. These experimental results were quantitatively analysed and systematically correlated with surface trap dynamics through a time-dependent model considering thermally activated capture and emission processes from traps states. The model showed excellent agreement with our experimental data, revealing the crucial role of nonequilibrium trapping dynamics in dictating transport in InAs NWs. As a result, we learned that key FET parameters such as threshold voltage and field-effect mobility are largely determined by the dynamics and history of the device and consideration of these properties is necessary to obtain accurate and reliable information from the system. By explaining and successfully modelling the hysteretic and time-dependent behaviour of the transconductance in InAs NWs, this work exposes a clear and direct link between the microscopic processes at the surface and macroscopic electrical conductivity which may be easily measured. Applying a similar methodology to other nanostructured materials is necessary for the development of future nanoelectronic devices. For example, similar dynamic analysis of transconductance combined with a non-equilibrium carrier population model with thermally activated capture and emission from molecular adsorption events may

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be used to investigate new paradigms for selectivity in nanostructure-based bio-chemical sensors. Furthermore, the ability to manipulate and deactivate surface traps in InAs NWs through the gate voltage and subsequent temperature cool down could provide a means of quenching quantum interference effects and phase de-cohering scattering events leading to ballistic transport necessary for quantum nanoelectronic devices operated at cryogenic temperatures.

Methods Growth of NWs Growth of InAs NWs was performed using a SemiTeq model STE75 solid source molecular beam epitaxy system produced by SemiTeq. InAs NWs were grown on GaAs (111)b substrates by a gold-catalysed vapour-liquid-solid (VLS) technique. The NWs had diameters ranging from approximately 20 to 50 nm and lengths of 8 to 10 um. High-resolution transmission electron microscopy revealed NWs to be single crystalline with wurtzite crystal structure and virtually free of stacking faults. Further details of NW growth are reported elsewhere. 41

FET fabrication InAs NWs were mechanically transferred to a thermally oxidized p++ silicon substrate with 100 nm of SiO2 serving as the global back-gate dielectric. Electrodes were patterned by electron beam lithography with an average separation of 1.6 µm between the source and drain. For ohmic contact formation, the substrates were dipped in a (NH4 )2 Sx solution (0.3% in H2 O by volume) for 7 minutes immediately prior to deposition of Ti(15 nm)/Au(120 nm) electrodes in a hybrid electron-beam/thermal evaporation system. After lift-off, the samples were cleaned and mounted in a 28-pin PLCC chip carrier by indium bonding. The samples were then cleaned in an NMP based resist stripper at 60o C for 60 minutes, followed by a 20


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thorough rinse in acetone, isopropanol, and deionized water.

Electrical characterization All conductance measurements were performed in a closed cycle liquid helium cryostat under high vacuum for temperatures ranging from 10 to 300 K. The NW AC differential conductance was measured using a low noise current pre-amp with dual lock-in amplifiers. An AC bias of ∂VDS = 1 mV was used and the NW conductance was determined from the resulting AC current ∂IDS measured at the pre-amp such that G = ∂IDS /∂VDS . The DC gate voltage Vg was provided by a DC voltage source from a Keithley 4200 Semiconductor Characterization System. The gate oxide capacitance was estimated from the analytical expression for a metallic cylinder on a plate Cox = 2π0 ef f /arccosh((tox + R)/R) where tox is the SiO2 thickness (100 nm). An effective dielectric constant of ef f = 2.12 was used based on our particular NW FET geometry. 42

Numerical modelling Each defect band with a Gaussian energy distribution was discretized into 100 equally spaced points in energy with a rate equation (Eq. 10) describing the population dynamics in each of those levels. These equations coupled with Eq. 6, that determines the Fermi level, form a system of algebraic differential equations that must be solved self-consistently. Because of exponential dependence of the capture and emission rates on energies and temperature, the dynamics involve rates ranging over several orders of magnitude making the system of equations very stiff. To avoid numerical instabilities and exceptionally small time steps required to solve such equations, we integrate the rate equations analytically by continuously linearising around the current estimate of Ef . This is done during the iteration cycle of solving for Ef as the root of Eq. 6 and iterated to self-consistency. The resulting algorithm is efficient and converges fast as long as the the change in Ef per time step is kept small compared to kT . To simulate a typical sweep at 300 K with a gate voltage swing of 10 V, 21


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only about 1000 time steps are required. The free electron and hole densities n and p appearing in Eq. 6 are determined by the density of states and the Fermi level. In particular, for electrons, we include quantized 1-D q P ∗ subbands so that n = 8πmh2e kT n F−1/2 [(Ef − En ) /kT ] and for holes we use the bulk 3-D 3/2 ∗ density of states giving p = 2πR2 2πmh2v kT F1/2 [(Ev − Ef ) /kT ] where m∗e is the effective mass of the electron, m∗v is the average density-of-states mass of the valence band, Ev is the energy of the top of the valence band, and En is the energy of n-th subband calculated using hard-walled confinement in a cylindrical InAs NW of radius R = 23 nm including non-parabolicity within the Kane Model. 35 Fj ’s are the Fermi-Dirac integrals of order j. All energies are measured relative to the bottom of the conduction band in bulk InAs and temperature dependence of the band gap is included.

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Acknowledgements The authors gratefully acknowledge financial support from Defence Research and Development Canada (DRDC), the National Sciences and Engineering Research Council of Canada (NSERC), and the Ontario Centres of Excellence (OCE). Additional Information The authors declare no competing financial interests. Supplementary information accompanies this paper and includes data for the gate voltage pulse transient response of the conductance of an InAs NW FET and further details and data regarding surface trap density calculations and temperature dependent G-Vg simulations and measurements. Correspondence and requests for materials should be addressed to D.L.

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(41) Kavanagh, K. L. , Salfi, J., Savelyev, I., Blumin, M. & Ruda, H. E. Transport and strain relaxation in wurtzite InAsGaAs core-shell heterowires. Appl. Phys. Lett. 98, 152103 (2011) (42) Wunnicke, O. Gate capacitance of back-gated nanowire field-effect transistors. Appl. Phys. Lett. 89, 083102 (2006)

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Fast Slow

Eb Ec

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Surface state dynamics dictating transport in InAs nanowires - Nano

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