Letter pubs.acs.org/NanoLett
Thermally Assisted Nonvolatile Memory in Monolayer MoS2 Transistors G. He,† H. Ramamoorthy,† C.-P. Kwan,‡ Y.-H. Lee,† J. Nathawat,† R. Somphonsane,§ M. Matsunaga,∥ A. Higuchi,∥ T. Yamanaka,∥ N. Aoki,∥ Y. Gong,⊥ X. Zhang,⊥ R. Vajtai,⊥ P. M. Ajayan,⊥ and J. P. Bird*,†,∥ †
Department of Electrical Engineering, University at Buffalo, The State University of New York, Buffalo, New York 14260-1900, United States ‡ Department of Physics, University at Buffalo, The State University of New York, Buffalo, New York 14260-1500, United States § Department of Physics, King Mongkut’s Institute of Technology Ladkrabang, Bangkok 10520, Thailand ∥ Graduate School of Advanced Integration Science, Chiba University, 1-33 Yayoi-cho, Inage-ku, Chiba 263-8522, Japan ⊥ Department of Materials Science and NanoEngineering, Rice University, Houston, Texas 77005, United States S Supporting Information *
ABSTRACT: We demonstrate a novel form of thermally-assisted hysteresis in the transfer curves of monolayer MoS2 FETs, characterized by the appearance of a large gate-voltage window and distinct current levels that differ by a factor of ∼102. The hysteresis emerges for temperatures in excess of 400 K and, from studies in which the gate-voltage sweep parameters are varied, appears to be related to charge injection into the SiO2 gate dielectric. The thermally-assisted memory is strongly suppressed in equivalent measurements performed on bilayer transistors, suggesting that weak screening in the monolayer system plays a vital role in generating its strongly sensitive response to the chargeinjection process. By exploiting the full features of the hysteretic transfer curves, programmable memory operation is demonstrated. The essential principles demonstrated here point the way to a new class of thermally assisted memories based on atomically thin two-dimensional semiconductors. KEYWORDS: Molybdenum disulfide, thermally-assisted memory, nonvolatile memory, electrical hysteresis
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hermally-assisted memories1 represent an emerging area of nanotechnology in which locally generated heating is exploited to ease the switching between different, nonvolatile memory states. In heat-assisted magnetic recording2 (or HAMR), for example, a laser beam is focused onto the surface of a high-density magnetic disk, locally lowering the coercivity and, thus, the magnetic field required to achieve bit programming. Other examples of technologies that make use of thermally-assisted processes include phase-change memories,3 memristors,4 and thermally assisted magnetic RAM.5 While these different memories vary widely in terms of their implementation, the benefits of thermally-assisted switching generally include high scalability, good thermal stability, and low-power programming. To return to the case of HAMR, for example, the development of mature technologies based on this approach is eventually expected to increase the storage capacity of hard disks by a factor of a hundred over existing technology.2 Recently, there has been enormous interest in the potential applications of two-dimensional (2D) transition-metal dichalcogenides, in various post-CMOS logic and memory schemes.6 Prominent among such materials is molybdenum disulfide (MoS2), which has been shown6 to exhibit efficient switching when used as the channel of a field-effect transistor (FET). A drawback of these (and other 2D) devices, however, is that they are often plagued by hysteretic7−19 gate operation. Among the © XXXX American Chemical Society
sources of hysteresis that have been identified in MoS2, ambient water and oxygen adsorption,13−15,18 charging of interfacial states,16 and electron trapping in the gate oxide,19 each have been separately emphasized. While hysteresis is typically considered undesirable for device performance, recent work has sought 20−23 to exploit it for nonvolatile-memory applications. Examples include graphene/MoS2 floating-gate memories,20,21 and memristors based upon the driven motion of MoS2 grain boundaries.23 In this Letter we demonstrate very different functionality, reporting a novel form of thermallyassisted memory in monolayer MoS2 FETs. When heated to temperatures in excess of 400 K the transfer curves of these devices develop pronounced hysteresis, characterized by a large gate-voltage window and distinct current levels that differ by a factor of ∼102. This nonvolatile functionality is attributed to a thermally assisted charging process in which charging/ discharging of the gate oxide generates large changes in the current flowing through the nearby ultrathin MoS2 channel. The thermally assisted memory is found to be strongly suppressed in equivalent measurements performed on bilayer MoS2 devices, suggesting that weak screening in the monolayer Received: July 13, 2016 Revised: September 21, 2016
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DOI: 10.1021/acs.nanolett.6b02905 Nano Lett. XXXX, XXX, XXX−XXX
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Figure 1. (a) Main panel shows transfer curves (Id(Vg)) from 200−500 K. Both gate-sweep directions are plotted. The measurements used a drain voltage Vd = 0.5 V and a gate-voltage sweep rate of 0.5 V/s. The pronounced current jump seen at higher temperatures occurs when sweeping gate voltage up from −40 V. The left inset is an optical micrograph of the device in which the black dotted line indicates the geometry of the MoS2 crystal. The two-probe measurements were made in the geometry indicated (for which the channel length was 4 μm). The right inset plots the 490 K data from the main panel to allow the hysteresis to be more-clearly seen. The measurement starts at Vg = −40 V and sweeps up (red) to Vg = +80 V, before returning back (blue) to Vg = −40 V. (b) The main panel plots ∂Id/∂Vg computed from the up-sweep data of (a). The inset shows the data of the right inset of that figure, with current on a logarithmic scale. (c) Key steps in the hysteresis process. In each panel the blue region indicates the filling of electron states in the gate, the red symbols denote states in the 2D MoS2 bands, and the intervening layer corresponds to the gate oxide. The variable shading in this layer indicates schematically a band of intermediate levels. Panel (1): tunneling into the gate oxide for large negative gate bias. Panel (2): Releasing gate charge at small positive Vg. Panel (3): Tunneling from MoS2 into interface states/gate oxide under positive gate bias.
and atomic-force microscopy.25 The heavily n-type Si substrate served as the transistor back-gate, with the gate dielectric provided by the 280 nm thick SiO2.25 Multiple transistors, with geometries such as that shown in the left inset to Figure 1a, were fabricated, and the characteristics of three of these were investigated in detail: two were measured in Buffalo, while a third was studied in Chiba, and all yielded very similar results. Results presented in this Letter should therefore be viewed as representing the typical behavior found in our studies. Fabricated devices were mounted in a ceramic DIP package, following which they were installed in the vacuum chamber of a variable-temperature system. All measurements were performed after first pumping this system to a vacuum of ∼10−6 mbar and then holding it at that base pressure. This allowed adsorbed water and oxygen to be eliminated16 as the source of the hysteretic behavior reported here. To reproducibly investigate the characteristics of the devices, each of them was subjected to an annealing treatment in which, after being mounted in the cryostat, they were first heated to ∼500 K and maintained at this temperature for several hours. This was found to stabilize the electrical characteristics, yielding consistent behavior across
system is vital to its strong sensitivity to the charge injection. The robust hysteresis in the monolayer system is furthermore shown to support programmable memory operation in which the state of the memory is deterministically controlled by means of the gate-voltage biasing history. While the FETs investigated here are by no means optimized for ultimate applications, the temperature (∼400 K) required to activate the nonvolatile memory is comparable to that which can be achieved locally, on-chip, during regular FET operation. This suggests the possibility of realizing compact memory technology that functions overall at ambient temperature, and which is comprised of one-transistor memory cells. In each such cell, the same MoS2 FET may be used to produce the locally increased temperature required for memory action and to realize the memory storage itself. The triangular-shaped, monolayer MoS2 crystals (see Figure 1(a), left inset) used in this study were grown on commercial Si/SiO2 wafers by chemical vapor deposition (CVD) (for further details see refs 24 and 25). This yielded triangularshaped single crystals, a few tens of microns on a side, whose monolayer character was confirmed by Raman spectroscopy B
DOI: 10.1021/acs.nanolett.6b02905 Nano Lett. XXXX, XXX, XXX−XXX
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should therefore involve a distinct mechanism from those discussed above. As indicated in the right inset of Figure 1a, at the highest temperatures studied, the hysteresis is dominated by a pronounced step-like change in drain current (Id) that occurs when sweeping the gate voltage upward from an initial negative value. In the inset of Figure 1b we replot the data from Figure 1a on a semilog scale, revealing that the hysteresis is actually defined by the presence of two discrete current jumps, one of which is associated with each sweep direction. These two discontinuities are separated by a large gate-voltage window of ∼40 V, and both exhibit a current change by a factor of ∼102. A useful method for studying the high-temperature hysteresis involves inspecting the form of its transconductance (∂Id/∂Vg, at fixed drain voltage Vd). Most notably, the step-like change of current observed when sweeping up the gate voltage produces a distinct transconductance peak, whose temperature dependence is indicated systematically in Figure 1b. Here it is clear how the current step, and so the associated hysteresis, emerges when the temperature is increased beyond 360 K. In the discussion that follows, we present a systematic study that attributes this hightemperature memory effect to charging processes involving carrier exchange between the different components of the device (gate, oxide, and MoS2 channel, see Figure 1c). The connection of the hysteresis to carrier injection from the gate is established in Figure 2. In Figure 2a, we show how the hysteresis is influenced by varying the initial point (Vgstart) of the gate-voltage sweep. In the main panel we see that with Vgstart = −10 V there is essentially no hysteresis in the transfer curves. As Vgstart is made more negative, however, the hysteresis emerges. Consistent with this, in the inset to the figure we plot the transconductance (for the up sweeps) obtained while incrementing Vgstart in a more systematic manner. Two trends are apparent here, the first of which is that the amplitude of the transconductance peak grows steadily as Vgstart is made more negative. The second is a clear shift of this peak to more positive gate voltage as Vgstart becomes more negative. Most notably, the peak occurs well-beyond zero gate voltage, indicating that the current jump does not26,27 somehow provide a “memory” of the sample having been held at this voltage between successive measurements. Rather, the indication of Figure 2a is that the hysteresis is caused by biasing the transistor at negative gate voltage. Further evidence for this is provided in Figures 2b,c. In Figure 2b, we demonstrate the influence of holding the device at various fixed voltages (Vghold) for 24 h, prior to the same upward gate-voltage sweep. These data show that making Vghold more negative shifts the transconductance peak to more positive gate voltage, in accordance with Figure 2a. Similarly, in Figure 2c we show the result of holding the device at a fixed Vghold of −30 V, for different times prior to initiating the measurement (between Vg = −40 V and +60 V); holding at negative voltage for longer time again shifts the current jump (and its transconductance peak) to more-positive gate voltage. The observed hysteresis implies a dynamic character to the transistor current, and in Figure 3a, we explore the origins of this by measuring sweep-rate-dependent transfer curves. Varying this rate by a factor of 500, an intriguing trend is observed; while the current jump observed for increasing gate voltage becomes slightly more prominent as the sweep speed is reduced, a significant decrease in overall current level is observed for the down sweep. This suggests the presence of very different time scales for different ranges of the hysteresis curve, an idea we explore in Figure 3b. This plots the results of an experiment in which we stop the down sweep at some
different heating cycles and devices, with no noticeable degradation of the SiO2 dielectric. In measurements (see Figures 2−4, for example) in which the dependence of the
Figure 2. (a) Main panel shows transfer curves measured at four different start voltages (Vgstart). The gate voltage was swept at a rate of 0.5 V/s and the inset shows corresponding transconductance curves (up sweeps only) for a more-systematic variation of Vgstart. (b) In each experiment the device was held at fixed Vghold (varied from 0 to −30 V) for 24 h prior to beginning the gate-voltage sweep. For clarity, only sweep-up data are shown, and the corresponding transconductance obtained from these results is plotted in the inset. (c) Influence of hold time. Each measurement was performed for Vghold = −30 V, while varying the hold time at this voltage from 0−10 h. Following this, the gate voltage was swept between −40 and 60 V. The temperature was held at 490 K in the measurements of panels (a)−(c).
hysteresis on different sweep parameters was investigated, a systematic “device reset” was implemented to ensure that any specific measurement was not influenced by prior history. This involved returning the gate voltage (Vg) back to zero at the end of any measurement, and then holding it at that condition (and temperature) for 24 h. The thermally-activated hysteresis of interest here is demonstrated in the main panel of Figure 1a, which plots the transfer curves of a representative MoS2 FET over the temperature range from 200−500 K. Curves for both gatesweep directions are plotted and are essentially indistinguishable from one another below ∼300 K. From 300−360 K weak hysteresis emerges in the data, reminiscent of recent reports on the influence of interfacial-state charging.16 Our interest here is in the data obtained at higher temperatures (T > 360 K), where a pronounced and completely different form of hysteresis is observed. Such behavior has not been reported previously and C
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Figure 4. (a) Main panel plots transfer curves measured at 498 K, after holding the device under various gate-bias conditions (indicated). In the left inset we show how these curves may be collapsed onto a common variation through the introduction of an appropriate gatevoltage shift (ΔVT). The right inset plots the variation of ΔVT as a function of hold time, for a fixed holding gate voltage Vghold = −30 V. (b) The main panel plots transfer curves measured at 498 K, for several different values of Vgstart (indicated). In the left inset we show how these curves may be collapsed onto a common variation through the introduction of an appropriate gate-voltage shift (ΔVT). The right inset plots the variation of ΔVT as a function of Vgstart.
Figure 3. (a) Measurements of the hysteresis at 480 K for four different gate-voltage sweep rates (indicated). (b) Influence of hold voltage on hysteretic behavior. In each panel, the gate voltage was first swept from −40 to +80 V, following which it was stopped at some intermediate voltage (Vghold, values indicated), and the time-dependent decay of the current was then measured over an interval of 18,000 s. Following this the sweep was resumed and the gate voltage returned to −40 V. (c) Time-decay of the drain current measured during the hold stage of the experiments described in (b).
this process that we attribute to the current jump observed when sweeping gate voltage upward. This picture is consistent with Figure 2, which shows that either making Vghold more negative or increasing the hold time forces the current jump to more-positive Vg. Since either of these processes should result in the injection of more negative charge, it is natural that a larger positive gate bias should be needed to tilt the bands back to a position where the stored charge can then be driven out of the oxide. On the downward portion of the gate sweep the bands are initially aligned as in panel (3) of Figure 1c, favoring electron injection into traps16 at the MoS2/SiO2 interface. As the gate voltage eventually becomes negative, the band alignment reverses and injection into the interface states is suppressed. Instead, injection into the gate oxide once again becomes favored as we return to an alignment close to panel (1) of Figure 1c. The sudden decrease of current by 2 orders of magnitude, observed (inset to Figure 1b) on the down sweep below Vg = −20 V, appears to be consistent with the effect of this injection. According to this picture, then, the hysteresis arises from the need to reach a sufficient negative gate voltage to store excess electrons in the gate oxide; when sweeping up this charge is already present and the FET current is suppressed, whereas sweeping down it is necessary to reach strongly negative gate voltage to induce the electron storage.
intermediate gate voltage (Vghold) and monitor the timedependent variation of Id for several hours before resuming the sweep. Examples of the overall current changes induced by the holding action are shown in the figure, while in Figure 3c we plot the time-dependent current variations obtained at various Vghold. When stopping at positive Vghold a slow decay of the current is observed, over a characteristic time of many hours. For negative Vghold, however, the current decreases much more quickly, on a time scale that is shorter by orders of magnitude. Based on our results, we propose the following model for the thermally assisted hysteresis. Under strong negative biasing, the band profile should resemble that of panel (1) of Figure 1c, favoring electron injection from the gate into the oxide. The injected charge is “stored” in the oxide as long as Vg remains negative, providing an additional repulsive contribution to the gate field. This delays the turn-on of the n-type FET, holding it in its off-state as the gate voltage is swept up to zero (for further details, see the discussion related to Figure 4 that follows). As Vg is increased beyond zero, however, the band alignment evolves to that shown in panel (2), eventually allowing the stored charge to return back to the gate. This results in a rapid increase in the attractive gate field seen by the MoS2, and it is D
DOI: 10.1021/acs.nanolett.6b02905 Nano Lett. XXXX, XXX, XXX−XXX
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right inset of Figure 4a. According to this inset, as the hold time at an initial gate voltage of −30 V is increased, an increasingly positive ΔVT is needed to overlap the resulting transfer curve with the initial one. This result may be interpreted in the following way; by holding the device at negative gate voltage for longer periods, we increasingly load electrons into the gate oxide. Consequently, when sweeping back through zero to positive voltage, a larger voltage is required to discharge the oxide and to cause the onset of current. This in turn may be understood as a shift of VT to more positive Vg, consistent with the behavior plotted in the right inset. A similar effect is indicated in Figure 4b, the main panel of which shows transfer curves obtained for different Vgstart. Once again, as we indicate in the left inset, by introducing an appropriate gate-voltage shift to these different curves they may all be made to collapse such their high-current variations overlap with that obtained for zero holding. The dependence of ΔVT on Vgstart is plotted in the right inset to the figure, which shows that ΔVT again becomes increasingly positive as Vgstart is made more negative. (A threshold behavior is apparent in this figure, suggesting that the oxide tunneling only onsets once Vgstart is made more negative than −20 V, consistent with the observations of Figure 2a). As a comment we note that a threshold shift of 10 V in either Figure 4a or b implies an accumulated charge of ∼1012/cm2 (assuming this charge to be located at the Si/SiO2 interface). This value is quite consistent28 with the known interface trap density at Si/SiO2 interfaces. While the threshold-voltage shifts demonstrated in Figure 4 do appear to provide a connection to conventional floating-gate technology,29,30 they nonetheless differ crucially in that, in flash memory, charge injection occurs from the FET channel due to its high drain bias. We rule out such a mechanism here, as discussed in more detail in the Supporting Information. An additional point that should also be emphasized concerns the role of gate leakage in these devices. On the one hand, this is the essential process that drives the observation of the hightemperature hysteretic behavior. While the leakage increases with increasing temperature, it must nonetheless be emphasized that the current associated with it always remains several orders of magnitude smaller than the drain current, even at the highest temperatures (see Supporting Information). Key to the observation of the hysteresis reported here is the use of monolayer MoS2 as the FET channel. To demonstrate this point, in the Supporting Information we present the results of a similar study of thermally assisted hysteresis, for a device realized from bilayer material. While the transfer curve of this device also shows a thermally-assisted hysteresis, its magnitude is very much weaker than that exhibited by the monolayer FETs. We attribute this difference to improved screening in the bilayer system; much like graphene, the effectiveness of screening in MoS2 is known31−34 to decrease significantly when its thickness is reduced to the monolayer level. Under such conditions, it is therefore reasonable that monolayer devices should exhibit such a pronounced sensitivity to charging events in the gate oxide. Finally, in Figure 5 we show how it is possible to make use of the thermally-assisted hysteresis to implement nonvolatile memory operation. The memory function was achieved by using appropriate regions of the transfer curves to define the RESET, READ, and WRITE operations (Figure 5a). The RESET operation takes the device to a gate voltage of −40 V, following which a drain current close to zero is obtained when the READ operation is performed at Vg = 0 V (see Figure 5b).
Important support for this model of charge exchange with the gate oxide is provided by the observation of a related current discontinuity in the high-temperature transfer curves of graphene-on-SiO2 devices (see ref 26 and the Supporting Information). Due to the gapless nature of the graphene, however, the associated current modulation exhibited by such devices is much weaker than that found here. With regards to the role of temperature in the abovementioned processes, an important clue is provided by the data of Figure 1a. Here we see that, in the temperature range from 200−300 K, there is no significant hysteresis in the transfer curves, indicating that, for these temperatures at least, there must be negligible charge storage within the gate oxide. Consequently, the emergence of the hysteresis at higher temperatures must be related to the onset of electron injection into the oxide. The essential idea here is as follows; at room temperature, carriers in the gate should have insufficient energy to access deep traps within the oxide. At higher temperatures (400−500 K), however, the increased thermal energy available in the system should allow these sites to participate in carrier trapping/detrapping, resulting in the observation of the thermally-assisted hysteresis. Support for this picture is provided by our observation in the Supporting Information that the pronounced current jump observed when passing through zero gate voltage shows an activated dependence on temperature. The activation energy associated with this process is estimated to be ∼130 meV, an energy scale that we attribute to the minimum barrier that must be overcome in order to exchange charge between the gate and deep traps in the SiO2 (see the Supporting Information). The picture developed above can account for the timedependent variations observed in Figure 3. With Vghold > 0, the observed decay of current (Figure 3c) should arise from the steady injection of MoS2 electrons into interfacial traps. This results in a repulsive gating of the FET channel, which we observe as the slow resulting decay of the drain current. For negative Vghold, however, the situation is different. The band alignment corresponds to that of panel (1) of Figure 1c, favoring electron injection into the gate oxide. This once again yields a time-dependent decay of the drain current, although, as is apparent in Figure 3c, this process occurs much more quickly than the slow charging of interfacial traps observed for positive Vghold. (It should be mentioned that, while this alignment also favors the release of electrons from the SiO2/MoS2 interface, our results suggest that this process should be less important than the charge injection from the gate.) The nonvolatile functionality described above resembles that in floating-gate memories,28,29 where charge injection onto the floating-gate node induces a shift in the threshold voltage (VT) of an integrated FET. The memory effects that we discuss may also be interpreted in terms of a shift of VT, as we illustrate in Figure 4. In the main panel of Figure 4a, we show transfer curves measured after first holding the device for various times, and at different gate voltages, prior to the gate sweep. While these curves appear to show little connection, in the left inset we replot the data to show how they may be collapsed onto one another by the introduction of an appropriate gate-voltage shift (ΔVT). The procedure by which this figure was obtained is as follows. After subjecting the device to any specific holding condition, the required shift of its transfer curve was inferred by forcing its current at large gate voltages to overlap with that obtained (black line in Figure 4a) prior to the holding process. In this way we were able to obtain the ΔVT data plotted in the E
DOI: 10.1021/acs.nanolett.6b02905 Nano Lett. XXXX, XXX, XXX−XXX
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strongly sensitive response to the charge-injection process. By exploiting the full features of the hysteretic transfer curves, programmable memory operation was furthermore demonstrated. While our devices are by no means optimized in terms of their operational characteristics, the essential principles demonstrated here point the way to a new class of thermallyassisted memories based on atomically thin 2D semiconductors.
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ASSOCIATED CONTENT
S Supporting Information *
The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.6b02905. Additional characterization of the thermally assisted hysteresis (PDF)
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AUTHOR INFORMATION
Corresponding Author
*E-mail: jbird@buffalo.edu. Phone: +1 (716) 645-1015.
Figure 5. Programmable memory operation based on the thermally assisted, hysteretic transfer curve. (a) The transfer curve used to implement the memory function shown in (b). (b) The upper plot shows the gate-voltage sequence applied to the device, while the lower one shows the resulting variation of the drain current measured in response to this sequence. The measurements in panels (a) and (b) were performed for the following conditions: Vd = 0.5 V, T = 490 K, and sweep rate = 0.5 V/s.
Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS Research at Buffalo was supported by the U.S. Department of Energy, Office of Basic Energy Sciences, Division of Materials Sciences and Engineering, under Award DE-FG02-04ER46180, while that at Chiba was supported in part by the JSPS Kakenhi Grant No. JP25067005 on Innovative Areas “Science of Atomic Layers”. CVD growth of MoS2 material at Rice was supported in part by the Army Research Office (MURI grant W911NF11-1-0362). R.S. acknowledges support from the Thailand Research Fund (contract # TRG5880012).
(The current measured after the RESET is actually at the level of ∼1 μA, reflecting the fact that the gate voltage at which the READ is performed lies toward the end of the working range of the hysteresis window. In principle it should be possible to suppress the off-state READ current even further by working at a more negative gate voltage, Vg = −10 V, for example, or by increasing the duration of the RESET. We have not made any attempt to optimize this aspect of our investigations, however.) If the WRITE operation is then implemented at Vg = +40 V, returning to Vg = 0 V to perform the READ now yields a nonzero drain current (Id > 10 μA, see Figure 5b). This is the essential basis of the memory operation. Although the structure of our system is by no means tailored to maximize the efficacy of the memory mechanism, approaches such as van der Waals stacking21,35,36 may allow such optimization to be achieved in the future. In any practical implementation, it will be necessary to develop approaches to locally, and selectively, heat the memory cell to be programmed. This could be achieved, for example, by first using a large drain current to heat the active transistor in an array, following which its thermally-assisted memory function could be quickly implemented. The advent of such memories based on 2D semiconductors represents a useful addition to the suite of functionalities offered by these materials. In conclusion, we have demonstrated a novel form of thermally assisted hysteresis in the transfer curves of monolayer MoS2 FETs, characterized by the appearance of a large gatevoltage window and distinct current levels. The hysteresis emerges for temperatures in excess of 400 K, and from studies in which the gate-voltage sweep parameters are varied appears to be related to charge injection into the SiO2 gate dielectric. The thermally assisted memory is strongly suppressed in equivalent measurements performed on transistors implemented from bilayer MoS2, suggesting that weak screening in the monolayer system plays a vital role in generating its
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DOI: 10.1021/acs.nanolett.6b02905 Nano Lett. XXXX, XXX, XXX−XXX
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DOI: 10.1021/acs.nanolett.6b02905 Nano Lett. XXXX, XXX, XXX−XXX
